Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22180

1

T1

20

T2

63

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

3497

1

T2

4

T3

1

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19804

1

T1

20

T2

60

T3

1

auto[1]

5873

1

T2

7

T5

1

T7

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	347	1			T9	12		T90	7		T220	6
values[0]	57	1			T149	16		T223	12		T238	9
values[1]	480	1			T5	1		T13	1		T54	22
values[2]	472	1			T13	1		T49	37		T50	1
values[3]	849	1			T40	2		T55	6		T26	7
values[4]	608	1			T3	1		T49	13		T27	12
values[5]	3025	1			T5	2		T8	13		T11	15
values[6]	524	1			T4	19		T8	10		T12	10
values[7]	692	1			T9	17		T12	12		T52	7
values[8]	601	1			T2	7		T15	11		T27	10
values[9]	1094	1			T4	16		T7	20		T12	5
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	516	1			T5	1		T13	2		T49	37
values[1]	488	1			T50	1		T51	2		T53	4
values[2]	822	1			T40	2		T55	6		T26	7
values[3]	2980	1			T3	1		T5	1		T11	15
values[4]	612	1			T5	1		T8	13		T50	8
values[5]	584	1			T4	19		T8	10		T9	17
values[6]	683	1			T2	4		T12	12		T52	7
values[7]	586	1			T2	3		T90	13		T54	2
values[8]	1097	1			T9	12		T12	5		T90	7
values[9]	213	1			T4	16		T7	20		T50	12
minimum	17096	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	21		T51	1		T53	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T5	1		T13	2		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T50	1		T51	1		T53	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	14		T155	15		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T55	6		T104	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T40	2		T26	4		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T5	1		T11	2		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	1		T62	3		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T50	8		T51	12		T52	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	1		T8	2		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	13		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T55	15		T15	1		T26	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	1		T52	7		T29	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	3		T55	3		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	3		T27	1		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T90	1		T54	1		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T9	1		T90	1		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T12	1		T62	9		T43	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T4	7		T145	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T7	11		T50	12		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16846	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T143	1		T149	16		T287	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	16		T51	1		T165	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T147	10		T224	9		T282	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T51	1		T196	7		T272	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T54	11		T183	10		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T145	7		T256	12		T183	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	3		T230	21		T46	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T11	13		T49	6		T150	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T62	13		T28	11		T183	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T51	10		T163	2		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	11		T193	8		T272	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T4	6		T8	9		T9	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	13		T156	6		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	11		T29	27		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	1		T15	3		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T27	9		T242	1		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T90	12		T54	1		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	11		T90	6		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	4		T62	7		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T4	9		T145	11		T226	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	9		T147	10		T227	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T40	2		T54	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T238	8		T281	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T9	1		T90	1		T220	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T148	1		T227	11		T228	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T302	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T149	16		T223	12		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T54	12		T165	6		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T5	1		T13	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T49	21		T50	1		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	1		T54	14		T155	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T55	6		T104	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T40	2		T26	4		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T49	7		T27	1		T28	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	1		T28	14		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T5	1		T11	2		T150	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	1		T8	2		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	13		T8	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T55	15		T15	1		T26	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	1		T12	1		T52	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T55	3		T146	1		T221	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	3		T27	1		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	3		T15	8		T141	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T4	7		T28	2		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T7	11		T12	1		T50	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T9	11		T90	6		T273	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T227	11		T228	11		T170	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T238	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T54	10		T165	7		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T147	10		T282	1		T283	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	16		T51	2		T145	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T54	11		T183	10		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T145	7		T256	12		T183	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T26	3		T46	3		T229	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	6		T27	11		T28	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T28	11		T230	21		T236	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T11	13		T150	28		T30	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T8	11		T62	13		T183	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	6		T8	9		T12	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	13		T156	6		T179	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	16		T12	11		T29	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	1		T257	4		T228	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T27	9		T42	3		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	1		T15	3		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	9		T145	11		T177	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	9		T12	4		T90	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	17		T51	2		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	1		T13	2		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T50	1		T51	2		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T54	12		T155	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T55	1		T104	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T40	2		T26	4		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T5	1		T11	15		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T62	14		T28	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T50	1		T51	11		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T8	13		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	7		T8	10		T9	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T55	1		T15	1		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	12		T52	1		T29	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	3		T55	1		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	3		T27	10		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T90	13		T54	2		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T9	12		T90	7		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T12	5		T62	8		T43	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T4	10		T145	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T7	10		T50	1		T147	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T143	1		T149	1		T287	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T49	20		T53	10		T165	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T282	11		T283	3		T215	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T53	3		T176	6		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T54	13		T155	14		T183	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T55	5		T183	22		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	3		T230	14		T46	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T49	6		T28	18		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T62	2		T28	13		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T50	7		T51	11		T52	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T166	6		T241	4		T193	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	12		T49	9		T53	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	14		T26	12		T221	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T52	6		T29	20		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T55	2		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	1		T240	22		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	1		T266	6		T223	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T42	3		T220	5		T177	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T62	8		T43	4		T228	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T4	6		T285	4		T335	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T7	10		T50	11		T227	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T54	11		T245	15		T302	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T149	15		T287	2		T223	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	12		T90	7		T220	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T148	1		T227	13		T228	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T302	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T149	1		T223	1		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T54	11		T165	8		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T5	1		T13	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	17		T50	1		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T13	1		T54	12		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T55	1		T104	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T40	2		T26	4		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	7		T27	12		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	1		T28	12		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	1		T11	15		T150	31
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T5	1		T8	13		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	7		T8	10		T12	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T55	1		T15	1		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	17		T12	12		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T55	1		T146	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	3		T27	10		T42	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	3		T15	8		T141	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	10		T28	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T7	10		T12	5		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T220	5		T160	8		T37	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T227	9		T228	16		T191	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T302	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T149	15		T223	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T54	11		T165	5		T178	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T282	11		T287	2		T283	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	20		T53	13		T176	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T54	13		T155	14		T183	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	5		T153	11		T183	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	3		T46	3		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T49	6		T28	18		T235	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	13		T155	9		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T50	7		T103	11		T108	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T62	2		T183	15		T166	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	12		T49	9		T51	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T55	14		T26	12		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T52	6		T29	20		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T55	2		T221	10		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	3		T240	22		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	1		T15	3		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T4	6		T28	1		T177	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	10		T50	11		T62	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10