Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20413

1

T1

20

T2

63

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

5264

1

T2

4

T4

16

T5

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20096

1

T1

20

T2

67

T3

1

auto[1]

5581

1

T4

35

T5

2

T8

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	279	1			T5	1		T50	12		T52	12
values[0]	37	1			T26	7		T193	11		T312	1
values[1]	628	1			T4	16		T9	17		T49	17
values[2]	707	1			T7	20		T9	12		T13	1
values[3]	683	1			T5	1		T8	10		T90	7
values[4]	794	1			T8	1		T50	8		T51	22
values[5]	560	1			T12	5		T13	1		T51	2
values[6]	674	1			T2	3		T3	1		T4	19
values[7]	537	1			T2	4		T5	1		T12	12
values[8]	540	1			T49	37		T53	16		T62	16
values[9]	3310	1			T11	15		T12	10		T49	13
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	653	1			T7	20		T9	17		T13	1
values[1]	2987	1			T5	1		T9	12		T11	15
values[2]	621	1			T8	10		T51	22		T90	7
values[3]	758	1			T8	1		T50	8		T55	6
values[4]	641	1			T4	19		T12	5		T13	1
values[5]	564	1			T2	7		T3	1		T8	12
values[6]	661	1			T5	1		T12	12		T40	2
values[7]	596	1			T49	37		T62	16		T143	1
values[8]	1042	1			T5	1		T49	13		T50	12
values[9]	83	1			T12	10		T15	1		T147	5
minimum	17071	1			T1	20		T2	60		T4	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	11		T9	1		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T27	1		T43	2		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	1		T144	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1522	1			T5	1		T11	2		T150	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T90	1		T26	13		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T51	12		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T142	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T50	8		T55	6		T218	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	13		T13	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T51	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	3		T3	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	3		T8	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T54	1		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T40	2		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	21		T62	9		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	10		T239	10		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T49	7		T52	12		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	1		T50	12		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T12	1		T166	7		T336	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T15	1		T147	1		T168	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16815	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T4	7		T49	10		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	9		T9	16		T26	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T27	9		T43	1		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	11		T236	11		T283	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1066	1			T11	13		T150	28		T163	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T90	6		T26	13		T145	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T8	9		T51	10		T54	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T225	14		T141	3		T273	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T218	6		T157	16		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	6		T147	10		T268	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	4		T51	1		T156	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T228	11		T169	7		T215	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	1		T8	11		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	11		T54	1		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T90	12		T62	13		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	16		T62	7		T183	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T179	10		T223	8		T293	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T49	6		T15	3		T183	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	1		T28	11		T29	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T12	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T147	4		T168	2		T337	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T40	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T4	9		T49	7		T27	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T52	12		T153	12		T48	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T5	1		T50	12		T55	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T26	4		T306	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T193	3		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	1		T28	19		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	7		T49	10		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	11		T9	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T163	1		T165	6		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T90	1		T26	13		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	1		T8	1		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T142	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	8		T51	12		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T219	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T51	1		T55	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	3		T3	1		T4	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T104	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T50	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	3		T5	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	21		T62	9		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T53	16		T320	18		T239	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T12	1		T49	7		T55	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1584	1			T11	2		T150	3		T86	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T48	1		T226	12		T169	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T147	10		T304	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T26	3		T306	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T193	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	16		T28	13		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	9		T49	7		T27	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	9		T9	11		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T163	2		T165	7		T227	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T90	6		T26	13		T145	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	9		T54	21		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T225	14		T273	3		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T51	10		T43	4		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T147	10		T141	3		T268	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	4		T51	1		T141	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	6		T228	11		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	11		T156	6		T46	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	11		T54	1		T272	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	1		T90	12		T62	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T49	16		T62	7		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T320	15		T179	10		T193	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T12	9		T49	6		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1095	1			T11	13		T150	28		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	10		T9	17		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	10		T43	2		T145	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	12		T144	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1414	1			T5	1		T11	15		T150	31
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T90	7		T26	14		T145	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	10		T51	11		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T142	1		T225	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	1		T55	1		T218	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	7		T13	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	5		T51	2		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	3		T3	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	3		T8	12		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	12		T54	2		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T40	2		T90	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	17		T62	8		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T155	1		T239	1		T179	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T49	7		T52	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T50	1		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T12	10		T166	1		T336	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T15	1		T147	5		T168	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16976	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T4	10		T49	8		T27	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	10		T26	3		T28	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T43	1		T252	12		T338	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T236	10		T180	14		T287	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1174	1			T54	13		T165	5		T103	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T26	12		T240	10		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T51	11		T53	10		T54	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T178	10		T193	21		T170	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	7		T55	5		T218	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	12		T266	16		T268	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	2		T228	13		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T52	6		T228	16		T215	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	1		T196	7		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	1		T242	1		T272	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T62	2		T220	5		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	20		T62	8		T183	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T155	9		T239	9		T223	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T49	6		T52	11		T55	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T50	11		T53	18		T55	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T166	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T168	10		T337	10		T332	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T229	1		T37	8		T339	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T4	6		T49	9		T42	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T52	1		T153	1		T48	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T5	1		T50	1		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T26	4		T306	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T193	9		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	17		T28	14		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	10		T49	8		T27	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	10		T9	12		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T163	3		T165	8		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T90	7		T26	14		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T8	10		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T142	1		T225	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	1		T51	11		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	1		T219	1		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	5		T51	2		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	3		T3	1		T4	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	12		T104	1		T156	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	12		T50	1		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	3		T5	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	17		T62	8		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T53	1		T320	16		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T12	10		T49	7		T55	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T11	15		T150	31		T86	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T52	11		T153	11		T48	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T50	11		T55	14		T241	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T26	3		T306	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T193	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	18		T166	6		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	6		T49	9		T42	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	10		T235	6		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T165	5		T227	9		T180	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	12		T240	10		T149	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	10		T54	24		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T178	10		T193	21		T170	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	7		T51	11		T43	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T266	16		T268	7		T296	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T55	5		T141	12		T295	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	12		T52	6		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	2		T250	2		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T28	1		T272	9		T245	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	1		T62	2		T220	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	20		T62	8		T282	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T53	15		T320	17		T239	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T49	6		T55	2		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1239	1			T53	3		T28	13		T29	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10