Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	10		T51	2		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T54	12		T62	22		T147	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T8	1		T11	15		T150	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T90	7		T54	2		T27	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	10		T12	5		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	1		T51	2		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	1		T40	1		T165	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	3		T5	1		T55	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T49	17		T42	8		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	10		T9	17		T28	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	12		T26	4		T145	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	10		T13	1		T163	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	12		T13	1		T49	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T90	13		T28	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T52	1		T147	5		T253	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	1		T4	7		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	3		T9	12		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T55	1		T219	1		T177	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T254	3		T255	1		T186	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T26	14		T145	12		T252	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16946	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T52	11		T53	10		T220	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T54	13		T62	10		T183	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T103	11		T108	14		T218	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	1		T155	14		T266	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	6		T50	11		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	15		T29	10		T178	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	7		T165	5		T257	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T55	5		T43	4		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	20		T42	3		T242	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	10		T28	31		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	3		T221	12		T183	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T55	2		T196	7		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T49	15		T51	11		T239	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T28	1		T183	15		T223	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T52	6		T240	10		T149	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	12		T53	3		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	1		T54	11		T29	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T55	14		T177	15		T235	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T254	7		T258	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T26	12		T252	12		T259	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T215	7		T267	15		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T2	1		T41	3		T56	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T260	12		T261	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T179	11		T60	15		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T262	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	10		T51	2		T52	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T62	22		T147	11		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T11	15		T150	31		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	1		T54	14		T27	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	10		T8	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T51	2		T90	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	1		T165	8		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	3		T29	11		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	17		T50	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	1		T8	10		T9	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	12		T145	18		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	10		T13	1		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	12		T13	1		T49	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T90	13		T143	1		T196	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T52	1		T40	2		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	1		T5	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T2	3		T9	12		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T4	7		T55	1		T26	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16519	1			T1	20		T2	59		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T60	5		T264	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T52	11		T241	13		T268	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T62	10		T183	22		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T53	10		T103	11		T108	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	15		T54	13		T43	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	6		T15	3		T218	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T155	14		T159	5		T269	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	11		T165	5		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T29	10		T240	12		T228	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	20		T50	7		T42	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T55	5		T28	18		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T183	18		T242	1		T191	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	10		T55	2		T28	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T49	15		T51	11		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T196	7		T221	10		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T52	6		T240	20		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	3		T28	1		T183	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T54	11		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	12		T55	14		T26	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10