Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22450

1

T1

20

T2

63

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T2

4

T4

19

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19856

1

T1

20

T2

63

T3

1

auto[1]

5821

1

T2

4

T7

20

T8

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T219	1		T184	19		T270	25
values[0]	32	1			T217	1		T92	7		T271	23
values[1]	678	1			T49	37		T51	2		T52	12
values[2]	621	1			T5	1		T51	2		T52	7
values[3]	659	1			T49	17		T90	13		T53	4
values[4]	709	1			T12	12		T50	1		T26	26
values[5]	607	1			T12	5		T90	7		T55	9
values[6]	759	1			T4	35		T8	1		T9	12
values[7]	683	1			T8	10		T50	12		T51	22
values[8]	2840	1			T2	4		T5	1		T11	15
values[9]	1116	1			T2	3		T3	1		T5	1
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	781	1			T5	1		T49	37		T51	2
values[1]	660	1			T51	2		T40	1		T90	13
values[2]	708	1			T49	17		T29	21		T218	13
values[3]	604	1			T26	26		T29	1		T43	3
values[4]	662	1			T4	16		T8	1		T12	17
values[5]	805	1			T4	19		T9	12		T13	1
values[6]	2851	1			T8	10		T11	15		T150	31
values[7]	735	1			T2	4		T5	1		T8	12
values[8]	804	1			T2	3		T5	1		T9	17
values[9]	117	1			T3	1		T7	20		T104	1
minimum	16950	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T51	1		T52	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T49	21		T52	12		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	1		T26	4		T28	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T51	1		T40	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	10		T29	11		T218	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T218	1		T243	4		T266	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T26	13		T145	1		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	1		T43	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	7		T8	1		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T90	1		T53	11		T55	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T49	7		T196	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	13		T9	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T8	1		T11	2		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	12		T40	2		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T8	1		T54	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	3		T53	16		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	3		T9	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T13	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T3	1		T104	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T7	11		T146	1		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16791	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T272	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	1		T62	7		T27	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T49	16		T230	21		T46	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T26	3		T28	13		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T51	1		T90	12		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	7		T29	10		T218	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T243	3		T268	8		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	13		T145	17		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	1		T273	11		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	9		T12	15		T62	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T90	6		T27	11		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	6		T177	11		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	6		T9	11		T54	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T8	9		T11	13		T150	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T51	10		T145	11		T257	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	11		T54	11		T227	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	1		T163	2		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	16		T12	9		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T141	3		T179	8		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T274	11		T275	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T7	9		T161	1		T184	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T272	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T219	1		T184	9		T270	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T217	1		T92	4		T271	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T51	1		T27	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T49	21		T52	12		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T52	7		T62	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T51	1		T40	1		T43	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	10		T26	4		T29	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T90	1		T53	4		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T50	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	1		T219	1		T243	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T55	6		T183	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T90	1		T55	3		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	7		T8	1		T49	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	13		T9	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	1		T50	12		T28	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	12		T40	2		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T5	1		T11	2		T150	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	3		T163	1		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T2	3		T3	1		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T5	1		T7	11		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T184	10		T270	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T92	3		T271	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T51	1		T27	9		T147	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	16		T230	21		T46	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T62	7		T28	13		T145	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	1		T43	4		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T49	7		T26	3		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T90	12		T54	1		T268	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	11		T26	13		T145	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T243	3		T273	11		T179	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	4		T183	18		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T90	6		T15	3		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	9		T49	6		T62	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	6		T9	11		T54	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	9		T28	11		T29	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T51	10		T145	11		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T11	13		T150	28		T54	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	1		T163	2		T42	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T8	11		T9	16		T12	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	9		T141	3		T179	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T51	2		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T49	17		T52	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	1		T26	4		T28	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T51	2		T40	1		T90	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	8		T29	11		T218	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T218	1		T243	4		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	14		T145	18		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	1		T43	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	10		T8	1		T12	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T90	7		T53	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	7		T196	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	7		T9	12		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T8	10		T11	15		T150	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	11		T40	2		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T8	12		T54	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	3		T53	1		T163	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T2	3		T9	17		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T13	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T3	1		T104	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T7	10		T146	1		T161	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16929	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T272	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T52	6		T62	8		T176	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	20		T52	11		T155	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	3		T28	18		T45	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T53	3		T43	4		T183	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	9		T29	10		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T243	3		T266	8		T239	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T26	12		T228	16		T243	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T43	1		T223	8		T276	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	6		T50	7		T55	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T53	10		T55	2		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T49	6		T177	15		T228	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	12		T54	11		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T50	11		T55	14		T165	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T51	11		T153	11		T166	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T54	13		T28	1		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T53	15		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T196	7		T229	1		T266	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T166	6		T240	10		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T275	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T7	10		T161	1		T184	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T272	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T219	1		T184	11		T270	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T217	1		T92	5		T271	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	2		T27	10		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	17		T52	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T52	1		T62	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T51	2		T40	1		T43	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	8		T26	4		T29	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T90	13		T53	1		T54	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	12		T50	1		T26	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T142	1		T219	1		T243	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	5		T55	1		T183	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T90	7		T55	1		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	10		T8	1		T49	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	7		T9	12		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T8	10		T50	1		T28	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	11		T40	2		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T5	1		T11	15		T150	31
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	3		T163	3		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T2	3		T3	1		T8	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	1		T7	10		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T184	8		T270	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T92	2		T271	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T176	6		T45	2		T46	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T49	20		T52	11		T155	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	6		T62	8		T28	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T43	4		T183	18		T277	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	9		T26	3		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T53	3		T239	20		T268	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T26	12		T155	9		T228	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T243	3		T266	8		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T55	5		T183	15		T243	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	2		T15	3		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	6		T49	6		T50	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	12		T53	10		T54	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T50	11		T28	13		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T51	11		T153	11		T241	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T54	13		T55	14		T165	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	1		T42	3		T166	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T227	9		T241	4		T266	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	10		T53	15		T166	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10