Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22085

1

T1

20

T2

63

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3592

1

T2

4

T3

1

T4

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19879

1

T1

20

T2

60

T3

1

auto[1]

5798

1

T2

7

T5

1

T7

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T9	12		T269	11		-	-
values[0]	44	1			T149	16		T180	1		T223	12
values[1]	523	1			T5	1		T13	1		T54	22
values[2]	489	1			T13	1		T49	37		T50	1
values[3]	781	1			T40	2		T26	7		T145	8
values[4]	631	1			T3	1		T49	13		T62	16
values[5]	3002	1			T5	2		T8	13		T11	15
values[6]	576	1			T4	19		T8	10		T49	17
values[7]	695	1			T2	4		T9	17		T12	12
values[8]	555	1			T2	3		T15	11		T27	10
values[9]	1430	1			T4	16		T7	20		T12	5
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	712	1			T5	1		T13	2		T49	37
values[1]	534	1			T50	1		T51	2		T53	4
values[2]	740	1			T40	2		T55	6		T26	7
values[3]	2953	1			T3	1		T5	1		T8	12
values[4]	614	1			T5	1		T8	1		T50	8
values[5]	544	1			T4	19		T8	10		T9	17
values[6]	779	1			T12	12		T49	17		T52	7
values[7]	623	1			T2	7		T90	13		T54	2
values[8]	942	1			T7	20		T12	5		T90	7
values[9]	286	1			T4	16		T9	12		T50	12
minimum	16950	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	21		T51	1		T53	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T13	2		T54	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T50	1		T51	1		T53	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T148	1		T183	19		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T55	6		T104	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	2		T26	4		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T11	2		T49	7		T150	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	1		T5	1		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T50	8		T51	12		T52	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T8	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	13		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T15	1		T26	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T49	10		T52	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T15	8		T29	11		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	3		T27	1		T240	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	3		T90	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T90	1		T220	6		T177	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T7	11		T12	1		T62	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T9	1		T145	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T4	7		T50	12		T227	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16802	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	16		T51	1		T165	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T54	11		T145	17		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T51	1		T196	7		T272	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T183	10		T236	11		T237	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T145	7		T256	12		T183	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T26	3		T230	21		T229	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T11	13		T49	6		T150	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	11		T62	13		T28	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T51	10		T163	2		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T243	10		T193	8		T272	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T4	6		T8	9		T9	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	9		T26	13		T147	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	11		T49	7		T29	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	3		T29	10		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T27	9		T242	1		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T90	12		T54	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T90	6		T177	11		T273	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	9		T12	4		T62	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T9	11		T145	11		T147	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T4	9		T227	11		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T40	2		T54	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T9	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T269	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T149	16		T180	1		T223	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T54	12		T165	6		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	1		T13	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T49	21		T50	1		T51	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T13	1		T54	14		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T145	1		T153	12		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	2		T26	4		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	7		T27	1		T28	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T62	3		T28	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T11	2		T150	3		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	2		T8	2		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	13		T8	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T40	1		T15	1		T26	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	1		T12	1		T52	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	3		T29	11		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	3		T27	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	8		T28	2		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T90	1		T145	1		T220	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	471	1			T4	7		T7	11		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T9	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T269	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T280	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T281	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T54	10		T165	7		T178	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T147	10		T282	1		T283	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	16		T51	2		T196	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T54	11		T145	17		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T145	7		T256	12		T183	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	3		T229	7		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	6		T27	11		T28	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T62	13		T28	11		T230	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T11	13		T150	28		T30	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	11		T12	9		T183	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	6		T8	9		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	13		T147	4		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	16		T12	11		T29	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T29	10		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T27	9		T242	1		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	3		T42	3		T141	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T90	6		T145	11		T177	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T4	9		T7	9		T12	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T49	17		T51	2		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T13	2		T54	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T50	1		T51	2		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T148	1		T183	11		T278	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	1		T104	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	2		T26	4		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T11	15		T49	7		T150	31
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T5	1		T8	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	1		T51	11		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T8	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	7		T8	10		T9	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	10		T15	1		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	12		T49	8		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T15	8		T29	11		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	3		T27	10		T240	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	3		T90	13		T54	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T90	7		T220	1		T177	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T7	10		T12	5		T62	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T9	12		T145	12		T147	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T4	10		T50	1		T227	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16939	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T49	20		T53	10		T165	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	13		T149	15		T282	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T53	3		T176	6		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T183	18		T166	6		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T55	5		T183	22		T46	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	3		T230	14		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T49	6		T28	18		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T62	2		T28	13		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T50	7		T51	11		T52	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T166	6		T241	4		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	12		T53	15		T55	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T26	12		T221	10		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T49	9		T52	6		T55	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	3		T29	10		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T240	22		T241	4		T266	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T28	1		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T220	5		T177	15		T239	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	10		T62	8		T42	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T284	15		T285	4		T286	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T4	6		T50	11		T227	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T54	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T9	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T269	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T280	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T149	1		T180	1		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T54	11		T165	8		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	1		T13	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	17		T50	1		T51	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	1		T54	12		T145	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T145	8		T153	1		T256	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T40	2		T26	4		T196	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T49	7		T27	12		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	1		T62	14		T28	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T11	15		T150	31		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T5	2		T8	13		T12	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	7		T8	10		T49	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	1		T15	1		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	17		T12	12		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	3		T29	11		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	3		T27	10		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	8		T28	1		T42	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T90	7		T145	12		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	446	1			T4	10		T7	10		T12	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T149	15		T223	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T54	11		T165	5		T178	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T282	11		T287	2		T283	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	20		T53	13		T55	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T54	13		T183	18		T166	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T153	11		T183	22		T46	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T26	3		T229	1		T236	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	6		T28	18		T235	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T62	2		T28	13		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T103	11		T108	14		T218	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T183	15		T166	6		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	12		T49	9		T50	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T26	12		T243	11		T170	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T52	6		T55	2		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	1		T29	10		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T240	10		T242	1		T252	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	3		T28	1		T42	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T220	5		T177	15		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T4	6		T7	10		T50	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10