Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22361

1

T1

20

T2

60

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3316

1

T2

7

T4

19

T7

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T1

20

T2

67

T4

35

auto[1]

5537

1

T3

1

T7

20

T9

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T12	12		T243	22		T248	10
values[0]	38	1			T231	1		T233	23		T37	1
values[1]	593	1			T54	25		T55	3		T29	1
values[2]	723	1			T8	1		T51	22		T52	12
values[3]	560	1			T9	12		T12	10		T90	7
values[4]	2789	1			T2	3		T3	1		T5	1
values[5]	595	1			T5	1		T55	6		T28	32
values[6]	683	1			T4	16		T5	1		T7	20
values[7]	849	1			T8	12		T12	5		T50	8
values[8]	581	1			T13	1		T49	37		T50	1
values[9]	1294	1			T2	4		T4	19		T13	1
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	845	1			T51	22		T54	25		T55	3
values[1]	661	1			T8	1		T52	12		T90	13
values[2]	488	1			T2	3		T3	1		T9	12
values[3]	2854	1			T5	2		T11	15		T12	10
values[4]	567	1			T55	6		T26	7		T28	34
values[5]	737	1			T4	16		T5	1		T8	22
values[6]	799	1			T7	20		T9	17		T50	8
values[7]	746	1			T4	19		T13	1		T49	37
values[8]	922	1			T2	4		T12	12		T13	1
values[9]	127	1			T52	7		T104	1		T241	5
minimum	16931	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T55	3		T29	1		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T51	12		T54	14		T143	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T62	3		T146	1		T44	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T52	12		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T3	1		T40	2		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	3		T9	1		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T5	2		T11	2		T150	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T42	8		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	6		T28	21		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	4		T220	6		T176	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	7		T5	1		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T50	12		T53	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T50	8		T62	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	11		T51	1		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T13	1		T49	21		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	13		T54	12		T165	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	1		T49	7		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	3		T12	1		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T104	1		T241	5		T294	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T52	7		T178	11		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16791	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T156	6		T276	12		T295	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	10		T54	11		T145	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T62	13		T226	4		T296	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T90	12		T27	9		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T90	6		T43	1		T177	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	11		T54	1		T27	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T11	13		T150	28		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	9		T42	3		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	13		T256	12		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T26	3		T297	10		T298	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	9		T8	20		T29	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	4		T196	7		T147	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	16		T62	7		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	9		T51	1		T183	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T49	16		T51	1		T28	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	6		T54	10		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	6		T163	2		T218	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	1		T12	11		T49	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T174	6		T299	4		T258	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T178	5		T283	1		T170	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T40	2		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T243	12		T248	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T12	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T300	3		T301	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T231	1		T233	14		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T55	3		T29	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T54	14		T143	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T62	3		T146	1		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	1		T51	12		T52	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T90	1		T43	2		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	1		T12	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T3	1		T5	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	3		T42	8		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	1		T55	6		T28	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T220	6		T154	1		T155	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	7		T5	1		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	11		T50	12		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T8	1		T50	8		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T51	1		T53	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T49	21		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T219	1		T196	1		T240	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	1		T49	7		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T2	3		T4	13		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T243	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T12	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T300	7		T301	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T231	2		T269	4		T222	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T54	11		T193	16		T170	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T62	13		T156	6		T276	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	10		T90	12		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T90	6		T43	1		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	11		T12	9		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T11	13		T150	28		T26	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T42	3		T45	2		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T28	13		T16	1		T141	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T147	10		T228	11		T193	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	9		T8	9		T9	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	9		T26	3		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	11		T15	3		T29	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	4		T51	1		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	16		T51	1		T62	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T141	11		T237	1		T290	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T49	6		T163	2		T28	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T2	1		T4	6		T49	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T55	1		T29	1		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T51	11		T54	12		T143	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T62	14		T146	1		T44	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T52	1		T90	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T40	2		T90	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	3		T9	12		T54	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T5	2		T11	15		T150	31
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	10		T42	8		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T55	1		T28	15		T256	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T26	4		T220	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	10		T5	1		T8	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	5		T50	1		T53	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	17		T50	1		T62	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	10		T51	2		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	1		T49	17		T51	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	7		T54	11		T165	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	1		T49	7		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T2	3		T12	12		T49	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T104	1		T241	1		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T52	1		T178	6		T283	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16931	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T55	2		T166	6		T276	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T51	11		T54	13		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T62	2		T166	6		T296	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T52	11		T43	4		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T43	1		T177	15		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T227	9		T48	1		T243	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T26	12		T103	11		T108	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T42	3		T45	2		T228	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T55	5		T28	19		T250	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T26	3		T220	5		T176	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	6		T29	10		T149	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T50	11		T53	18		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	7		T62	8		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	10		T53	10		T55	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T49	20		T28	13		T230	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T4	12		T54	11		T165	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	6		T218	5		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T49	9		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T241	4		T294	6		T174	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T52	6		T178	10		T170	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T243	11		T248	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T12	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T300	8		T301	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T231	1		T233	10		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T55	1		T29	1		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T54	12		T143	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T62	14		T146	1		T156	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	1		T51	11		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T90	7		T43	2		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	12		T12	10		T54	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T3	1		T5	1		T11	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	3		T42	8		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T55	1		T28	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T220	1		T154	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	10		T5	1		T8	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	10		T50	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	12		T50	1		T15	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	5		T51	2		T53	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	1		T49	17		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T219	1		T196	1		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T13	1		T49	7		T163	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T2	3		T4	7		T49	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T243	11		T248	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T300	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T233	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T55	2		T166	6		T252	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T54	13		T153	11		T193	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T62	2		T166	6		T276	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T51	11		T52	11		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T43	1		T177	15		T235	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T227	9		T48	1		T282	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T26	12		T28	1		T103	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T42	3		T176	6		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T55	5		T28	18		T250	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T220	5		T155	14		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	6		T221	12		T149	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	10		T50	11		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T50	7		T15	3		T29	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	25		T55	14		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	20		T62	8		T257	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T240	10		T141	12		T302	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T49	6		T28	13		T218	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	1		T4	12		T49	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10