Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20407

1

T1

20

T2

60

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

5270

1

T2

7

T4

16

T5

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20093

1

T1

20

T2

64

T3

1

auto[1]

5584

1

T2

3

T4

35

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T180	1		T303	6		T304	2
values[0]	69	1			T26	7		T42	11		T43	3
values[1]	547	1			T4	16		T9	17		T49	17
values[2]	753	1			T7	20		T13	1		T163	3
values[3]	702	1			T5	1		T8	10		T9	12
values[4]	729	1			T8	1		T50	8		T51	22
values[5]	659	1			T3	1		T12	5		T13	1
values[6]	541	1			T2	3		T4	19		T8	12
values[7]	587	1			T2	4		T5	1		T12	12
values[8]	613	1			T49	37		T90	13		T53	16
values[9]	3507	1			T5	1		T11	15		T12	10
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	808	1			T4	16		T7	20		T9	17
values[1]	3060	1			T5	1		T8	10		T9	12
values[2]	571	1			T51	22		T90	7		T53	11
values[3]	744	1			T8	1		T50	8		T55	6
values[4]	557	1			T4	19		T12	5		T13	1
values[5]	628	1			T2	7		T3	1		T8	12
values[6]	666	1			T5	1		T12	12		T40	2
values[7]	582	1			T49	37		T62	16		T143	1
values[8]	979	1			T5	1		T49	13		T50	12
values[9]	154	1			T12	10		T53	4		T15	1
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	11		T9	1		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	7		T49	10		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	1		T144	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1548	1			T5	1		T8	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T90	1		T26	13		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T51	12		T53	11		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	1		T142	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T50	8		T55	6		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	13		T13	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T51	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	1		T50	1		T52	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	6		T8	1		T196	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T54	1		T28	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T40	2		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	21		T62	9		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T155	10		T230	1		T243	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T49	7		T52	12		T55	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T50	12		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T12	1		T53	4		T166	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T15	1		T29	11		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	9		T9	16		T26	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	9		T49	7		T27	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	11		T236	11		T283	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1095	1			T8	9		T11	13		T150	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T90	6		T26	13		T145	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T51	10		T183	18		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T225	14		T141	3		T273	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	4		T218	6		T157	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	6		T147	10		T141	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	4		T51	1		T156	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T228	11		T169	7		T215	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	1		T8	11		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	11		T54	1		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T90	12		T62	13		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	16		T62	7		T183	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T243	3		T179	10		T223	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T49	6		T15	3		T183	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	1		T28	11		T29	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T12	9		T303	2		T258	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T29	17		T147	4		T168	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T303	4		T305	17		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T180	1		T304	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T26	4		T268	9		T306	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T42	8		T43	2		T193	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	1		T143	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	7		T49	10		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T7	11		T13	1		T28	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T163	1		T165	6		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	1		T90	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T8	1		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	1		T225	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T50	8		T51	12		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T13	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T51	1		T55	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	13		T52	7		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	3		T8	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	1		T50	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	3		T5	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	21		T62	9		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T90	1		T53	16		T28	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T12	1		T49	7		T52	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1628	1			T5	1		T11	2		T150	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T303	2		T305	16		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T304	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T26	3		T268	8		T306	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T42	3		T43	1		T193	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	16		T145	11		T229	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	9		T49	7		T27	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	9		T28	13		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T163	2		T165	7		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	11		T90	6		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	9		T54	21		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T225	14		T273	3		T178	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	10		T43	4		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	10		T141	14		T288	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	4		T51	1		T178	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	6		T228	11		T268	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T8	11		T156	6		T46	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	11		T54	1		T272	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T62	13		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T49	16		T62	7		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T90	12		T28	11		T243	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T12	9		T49	6		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1091	1			T11	13		T150	28		T51	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T7	10		T9	17		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	10		T49	8		T27	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	12		T144	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1445	1			T5	1		T8	10		T11	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T90	7		T26	14		T145	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T51	11		T53	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	1		T142	1		T225	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	1		T55	1		T43	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	7		T13	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	5		T51	2		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T50	1		T52	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	6		T8	12		T196	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	12		T54	2		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T40	2		T90	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T49	17		T62	8		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T155	1		T230	1		T243	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T49	7		T52	1		T55	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T50	1		T51	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T12	10		T53	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T15	1		T29	18		T147	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	10		T26	3		T28	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	6		T49	9		T42	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T236	10		T180	14		T191	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1198	1			T54	24		T165	5		T103	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T26	12		T240	10		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	11		T53	10		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T178	10		T170	8		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	7		T55	5		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	12		T141	12		T266	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T46	2		T228	13		T283	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	6		T228	16		T215	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	1		T196	7		T250	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	1		T242	1		T272	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T62	2		T220	5		T46	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	20		T62	8		T183	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T155	9		T243	3		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T49	6		T52	11		T55	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T50	11		T53	15		T55	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T53	3		T166	6		T303	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T29	10		T168	10		T159	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T303	3		T305	17		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T180	1		T304	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T26	4		T268	9		T306	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T42	8		T43	2		T193	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	17		T143	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	10		T49	8		T27	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	10		T13	1		T28	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T163	3		T165	8		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	12		T90	7		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T8	10		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T225	15		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	1		T51	11		T43	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T13	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	5		T51	2		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	7		T52	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	3		T8	12		T156	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	12		T50	1		T54	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	3		T5	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	17		T62	8		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T90	13		T53	1		T28	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	439	1			T12	10		T49	7		T52	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1444	1			T5	1		T11	15		T150	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T303	3		T305	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T26	3		T268	8		T306	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T42	3		T43	1		T193	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T166	6		T240	10		T229	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T4	6		T49	9		T252	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	10		T28	18		T235	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T165	5		T155	14		T60	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	12		T240	10		T149	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T53	10		T54	24		T177	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T178	10		T170	8		T171	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	7		T51	11		T43	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T141	12		T266	16		T296	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T55	5		T295	1		T170	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	12		T52	6		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T46	2		T250	2		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T28	1		T272	9		T245	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	1		T62	2		T220	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	20		T62	8		T282	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	15		T28	13		T243	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T49	6		T52	11		T53	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1275	1			T50	11		T55	14		T29	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10