Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22349

1

T1

20

T2

60

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T2

7

T3

1

T4

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19494

1

T1

20

T2

66

T3

1

auto[1]

6183

1

T2

1

T4

35

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	580	1			T2	1		T9	12		T41	3
values[0]	20	1			T60	20		-	-		-	-
values[1]	739	1			T12	10		T51	2		T52	12
values[2]	2769	1			T11	15		T150	31		T86	2
values[3]	707	1			T4	16		T5	1		T8	1
values[4]	758	1			T2	3		T50	12		T165	13
values[5]	741	1			T5	1		T9	17		T49	37
values[6]	661	1			T7	20		T8	10		T12	12
values[7]	637	1			T13	1		T49	30		T51	22
values[8]	550	1			T3	1		T4	19		T5	1
values[9]	996	1			T2	4		T50	1		T54	22
minimum	16519	1			T1	20		T2	59		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T12	10		T52	12		T53	11
values[1]	2698	1			T11	15		T150	31		T86	2
values[2]	780	1			T4	16		T5	1		T8	1
values[3]	744	1			T2	3		T5	1		T40	1
values[4]	653	1			T9	17		T49	37		T50	8
values[5]	714	1			T7	20		T8	10		T12	12
values[6]	649	1			T8	12		T49	30		T51	22
values[7]	459	1			T3	1		T4	19		T5	1
values[8]	1005	1			T2	4		T9	12		T50	1
values[9]	86	1			T146	1		T171	16		T259	26
minimum	17051	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T12	1		T53	11		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	12		T54	14		T62	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T11	2		T150	3		T86	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T90	1		T53	16		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	7		T8	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T50	12		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T55	6		T256	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	3		T5	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	21		T50	8		T42	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	1		T163	1		T28	33
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T90	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	11		T8	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T49	10		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T49	7		T51	12		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T52	7		T218	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T4	13		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T50	1		T15	1		T176	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T2	3		T9	1		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T146	1		T171	16		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T259	10		T255	1		T260	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16812	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T51	1		T272	12		T181	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	9		T183	18		T268	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T54	11		T62	7		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T11	13		T150	28		T30	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T90	6		T54	1		T27	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	9		T12	4		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	3		T29	10		T224	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T256	12		T257	4		T238	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T165	7		T228	11		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T49	16		T42	3		T178	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	16		T163	2		T28	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	11		T90	12		T145	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	9		T8	9		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	11		T49	7		T26	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	6		T51	10		T46	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T147	4		T156	6		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T4	6		T147	10		T46	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T235	13		T228	7		T141	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	1		T9	11		T54	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T258	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T259	16		T260	11		T261	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T40	2		T62	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T51	1		T272	9		T181	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	439	1			T2	1		T41	3		T56	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T9	1		T55	15		T29	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T60	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T62	3		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	1		T52	12		T62	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T11	2		T150	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	16		T54	15		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	7		T8	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T90	1		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T144	1		T256	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	3		T50	12		T165	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T49	21		T50	8		T55	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T9	1		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T142	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	11		T8	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	10		T90	1		T26	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T49	7		T51	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	1		T52	7		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T4	13		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T50	1		T15	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	3		T54	12		T26	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16381	1			T1	20		T2	59		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T228	7		T283	1		T292	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T9	11		T29	17		T308	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T60	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	9		T62	13		T183	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	1		T62	7		T145	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T11	13		T150	28		T27	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T54	12		T27	9		T230	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	9		T12	4		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T90	6		T15	3		T29	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T256	12		T45	2		T257	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T165	7		T178	5		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	16		T42	3		T178	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	16		T163	2		T28	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	11		T145	17		T183	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	9		T8	9		T28	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	7		T90	12		T26	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T49	6		T51	10		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	11		T156	6		T183	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T4	6		T16	1		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T147	4		T235	13		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T54	10		T26	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	10		T53	1		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T52	1		T54	12		T62	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T11	15		T150	31		T86	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T90	7		T53	1		T54	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	10		T8	1		T12	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T50	1		T15	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T55	1		T256	13		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	3		T5	1		T40	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	17		T50	1		T42	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	17		T163	3		T28	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	12		T90	13		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	10		T8	10		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	12		T49	8		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T49	7		T51	11		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	1		T218	1		T147	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T3	1		T4	7		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T50	1		T15	1		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T2	3		T9	12		T54	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T146	1		T171	1		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T259	17		T255	1		T260	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16974	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T51	2		T272	10		T181	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T53	10		T220	5		T183	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T52	11		T54	13		T62	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T103	11		T43	1		T108	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T53	15		T166	6		T239	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	6		T218	5		T45	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	11		T15	3		T29	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T55	5		T257	7		T293	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T165	5		T240	12		T228	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	20		T50	7		T42	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	31		T43	4		T153	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T221	12		T183	18		T166	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	10		T55	2		T196	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T49	9		T26	3		T183	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T49	6		T51	11		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T52	6		T240	10		T149	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	12		T53	3		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T176	6		T235	6		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T54	11		T55	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T171	15		T258	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T259	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T62	2		T237	1		T309	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T272	11		T222	9		T310	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T2	1		T41	3		T56	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T9	12		T55	1		T29	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T60	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	10		T62	14		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	2		T52	1		T62	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T11	15		T150	31		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T53	1		T54	14		T27	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	10		T8	1		T12	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T90	7		T15	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T144	1		T256	13		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	3		T50	1		T165	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	17		T50	1		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T9	17		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	12		T142	1		T145	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	10		T8	10		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T49	8		T90	13		T26	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	1		T49	7		T51	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	12		T52	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	1		T4	7		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T50	1		T15	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T2	3		T54	11		T26	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16519	1			T1	20		T2	59		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T228	13		T311	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T55	14		T29	10		T294	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T60	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T62	2		T183	22		T241	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T52	11		T62	8		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T53	10		T103	11		T43	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T53	15		T54	13		T230	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	6		T218	5		T241	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	3		T29	10		T155	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T45	2		T257	7		T180	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T50	11		T165	5		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	20		T50	7		T55	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	18		T43	4		T153	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T183	18		T166	6		T242	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	10		T55	2		T28	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	9		T26	3		T221	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	6		T51	11		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T52	6		T183	15		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	12		T53	3		T28	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T176	6		T235	6		T240	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T54	11		T26	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10