Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25677

1

T1

20

T2

67

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22406

1

T1

20

T2

63

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3271

1

T2

4

T5

1

T7

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19910

1

T1

20

T2

63

T3

1

auto[1]

5767

1

T2

4

T4

19

T7

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21782

1

T1

20

T2

66

T3

1

auto[1]

3895

1

T2

1

T4

15

T7

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	199	1			T2	3		T3	1		T5	1
values[0]	19	1			T312	1		T92	7		T313	11
values[1]	689	1			T49	37		T51	2		T52	12
values[2]	630	1			T5	1		T51	2		T52	7
values[3]	615	1			T90	13		T53	4		T54	2
values[4]	754	1			T49	17		T26	26		T142	1
values[5]	600	1			T8	1		T12	17		T50	1
values[6]	778	1			T4	35		T9	12		T13	1
values[7]	642	1			T8	10		T51	22		T40	2
values[8]	2843	1			T2	4		T5	1		T11	15
values[9]	980	1			T8	12		T9	17		T12	10
minimum	16928	1			T1	20		T2	60		T6	11

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	688	1			T5	1		T51	2		T52	7
values[1]	591	1			T51	2		T40	1		T90	13
values[2]	668	1			T49	17		T29	21		T218	13
values[3]	604	1			T26	26		T29	1		T43	3
values[4]	686	1			T4	16		T8	1		T12	17
values[5]	796	1			T4	19		T9	12		T13	1
values[6]	2828	1			T8	10		T11	15		T150	31
values[7]	715	1			T2	4		T5	1		T8	12
values[8]	848	1			T2	3		T5	1		T9	17
values[9]	108	1			T3	1		T7	20		T148	1
minimum	17145	1			T1	20		T2	60		T6	11

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

3948

1

T2

1

T4

18

T7

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	1		T51	1		T52	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T217	1		T143	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T62	9		T15	1		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	1		T40	1		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	10		T29	11		T218	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T218	1		T243	4		T266	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	13		T145	1		T155	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	1		T43	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	7		T8	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	1		T90	1		T55	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	13		T13	1		T49	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	1		T53	11		T54	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T8	1		T11	2		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T51	12		T40	2		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T8	1		T55	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	3		T163	1		T54	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	3		T9	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	1		T13	1		T53	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T3	1		T148	1		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T7	11		T254	1		T184	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16827	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T49	21		T52	12		T155	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	1		T27	9		T28	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T230	21		T229	2		T272	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T62	7		T26	3		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T51	1		T90	12		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T49	7		T29	10		T218	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T243	3		T268	8		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T26	13		T145	17		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	1		T273	11		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	9		T12	4		T62	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	11		T90	6		T27	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	6		T49	6		T28	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	11		T54	10		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T8	9		T11	13		T150	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T51	10		T145	11		T257	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	11		T227	11		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	1		T163	2		T54	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	16		T12	9		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	3		T179	8		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T274	11		T262	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T7	9		T254	2		T184	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	1		T40	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T49	16		T46	3		T290	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T2	3		T3	1		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T5	1		T7	11		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T312	1		T92	4		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T51	1		T27	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	21		T52	12		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T52	7		T62	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T51	1		T40	1		T43	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T26	4		T29	11		T218	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T90	1		T53	4		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T49	10		T26	13		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	1		T219	1		T243	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	1		T12	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T90	1		T55	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	20		T13	1		T49	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	1		T53	11		T54	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	1		T28	14		T29	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T51	12		T40	2		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T5	1		T11	2		T150	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	3		T163	1		T54	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	1		T9	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T53	16		T146	2		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16790	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T169	25		T314	10		T315	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T7	9		T158	8		T254	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T92	3		T313	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T51	1		T27	9		T147	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T49	16		T230	21		T46	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T62	7		T28	13		T145	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T51	1		T43	4		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T26	3		T29	10		T218	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T90	12		T54	1		T268	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	7		T26	13		T145	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T243	3		T273	11		T179	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T12	4		T183	18		T243	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	11		T90	6		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	15		T49	6		T62	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	11		T54	10		T177	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	9		T28	11		T29	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T51	10		T145	11		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T11	13		T150	28		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T163	2		T54	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	11		T9	16		T12	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T141	3		T179	8		T236	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T40	2		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T51	2		T52	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T217	1		T143	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T62	8		T15	1		T26	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	2		T40	1		T90	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	8		T29	11		T218	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T218	1		T243	4		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	14		T145	18		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	1		T43	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	10		T8	1		T12	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	12		T90	7		T55	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	7		T13	1		T49	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	12		T53	1		T54	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T8	10		T11	15		T150	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	11		T40	2		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T8	12		T55	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	3		T163	3		T54	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T2	3		T9	17		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T13	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T3	1		T148	1		T274	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T7	10		T254	3		T184	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16958	1			T1	20		T2	60		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T49	17		T52	1		T155	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T52	6		T28	18		T176	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T230	14		T272	11		T316	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T62	8		T26	3		T180	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T53	3		T43	4		T183	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T49	9		T29	10		T218	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T243	3		T266	8		T239	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	12		T155	9		T228	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T43	1		T223	8		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	6		T55	5		T62	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	2		T221	12		T235	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	12		T49	6		T50	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T53	10		T54	11		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T50	11		T165	5		T29	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	11		T153	11		T166	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T55	14		T28	1		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	1		T54	13		T42	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T196	7		T266	6		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T53	15		T166	6		T240	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T262	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T7	10		T184	8		T270	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T282	11		T302	9		T317	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T49	20		T52	11		T155	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T2	3		T3	1		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T5	1		T7	10		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T312	1		T92	5		T313	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T51	2		T27	10		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T49	17		T52	1		T217	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T52	1		T62	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T51	2		T40	1		T43	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	4		T29	11		T218	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T90	13		T53	1		T54	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	8		T26	14		T145	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T142	1		T219	1		T243	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	1		T12	5		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	12		T90	7		T55	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	17		T13	1		T49	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	12		T53	1		T54	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	10		T28	12		T29	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T51	11		T40	2		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T5	1		T11	15		T150	31
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	3		T163	3		T54	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T8	12		T9	17		T12	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T53	1		T146	2		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T1	20		T2	60		T6	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T315	11		T318	5		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T7	10		T319	6		T303	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T92	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T176	6		T45	2		T46	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	20		T52	11		T155	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T52	6		T62	8		T28	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T43	4		T183	18		T193	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T26	3		T29	10		T218	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	3		T239	20		T268	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	9		T26	12		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T243	3		T266	8		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T55	5		T183	15		T243	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T55	2		T15	3		T43	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	18		T49	6		T50	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T53	10		T54	11		T177	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	13		T29	10		T183	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T51	11		T153	11		T166	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T50	11		T55	14		T165	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T2	1		T54	13		T42	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T196	7		T227	9		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T53	15		T166	6		T240	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21729

1

T1

20

T2

66

T3

1

auto[1]

auto[0]

3948

1

T2

1

T4

18

T7

10