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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.44


Total test records in report: 919
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T798 /workspace/coverage/default/29.adc_ctrl_poweron_counter.1837491381 Jul 03 07:04:40 PM PDT 24 Jul 03 07:04:44 PM PDT 24 3383685230 ps
T291 /workspace/coverage/default/48.adc_ctrl_filters_both.3589874316 Jul 03 07:06:36 PM PDT 24 Jul 03 07:24:41 PM PDT 24 513438693099 ps
T799 /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1889436470 Jul 03 06:57:16 PM PDT 24 Jul 03 07:00:32 PM PDT 24 322913596571 ps
T800 /workspace/coverage/default/21.adc_ctrl_stress_all.1014708821 Jul 03 06:58:45 PM PDT 24 Jul 03 06:59:24 PM PDT 24 232878412909 ps
T61 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2779215596 Jul 03 05:06:57 PM PDT 24 Jul 03 05:07:06 PM PDT 24 2860299556 ps
T34 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2990305819 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:26 PM PDT 24 2275060833 ps
T801 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4196742000 Jul 03 05:07:22 PM PDT 24 Jul 03 05:07:23 PM PDT 24 536259818 ps
T802 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2420673801 Jul 03 05:07:30 PM PDT 24 Jul 03 05:07:32 PM PDT 24 293840548 ps
T20 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.592465843 Jul 03 05:07:26 PM PDT 24 Jul 03 05:07:34 PM PDT 24 2483719276 ps
T21 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.206434422 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:19 PM PDT 24 379658268 ps
T803 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2370536462 Jul 03 05:06:57 PM PDT 24 Jul 03 05:06:58 PM PDT 24 368422426 ps
T134 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1602196436 Jul 03 05:07:16 PM PDT 24 Jul 03 05:07:18 PM PDT 24 348134456 ps
T139 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1392138658 Jul 03 05:06:37 PM PDT 24 Jul 03 05:06:40 PM PDT 24 614239540 ps
T804 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.622627318 Jul 03 05:06:22 PM PDT 24 Jul 03 05:06:24 PM PDT 24 484330378 ps
T22 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3570186641 Jul 03 05:07:21 PM PDT 24 Jul 03 05:07:24 PM PDT 24 625179517 ps
T63 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2039090624 Jul 03 05:07:04 PM PDT 24 Jul 03 05:07:26 PM PDT 24 8055605588 ps
T23 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.588114482 Jul 03 05:07:27 PM PDT 24 Jul 03 05:07:29 PM PDT 24 502181321 ps
T24 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.564067447 Jul 03 05:07:07 PM PDT 24 Jul 03 05:07:21 PM PDT 24 4239050991 ps
T70 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3456232448 Jul 03 05:06:59 PM PDT 24 Jul 03 05:07:01 PM PDT 24 579645820 ps
T135 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.824411971 Jul 03 05:07:14 PM PDT 24 Jul 03 05:07:36 PM PDT 24 4454010876 ps
T64 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3823255121 Jul 03 05:06:53 PM PDT 24 Jul 03 05:06:59 PM PDT 24 9344771086 ps
T120 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.334464651 Jul 03 05:07:21 PM PDT 24 Jul 03 05:07:23 PM PDT 24 326961133 ps
T71 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1338639665 Jul 03 05:06:34 PM PDT 24 Jul 03 05:06:37 PM PDT 24 387732563 ps
T136 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2514483878 Jul 03 05:07:02 PM PDT 24 Jul 03 05:07:07 PM PDT 24 1911690451 ps
T93 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.26798195 Jul 03 05:07:02 PM PDT 24 Jul 03 05:07:04 PM PDT 24 635306206 ps
T137 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2504512518 Jul 03 05:07:22 PM PDT 24 Jul 03 05:07:38 PM PDT 24 5074283326 ps
T65 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1481285795 Jul 03 05:07:08 PM PDT 24 Jul 03 05:07:12 PM PDT 24 4219517912 ps
T77 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.424023540 Jul 03 05:07:10 PM PDT 24 Jul 03 05:07:12 PM PDT 24 391596895 ps
T805 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4055363854 Jul 03 05:07:23 PM PDT 24 Jul 03 05:07:24 PM PDT 24 340230501 ps
T78 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3859207852 Jul 03 05:06:56 PM PDT 24 Jul 03 05:06:58 PM PDT 24 600806710 ps
T138 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1139776451 Jul 03 05:06:38 PM PDT 24 Jul 03 05:06:39 PM PDT 24 511472753 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1313267344 Jul 03 05:06:33 PM PDT 24 Jul 03 05:06:36 PM PDT 24 836921612 ps
T66 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2492826828 Jul 03 05:07:13 PM PDT 24 Jul 03 05:07:25 PM PDT 24 4005238993 ps
T340 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3523430153 Jul 03 05:07:11 PM PDT 24 Jul 03 05:07:22 PM PDT 24 4192967943 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2054230100 Jul 03 05:06:41 PM PDT 24 Jul 03 05:06:43 PM PDT 24 445912866 ps
T72 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4049035720 Jul 03 05:07:23 PM PDT 24 Jul 03 05:07:26 PM PDT 24 563665853 ps
T806 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3442573592 Jul 03 05:07:32 PM PDT 24 Jul 03 05:07:34 PM PDT 24 504985612 ps
T807 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.859270703 Jul 03 05:07:12 PM PDT 24 Jul 03 05:07:15 PM PDT 24 2594526283 ps
T808 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1311049528 Jul 03 05:07:35 PM PDT 24 Jul 03 05:07:37 PM PDT 24 338447035 ps
T809 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.82408490 Jul 03 05:07:10 PM PDT 24 Jul 03 05:07:12 PM PDT 24 304203228 ps
T810 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1955606553 Jul 03 05:07:25 PM PDT 24 Jul 03 05:07:28 PM PDT 24 501476923 ps
T811 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.129895744 Jul 03 05:07:08 PM PDT 24 Jul 03 05:07:09 PM PDT 24 410223704 ps
T812 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3736656316 Jul 03 05:07:08 PM PDT 24 Jul 03 05:07:10 PM PDT 24 511043867 ps
T813 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.749439987 Jul 03 05:07:39 PM PDT 24 Jul 03 05:07:40 PM PDT 24 541462062 ps
T123 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.634737254 Jul 03 05:07:08 PM PDT 24 Jul 03 05:07:10 PM PDT 24 360233752 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1726821626 Jul 03 05:06:48 PM PDT 24 Jul 03 05:06:50 PM PDT 24 608425580 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.544773591 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:43 PM PDT 24 28142937904 ps
T79 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3990219984 Jul 03 05:07:25 PM PDT 24 Jul 03 05:07:45 PM PDT 24 8065181674 ps
T816 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1196044969 Jul 03 05:07:16 PM PDT 24 Jul 03 05:07:17 PM PDT 24 491991692 ps
T817 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4011132756 Jul 03 05:07:02 PM PDT 24 Jul 03 05:07:03 PM PDT 24 559923025 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3822370589 Jul 03 05:06:35 PM PDT 24 Jul 03 05:06:47 PM PDT 24 4269327596 ps
T819 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3580330053 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:39 PM PDT 24 431860554 ps
T820 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2734457375 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:39 PM PDT 24 498401628 ps
T80 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4004513711 Jul 03 05:07:08 PM PDT 24 Jul 03 05:07:10 PM PDT 24 349627117 ps
T821 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3373962806 Jul 03 05:07:20 PM PDT 24 Jul 03 05:07:21 PM PDT 24 469539364 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.674598174 Jul 03 05:07:21 PM PDT 24 Jul 03 05:07:34 PM PDT 24 4281144822 ps
T823 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2963156035 Jul 03 05:07:34 PM PDT 24 Jul 03 05:07:36 PM PDT 24 426215353 ps
T81 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3742821136 Jul 03 05:06:38 PM PDT 24 Jul 03 05:06:45 PM PDT 24 7916394727 ps
T824 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1749129866 Jul 03 05:07:22 PM PDT 24 Jul 03 05:07:23 PM PDT 24 370497046 ps
T825 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3325582162 Jul 03 05:07:39 PM PDT 24 Jul 03 05:07:41 PM PDT 24 371164299 ps
T826 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2803013414 Jul 03 05:06:42 PM PDT 24 Jul 03 05:06:49 PM PDT 24 4564228937 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2523742436 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:19 PM PDT 24 343319765 ps
T828 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2854466314 Jul 03 05:07:38 PM PDT 24 Jul 03 05:07:39 PM PDT 24 432201268 ps
T829 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2086793633 Jul 03 05:07:01 PM PDT 24 Jul 03 05:07:02 PM PDT 24 454273540 ps
T830 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1849459299 Jul 03 05:06:37 PM PDT 24 Jul 03 05:06:39 PM PDT 24 2374625516 ps
T73 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.800812588 Jul 03 05:07:13 PM PDT 24 Jul 03 05:07:16 PM PDT 24 423530517 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.475604681 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:21 PM PDT 24 559671451 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.805885486 Jul 03 05:07:11 PM PDT 24 Jul 03 05:07:22 PM PDT 24 4611187796 ps
T74 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.200713857 Jul 03 05:07:07 PM PDT 24 Jul 03 05:07:10 PM PDT 24 798558020 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1768645031 Jul 03 05:07:16 PM PDT 24 Jul 03 05:07:18 PM PDT 24 477068862 ps
T124 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.705173742 Jul 03 05:07:00 PM PDT 24 Jul 03 05:07:02 PM PDT 24 455817209 ps
T834 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1568659648 Jul 03 05:06:44 PM PDT 24 Jul 03 05:06:45 PM PDT 24 1237724698 ps
T835 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.422751924 Jul 03 05:06:57 PM PDT 24 Jul 03 05:07:00 PM PDT 24 670117376 ps
T836 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.559439801 Jul 03 05:06:22 PM PDT 24 Jul 03 05:06:24 PM PDT 24 571198861 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.717984734 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:38 PM PDT 24 378524387 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1586096365 Jul 03 05:06:35 PM PDT 24 Jul 03 05:06:39 PM PDT 24 968713315 ps
T838 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2566482215 Jul 03 05:07:32 PM PDT 24 Jul 03 05:07:34 PM PDT 24 495075710 ps
T839 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1856390906 Jul 03 05:07:20 PM PDT 24 Jul 03 05:07:22 PM PDT 24 731811721 ps
T840 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.886050590 Jul 03 05:07:04 PM PDT 24 Jul 03 05:07:07 PM PDT 24 551150945 ps
T126 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1579441890 Jul 03 05:06:41 PM PDT 24 Jul 03 05:09:01 PM PDT 24 44514544091 ps
T841 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1520460759 Jul 03 05:07:29 PM PDT 24 Jul 03 05:07:30 PM PDT 24 503618366 ps
T842 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3342854428 Jul 03 05:07:22 PM PDT 24 Jul 03 05:07:26 PM PDT 24 623187660 ps
T843 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3852201316 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:41 PM PDT 24 2592591378 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3009441378 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:39 PM PDT 24 2151854509 ps
T845 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2557539755 Jul 03 05:07:33 PM PDT 24 Jul 03 05:07:35 PM PDT 24 419737099 ps
T846 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1459076423 Jul 03 05:07:11 PM PDT 24 Jul 03 05:07:12 PM PDT 24 526417029 ps
T847 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.62594027 Jul 03 05:07:12 PM PDT 24 Jul 03 05:07:14 PM PDT 24 531382499 ps
T848 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2664045676 Jul 03 05:07:13 PM PDT 24 Jul 03 05:07:17 PM PDT 24 2127772974 ps
T82 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3678708066 Jul 03 05:07:02 PM PDT 24 Jul 03 05:07:22 PM PDT 24 7947420990 ps
T849 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2896792327 Jul 03 05:07:35 PM PDT 24 Jul 03 05:07:37 PM PDT 24 421312877 ps
T850 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1817848143 Jul 03 05:07:28 PM PDT 24 Jul 03 05:07:30 PM PDT 24 385293793 ps
T851 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2239510932 Jul 03 05:07:36 PM PDT 24 Jul 03 05:07:37 PM PDT 24 508368790 ps
T127 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2813567864 Jul 03 05:06:34 PM PDT 24 Jul 03 05:07:57 PM PDT 24 40814741869 ps
T852 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2677166318 Jul 03 05:07:33 PM PDT 24 Jul 03 05:07:34 PM PDT 24 440912236 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1361643632 Jul 03 05:06:37 PM PDT 24 Jul 03 05:06:40 PM PDT 24 415007578 ps
T853 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.392402127 Jul 03 05:07:20 PM PDT 24 Jul 03 05:07:22 PM PDT 24 493893300 ps
T854 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3900506148 Jul 03 05:07:32 PM PDT 24 Jul 03 05:07:34 PM PDT 24 366411512 ps
T129 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3290505644 Jul 03 05:06:46 PM PDT 24 Jul 03 05:06:50 PM PDT 24 955115559 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1284750072 Jul 03 05:06:45 PM PDT 24 Jul 03 05:06:47 PM PDT 24 561469127 ps
T856 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.855975169 Jul 03 05:06:51 PM PDT 24 Jul 03 05:06:53 PM PDT 24 597489961 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1875165374 Jul 03 05:07:20 PM PDT 24 Jul 03 05:07:27 PM PDT 24 3901299990 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1292933413 Jul 03 05:07:02 PM PDT 24 Jul 03 05:07:03 PM PDT 24 500736431 ps
T859 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4057192910 Jul 03 05:06:58 PM PDT 24 Jul 03 05:07:00 PM PDT 24 804150113 ps
T860 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1987082470 Jul 03 05:07:33 PM PDT 24 Jul 03 05:07:35 PM PDT 24 485226853 ps
T861 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2256496343 Jul 03 05:07:38 PM PDT 24 Jul 03 05:07:40 PM PDT 24 533909231 ps
T862 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1749009594 Jul 03 05:07:26 PM PDT 24 Jul 03 05:07:28 PM PDT 24 505671277 ps
T863 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1896647505 Jul 03 05:06:49 PM PDT 24 Jul 03 05:06:50 PM PDT 24 408701862 ps
T864 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4057692297 Jul 03 05:07:32 PM PDT 24 Jul 03 05:07:34 PM PDT 24 331373739 ps
T865 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1131981338 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:39 PM PDT 24 396868102 ps
T866 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2167200539 Jul 03 05:07:28 PM PDT 24 Jul 03 05:07:29 PM PDT 24 471379037 ps
T130 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.519003144 Jul 03 05:06:46 PM PDT 24 Jul 03 05:06:51 PM PDT 24 2384842964 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1739320951 Jul 03 05:07:12 PM PDT 24 Jul 03 05:07:15 PM PDT 24 571352541 ps
T341 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2924228480 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:40 PM PDT 24 4313110224 ps
T868 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2002251623 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:29 PM PDT 24 4336671413 ps
T869 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3888142735 Jul 03 05:07:00 PM PDT 24 Jul 03 05:07:02 PM PDT 24 407248573 ps
T870 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3297381433 Jul 03 05:06:37 PM PDT 24 Jul 03 05:06:39 PM PDT 24 290953600 ps
T871 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3936212404 Jul 03 05:06:40 PM PDT 24 Jul 03 05:06:43 PM PDT 24 1447621661 ps
T872 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1759541389 Jul 03 05:07:26 PM PDT 24 Jul 03 05:07:28 PM PDT 24 339175058 ps
T873 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.644831555 Jul 03 05:07:18 PM PDT 24 Jul 03 05:07:22 PM PDT 24 538107383 ps
T874 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3554083140 Jul 03 05:07:02 PM PDT 24 Jul 03 05:07:05 PM PDT 24 526568055 ps
T875 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2897244117 Jul 03 05:06:59 PM PDT 24 Jul 03 05:07:05 PM PDT 24 2176014156 ps
T876 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4252694897 Jul 03 05:07:22 PM PDT 24 Jul 03 05:07:44 PM PDT 24 5865385540 ps
T131 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.735683148 Jul 03 05:06:18 PM PDT 24 Jul 03 05:06:20 PM PDT 24 1420259373 ps
T877 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2693442151 Jul 03 05:07:16 PM PDT 24 Jul 03 05:07:17 PM PDT 24 538896879 ps
T878 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3558240449 Jul 03 05:06:57 PM PDT 24 Jul 03 05:07:00 PM PDT 24 1003747115 ps
T879 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3056900404 Jul 03 05:07:10 PM PDT 24 Jul 03 05:07:12 PM PDT 24 537559715 ps
T880 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1154396154 Jul 03 05:07:21 PM PDT 24 Jul 03 05:07:33 PM PDT 24 4656351817 ps
T881 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.30292419 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:22 PM PDT 24 4122053652 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.542102900 Jul 03 05:06:21 PM PDT 24 Jul 03 05:06:26 PM PDT 24 4509402076 ps
T883 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2466448308 Jul 03 05:07:20 PM PDT 24 Jul 03 05:07:27 PM PDT 24 8285272349 ps
T884 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1910528696 Jul 03 05:07:28 PM PDT 24 Jul 03 05:07:30 PM PDT 24 345326998 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3972240558 Jul 03 05:06:37 PM PDT 24 Jul 03 05:06:41 PM PDT 24 541126586 ps
T886 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4198610850 Jul 03 05:07:24 PM PDT 24 Jul 03 05:07:25 PM PDT 24 312813041 ps
T132 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2396818578 Jul 03 05:06:57 PM PDT 24 Jul 03 05:06:59 PM PDT 24 561647609 ps
T887 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.701104834 Jul 03 05:06:59 PM PDT 24 Jul 03 05:07:04 PM PDT 24 9575227962 ps
T133 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1085058807 Jul 03 05:07:08 PM PDT 24 Jul 03 05:07:10 PM PDT 24 426382990 ps
T888 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2442083852 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:19 PM PDT 24 459877000 ps
T889 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.85161298 Jul 03 05:07:38 PM PDT 24 Jul 03 05:07:39 PM PDT 24 361208901 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.370963582 Jul 03 05:06:47 PM PDT 24 Jul 03 05:06:52 PM PDT 24 2094641307 ps
T891 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.233621191 Jul 03 05:06:35 PM PDT 24 Jul 03 05:06:37 PM PDT 24 472297223 ps
T892 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1361950093 Jul 03 05:06:53 PM PDT 24 Jul 03 05:06:54 PM PDT 24 436015682 ps
T893 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2904919747 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:39 PM PDT 24 656021023 ps
T894 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4129787269 Jul 03 05:06:49 PM PDT 24 Jul 03 05:06:50 PM PDT 24 568003210 ps
T895 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.547998239 Jul 03 05:07:20 PM PDT 24 Jul 03 05:07:23 PM PDT 24 438800555 ps
T896 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2445107811 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:39 PM PDT 24 500207200 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1709689047 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:37 PM PDT 24 641152635 ps
T898 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2082035265 Jul 03 05:06:44 PM PDT 24 Jul 03 05:06:46 PM PDT 24 426108330 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.534624569 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:38 PM PDT 24 450701242 ps
T900 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1259644578 Jul 03 05:06:43 PM PDT 24 Jul 03 05:07:02 PM PDT 24 8390534172 ps
T901 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.581761845 Jul 03 05:07:28 PM PDT 24 Jul 03 05:07:30 PM PDT 24 450556127 ps
T902 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4172700680 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:37 PM PDT 24 373866984 ps
T903 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2869526529 Jul 03 05:07:01 PM PDT 24 Jul 03 05:07:03 PM PDT 24 541745835 ps
T904 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2832717319 Jul 03 05:06:36 PM PDT 24 Jul 03 05:06:38 PM PDT 24 528409032 ps
T905 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1855882643 Jul 03 05:07:11 PM PDT 24 Jul 03 05:07:13 PM PDT 24 498674178 ps
T906 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2289885535 Jul 03 05:07:19 PM PDT 24 Jul 03 05:07:21 PM PDT 24 2730451202 ps
T907 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2412745717 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:38 PM PDT 24 476588944 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3088847014 Jul 03 05:06:57 PM PDT 24 Jul 03 05:07:00 PM PDT 24 2142573436 ps
T909 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2578068224 Jul 03 05:06:18 PM PDT 24 Jul 03 05:06:20 PM PDT 24 298664048 ps
T910 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3909638345 Jul 03 05:07:11 PM PDT 24 Jul 03 05:07:14 PM PDT 24 356361296 ps
T83 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.562377884 Jul 03 05:06:58 PM PDT 24 Jul 03 05:07:02 PM PDT 24 4682852845 ps
T911 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.336514976 Jul 03 05:07:22 PM PDT 24 Jul 03 05:07:23 PM PDT 24 605460954 ps
T912 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.602271268 Jul 03 05:07:39 PM PDT 24 Jul 03 05:07:41 PM PDT 24 414046220 ps
T913 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4667980 Jul 03 05:06:35 PM PDT 24 Jul 03 05:06:37 PM PDT 24 1468944327 ps
T914 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.833076339 Jul 03 05:07:17 PM PDT 24 Jul 03 05:07:38 PM PDT 24 8409422322 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4164163873 Jul 03 05:06:36 PM PDT 24 Jul 03 05:08:11 PM PDT 24 41307529224 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2743012874 Jul 03 05:06:41 PM PDT 24 Jul 03 05:06:42 PM PDT 24 859864100 ps
T917 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.29828371 Jul 03 05:07:27 PM PDT 24 Jul 03 05:07:29 PM PDT 24 471018506 ps
T918 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4172555185 Jul 03 05:07:14 PM PDT 24 Jul 03 05:07:16 PM PDT 24 520407251 ps
T919 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.716977131 Jul 03 05:07:25 PM PDT 24 Jul 03 05:07:28 PM PDT 24 521363567 ps

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.492725781
Short name T2
Test name
Test status
Simulation time 50863767003 ps
CPU time 123.47 seconds
Started Jul 03 07:06:54 PM PDT 24
Finished Jul 03 07:08:59 PM PDT 24
Peak memory 218204 kb
Host smart-eb69d9b3-005a-4f05-b6cc-f8cfed47a3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492725781 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.492725781
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1457724603
Short name T4
Test name
Test status
Simulation time 365395741296 ps
CPU time 404.44 seconds
Started Jul 03 06:52:08 PM PDT 24
Finished Jul 03 06:58:53 PM PDT 24
Peak memory 201880 kb
Host smart-64ffd918-1b17-4c95-80cf-e19ef751dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457724603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1457724603
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3089223807
Short name T29
Test name
Test status
Simulation time 1059433811630 ps
CPU time 2497.75 seconds
Started Jul 03 07:05:24 PM PDT 24
Finished Jul 03 07:47:03 PM PDT 24
Peak memory 202164 kb
Host smart-e074ef99-37f8-4362-aa1c-7baa44c8f963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089223807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3089223807
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2296138450
Short name T16
Test name
Test status
Simulation time 174247469701 ps
CPU time 162.48 seconds
Started Jul 03 07:06:02 PM PDT 24
Finished Jul 03 07:08:45 PM PDT 24
Peak memory 218192 kb
Host smart-1024c991-2145-42d3-baba-8cad846b6b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296138450 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2296138450
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4065127112
Short name T49
Test name
Test status
Simulation time 594031562146 ps
CPU time 1222.33 seconds
Started Jul 03 06:58:52 PM PDT 24
Finished Jul 03 07:19:16 PM PDT 24
Peak memory 201972 kb
Host smart-3a51e2c6-3f61-4bbe-b469-0882dc5a2d60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065127112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4065127112
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2131303113
Short name T54
Test name
Test status
Simulation time 531196246448 ps
CPU time 827.11 seconds
Started Jul 03 06:54:45 PM PDT 24
Finished Jul 03 07:08:33 PM PDT 24
Peak memory 201908 kb
Host smart-1070fb8c-b018-4fa3-81c5-648de5157754
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131303113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2131303113
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1934868009
Short name T55
Test name
Test status
Simulation time 641497835650 ps
CPU time 127.48 seconds
Started Jul 03 07:05:31 PM PDT 24
Finished Jul 03 07:07:40 PM PDT 24
Peak memory 201940 kb
Host smart-8d17fa55-f0c0-419d-946d-459b76eaf30b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934868009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1934868009
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3465090486
Short name T26
Test name
Test status
Simulation time 337176604121 ps
CPU time 753.13 seconds
Started Jul 03 06:55:29 PM PDT 24
Finished Jul 03 07:08:03 PM PDT 24
Peak memory 201828 kb
Host smart-e8192404-5264-4926-8eaf-237313521375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465090486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3465090486
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2818022381
Short name T12
Test name
Test status
Simulation time 495761948711 ps
CPU time 289.4 seconds
Started Jul 03 06:52:25 PM PDT 24
Finished Jul 03 06:57:15 PM PDT 24
Peak memory 201888 kb
Host smart-a120f50f-cfb3-4804-b6e2-4b7e8cf163e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818022381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2818022381
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3993531223
Short name T60
Test name
Test status
Simulation time 234548003029 ps
CPU time 509.65 seconds
Started Jul 03 06:58:07 PM PDT 24
Finished Jul 03 07:06:38 PM PDT 24
Peak memory 217832 kb
Host smart-3e8ffaf9-945a-49f8-a02d-e50eb3eef426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993531223 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3993531223
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1181990278
Short name T51
Test name
Test status
Simulation time 508029399753 ps
CPU time 390.3 seconds
Started Jul 03 07:04:50 PM PDT 24
Finished Jul 03 07:11:22 PM PDT 24
Peak memory 201916 kb
Host smart-7f358c7f-6e76-4d43-9481-f1ecf524789e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181990278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1181990278
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3456232448
Short name T70
Test name
Test status
Simulation time 579645820 ps
CPU time 2.42 seconds
Started Jul 03 05:06:59 PM PDT 24
Finished Jul 03 05:07:01 PM PDT 24
Peak memory 218192 kb
Host smart-bebac097-e1bc-49ef-a233-cac278723280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456232448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3456232448
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2579965988
Short name T67
Test name
Test status
Simulation time 7985570244 ps
CPU time 10.04 seconds
Started Jul 03 06:50:47 PM PDT 24
Finished Jul 03 06:50:58 PM PDT 24
Peak memory 218240 kb
Host smart-8e1bae9a-8c55-4479-abab-577e29fa3a52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579965988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2579965988
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2994257551
Short name T141
Test name
Test status
Simulation time 823403219583 ps
CPU time 1101.49 seconds
Started Jul 03 06:58:43 PM PDT 24
Finished Jul 03 07:17:06 PM PDT 24
Peak memory 217768 kb
Host smart-0a8ad4e8-fc3e-48ec-8558-9e0860974779
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994257551 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2994257551
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2604155330
Short name T28
Test name
Test status
Simulation time 540102094519 ps
CPU time 1276.5 seconds
Started Jul 03 07:05:05 PM PDT 24
Finished Jul 03 07:26:23 PM PDT 24
Peak memory 201892 kb
Host smart-0749b51b-ca35-456b-8efe-6d02603537fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604155330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2604155330
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2629990314
Short name T228
Test name
Test status
Simulation time 356093530079 ps
CPU time 279.11 seconds
Started Jul 03 06:57:08 PM PDT 24
Finished Jul 03 07:01:48 PM PDT 24
Peak memory 201912 kb
Host smart-75d1673a-72da-47a9-ab08-af8a8d625b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629990314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2629990314
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3658727714
Short name T170
Test name
Test status
Simulation time 501141765619 ps
CPU time 1118.15 seconds
Started Jul 03 06:59:25 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 201908 kb
Host smart-d2d1cbd6-1e27-449a-aad0-807bf1f740ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658727714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3658727714
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3697998282
Short name T160
Test name
Test status
Simulation time 359366492781 ps
CPU time 205.41 seconds
Started Jul 03 06:58:16 PM PDT 24
Finished Jul 03 07:01:42 PM PDT 24
Peak memory 201848 kb
Host smart-808b8a98-3c8e-4b61-ba91-a5c75c06cad4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697998282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3697998282
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.206434422
Short name T21
Test name
Test status
Simulation time 379658268 ps
CPU time 1.7 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:19 PM PDT 24
Peak memory 201488 kb
Host smart-4f6a7802-89c9-4b8d-8837-7359ec5232de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206434422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.206434422
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2180156363
Short name T231
Test name
Test status
Simulation time 502154162148 ps
CPU time 585.75 seconds
Started Jul 03 06:58:52 PM PDT 24
Finished Jul 03 07:08:38 PM PDT 24
Peak memory 201960 kb
Host smart-2eaa3794-1a0e-4517-87de-30e3594f5738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180156363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2180156363
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3537466496
Short name T43
Test name
Test status
Simulation time 104621728419 ps
CPU time 120.54 seconds
Started Jul 03 06:51:39 PM PDT 24
Finished Jul 03 06:53:40 PM PDT 24
Peak memory 210628 kb
Host smart-75d0edd3-22c4-4b7f-aabb-3bcc47376a3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537466496 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3537466496
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1243932238
Short name T180
Test name
Test status
Simulation time 554801195184 ps
CPU time 149.96 seconds
Started Jul 03 06:50:39 PM PDT 24
Finished Jul 03 06:53:09 PM PDT 24
Peak memory 201992 kb
Host smart-64d2febc-28c4-4c8c-b1c4-0676f313c2d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243932238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1243932238
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4181179648
Short name T243
Test name
Test status
Simulation time 589240908495 ps
CPU time 281.65 seconds
Started Jul 03 07:05:13 PM PDT 24
Finished Jul 03 07:09:55 PM PDT 24
Peak memory 201992 kb
Host smart-dd6d58e0-0d0c-408f-8e7a-4610958f943a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181179648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4181179648
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3332088900
Short name T184
Test name
Test status
Simulation time 545622953486 ps
CPU time 250.22 seconds
Started Jul 03 06:53:31 PM PDT 24
Finished Jul 03 06:57:41 PM PDT 24
Peak memory 201900 kb
Host smart-63798789-cc13-495b-ad2f-36aac12387b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332088900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3332088900
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.468149964
Short name T147
Test name
Test status
Simulation time 491702975975 ps
CPU time 600.4 seconds
Started Jul 03 06:58:04 PM PDT 24
Finished Jul 03 07:08:05 PM PDT 24
Peak memory 201948 kb
Host smart-47633913-198a-4247-bfd1-1ded876ba780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468149964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.468149964
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.107896146
Short name T166
Test name
Test status
Simulation time 377761630545 ps
CPU time 177.84 seconds
Started Jul 03 07:04:38 PM PDT 24
Finished Jul 03 07:07:37 PM PDT 24
Peak memory 201940 kb
Host smart-69726a79-3b38-4252-b47a-ce1f4375365c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107896146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.107896146
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.541406794
Short name T272
Test name
Test status
Simulation time 330465052293 ps
CPU time 128.86 seconds
Started Jul 03 07:05:37 PM PDT 24
Finished Jul 03 07:07:46 PM PDT 24
Peak memory 201892 kb
Host smart-8df8d48b-24ab-4051-bed6-8aebd033e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541406794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.541406794
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2307385870
Short name T150
Test name
Test status
Simulation time 494072513525 ps
CPU time 1109.44 seconds
Started Jul 03 06:55:30 PM PDT 24
Finished Jul 03 07:14:00 PM PDT 24
Peak memory 201884 kb
Host smart-51ecf1ab-c561-4108-9f2a-cb90e51b5c33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307385870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2307385870
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3742821136
Short name T81
Test name
Test status
Simulation time 7916394727 ps
CPU time 7.01 seconds
Started Jul 03 05:06:38 PM PDT 24
Finished Jul 03 05:06:45 PM PDT 24
Peak memory 201916 kb
Host smart-989abb24-7ce9-4dce-a6c7-8c96ac45a8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742821136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3742821136
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3930370412
Short name T75
Test name
Test status
Simulation time 513051733 ps
CPU time 1.67 seconds
Started Jul 03 06:55:21 PM PDT 24
Finished Jul 03 06:55:23 PM PDT 24
Peak memory 201616 kb
Host smart-0b8d64ea-881f-4b2e-93b9-0f25db3ce59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930370412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3930370412
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.964799112
Short name T223
Test name
Test status
Simulation time 537511451563 ps
CPU time 1109.57 seconds
Started Jul 03 07:05:03 PM PDT 24
Finished Jul 03 07:23:34 PM PDT 24
Peak memory 201852 kb
Host smart-a8daf373-2900-45bc-87d7-965dc5cff521
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964799112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.964799112
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2826009287
Short name T258
Test name
Test status
Simulation time 532191064732 ps
CPU time 453.73 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:12:53 PM PDT 24
Peak memory 201932 kb
Host smart-2561e1f0-931e-4adf-b157-ff23031ccd31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826009287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2826009287
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3194127851
Short name T215
Test name
Test status
Simulation time 520739736745 ps
CPU time 1211.64 seconds
Started Jul 03 06:53:49 PM PDT 24
Finished Jul 03 07:14:01 PM PDT 24
Peak memory 201856 kb
Host smart-e842c499-b5b5-46a7-ac77-c63abe8a5d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194127851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3194127851
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3589874316
Short name T291
Test name
Test status
Simulation time 513438693099 ps
CPU time 1082.74 seconds
Started Jul 03 07:06:36 PM PDT 24
Finished Jul 03 07:24:41 PM PDT 24
Peak memory 201932 kb
Host smart-ca1c3097-cbb5-44d5-b9a5-3a495cfd77eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589874316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3589874316
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.462573457
Short name T48
Test name
Test status
Simulation time 133177922958 ps
CPU time 304.87 seconds
Started Jul 03 06:59:09 PM PDT 24
Finished Jul 03 07:04:15 PM PDT 24
Peak memory 210676 kb
Host smart-46a0e27c-b130-4541-9723-188d1cc12aa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462573457 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.462573457
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3748727579
Short name T302
Test name
Test status
Simulation time 503432833138 ps
CPU time 558.48 seconds
Started Jul 03 07:05:59 PM PDT 24
Finished Jul 03 07:15:18 PM PDT 24
Peak memory 201980 kb
Host smart-c7a87173-d008-4ee5-83f0-1c7f22a26c1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748727579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3748727579
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.200713857
Short name T74
Test name
Test status
Simulation time 798558020 ps
CPU time 2.25 seconds
Started Jul 03 05:07:07 PM PDT 24
Finished Jul 03 05:07:10 PM PDT 24
Peak memory 201804 kb
Host smart-21f4a433-db76-4907-a9e6-266a774cf5c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200713857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.200713857
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.519019780
Short name T222
Test name
Test status
Simulation time 523918111091 ps
CPU time 223.22 seconds
Started Jul 03 06:59:06 PM PDT 24
Finished Jul 03 07:02:49 PM PDT 24
Peak memory 201932 kb
Host smart-b372db96-5bee-4631-9dc7-4b1f80a79afa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519019780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.519019780
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2730063151
Short name T92
Test name
Test status
Simulation time 222311795017 ps
CPU time 32.57 seconds
Started Jul 03 06:58:58 PM PDT 24
Finished Jul 03 06:59:31 PM PDT 24
Peak memory 202124 kb
Host smart-145d0581-75ff-4d0e-89e0-e7c3220dcce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730063151 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2730063151
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.824411971
Short name T135
Test name
Test status
Simulation time 4454010876 ps
CPU time 21.73 seconds
Started Jul 03 05:07:14 PM PDT 24
Finished Jul 03 05:07:36 PM PDT 24
Peak memory 201824 kb
Host smart-e93be53c-e7b9-47b1-86dd-735ad91d8f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824411971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.824411971
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.375648560
Short name T300
Test name
Test status
Simulation time 529522527315 ps
CPU time 1256.27 seconds
Started Jul 03 06:57:01 PM PDT 24
Finished Jul 03 07:17:59 PM PDT 24
Peak memory 202000 kb
Host smart-8dc7fb54-9f29-43d0-9385-e4eca8c293e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375648560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.375648560
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3439425073
Short name T260
Test name
Test status
Simulation time 493254994820 ps
CPU time 1158.06 seconds
Started Jul 03 06:50:37 PM PDT 24
Finished Jul 03 07:09:56 PM PDT 24
Peak memory 201880 kb
Host smart-f186cf23-ce53-4559-acb3-8db773068a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439425073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3439425073
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2551577632
Short name T254
Test name
Test status
Simulation time 490196362331 ps
CPU time 575.43 seconds
Started Jul 03 06:55:25 PM PDT 24
Finished Jul 03 07:05:01 PM PDT 24
Peak memory 201896 kb
Host smart-00abcd5b-1657-42ac-8294-d3abcc93b81e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551577632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2551577632
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3661394932
Short name T262
Test name
Test status
Simulation time 337573369871 ps
CPU time 409.12 seconds
Started Jul 03 06:52:15 PM PDT 24
Finished Jul 03 06:59:05 PM PDT 24
Peak memory 201872 kb
Host smart-3391c62d-d8d4-47a5-a1eb-7509df3c67ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661394932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3661394932
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3966731234
Short name T288
Test name
Test status
Simulation time 483562490888 ps
CPU time 1159.99 seconds
Started Jul 03 06:59:00 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 201936 kb
Host smart-1f767d62-ef7a-4d74-9088-7c637f031ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966731234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3966731234
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1567511064
Short name T56
Test name
Test status
Simulation time 106746765487 ps
CPU time 386.15 seconds
Started Jul 03 06:54:22 PM PDT 24
Finished Jul 03 07:00:48 PM PDT 24
Peak memory 202268 kb
Host smart-45f63f83-304b-44e5-b764-d22bd2f5a0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567511064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1567511064
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2154368255
Short name T9
Test name
Test status
Simulation time 332108628623 ps
CPU time 664.92 seconds
Started Jul 03 06:55:26 PM PDT 24
Finished Jul 03 07:06:31 PM PDT 24
Peak memory 201892 kb
Host smart-37d32218-8aac-428f-8270-3ca8934aa141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154368255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2154368255
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1617047423
Short name T368
Test name
Test status
Simulation time 602653195217 ps
CPU time 355.07 seconds
Started Jul 03 06:55:32 PM PDT 24
Finished Jul 03 07:01:27 PM PDT 24
Peak memory 201876 kb
Host smart-f3408c9b-b7cd-4214-bd84-b07996ad7e14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617047423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1617047423
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1862736127
Short name T178
Test name
Test status
Simulation time 339627113456 ps
CPU time 37.85 seconds
Started Jul 03 06:58:33 PM PDT 24
Finished Jul 03 06:59:12 PM PDT 24
Peak memory 201892 kb
Host smart-319174fb-7f9c-40e9-bef9-b13700672b37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862736127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1862736127
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2138344031
Short name T232
Test name
Test status
Simulation time 340975681715 ps
CPU time 205.68 seconds
Started Jul 03 07:04:44 PM PDT 24
Finished Jul 03 07:08:11 PM PDT 24
Peak memory 201992 kb
Host smart-1eea4807-d031-499f-877b-dc146b18e11c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138344031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2138344031
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.87284552
Short name T303
Test name
Test status
Simulation time 495383212659 ps
CPU time 895.26 seconds
Started Jul 03 07:06:09 PM PDT 24
Finished Jul 03 07:21:05 PM PDT 24
Peak memory 201944 kb
Host smart-dec08c96-f42d-4d46-9b39-f55e463890f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87284552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gatin
g.87284552
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.4032306015
Short name T8
Test name
Test status
Simulation time 485787034796 ps
CPU time 294.69 seconds
Started Jul 03 06:56:55 PM PDT 24
Finished Jul 03 07:01:51 PM PDT 24
Peak memory 201968 kb
Host smart-79581bbb-3dae-4cee-abd1-6c1481842fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032306015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.4032306015
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.499968088
Short name T185
Test name
Test status
Simulation time 510497278492 ps
CPU time 187.19 seconds
Started Jul 03 07:00:03 PM PDT 24
Finished Jul 03 07:03:11 PM PDT 24
Peak memory 201904 kb
Host smart-282ab638-f216-406d-bb2a-770b752f9699
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499968088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.499968088
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1664331935
Short name T269
Test name
Test status
Simulation time 154114106153 ps
CPU time 101.47 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:07:21 PM PDT 24
Peak memory 218768 kb
Host smart-9c0d7a51-9d97-4ecd-a18c-8f5be8c4b174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664331935 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1664331935
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1657033858
Short name T193
Test name
Test status
Simulation time 562736391917 ps
CPU time 544.72 seconds
Started Jul 03 07:05:58 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 201920 kb
Host smart-c8a4eed4-5b2a-4508-87e6-68a53f0cd7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657033858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1657033858
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.873830675
Short name T292
Test name
Test status
Simulation time 485758094665 ps
CPU time 594.95 seconds
Started Jul 03 07:05:59 PM PDT 24
Finished Jul 03 07:15:55 PM PDT 24
Peak memory 201928 kb
Host smart-3f571f47-ec2c-431b-8905-598f5c814bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873830675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.873830675
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1372720730
Short name T275
Test name
Test status
Simulation time 173798659914 ps
CPU time 408.28 seconds
Started Jul 03 07:06:13 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 201884 kb
Host smart-70cc88d8-2846-432e-adb2-28d816da7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372720730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1372720730
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4267445225
Short name T280
Test name
Test status
Simulation time 331241819538 ps
CPU time 188.83 seconds
Started Jul 03 06:59:39 PM PDT 24
Finished Jul 03 07:02:49 PM PDT 24
Peak memory 201948 kb
Host smart-37b0188a-ba01-467e-b310-9d65c06e1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267445225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4267445225
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.224743170
Short name T156
Test name
Test status
Simulation time 162136500889 ps
CPU time 91.75 seconds
Started Jul 03 07:04:50 PM PDT 24
Finished Jul 03 07:06:23 PM PDT 24
Peak memory 201880 kb
Host smart-afe67bec-0ffb-4744-a811-dbf9f78c8aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224743170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.224743170
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.262034384
Short name T233
Test name
Test status
Simulation time 174777779763 ps
CPU time 411.97 seconds
Started Jul 03 07:06:26 PM PDT 24
Finished Jul 03 07:13:19 PM PDT 24
Peak memory 201984 kb
Host smart-6e8e8538-77e5-4d24-b56e-b02c73be612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262034384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.262034384
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3523430153
Short name T340
Test name
Test status
Simulation time 4192967943 ps
CPU time 10.79 seconds
Started Jul 03 05:07:11 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201876 kb
Host smart-911677c0-fe68-484d-bb78-f341a4647565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523430153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3523430153
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3240407841
Short name T206
Test name
Test status
Simulation time 126221883711 ps
CPU time 628.98 seconds
Started Jul 03 06:50:29 PM PDT 24
Finished Jul 03 07:00:59 PM PDT 24
Peak memory 202240 kb
Host smart-5894a9f6-be1a-4d80-96db-6decfb72f0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240407841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3240407841
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2773358517
Short name T332
Test name
Test status
Simulation time 383895205145 ps
CPU time 865.34 seconds
Started Jul 03 06:55:04 PM PDT 24
Finished Jul 03 07:09:29 PM PDT 24
Peak memory 201956 kb
Host smart-7c39c2ed-e15c-41f2-8929-0960f1bcb8fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773358517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2773358517
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1015073487
Short name T238
Test name
Test status
Simulation time 487388280077 ps
CPU time 1105.15 seconds
Started Jul 03 06:56:32 PM PDT 24
Finished Jul 03 07:14:58 PM PDT 24
Peak memory 201880 kb
Host smart-d5cece91-28f6-400d-81b8-96b4e0a7a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015073487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1015073487
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.501319690
Short name T304
Test name
Test status
Simulation time 304871023463 ps
CPU time 643.69 seconds
Started Jul 03 06:59:13 PM PDT 24
Finished Jul 03 07:09:57 PM PDT 24
Peak memory 210408 kb
Host smart-0bb8c32d-ccf7-42f8-b98c-f02a16a5c2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501319690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
501319690
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3566890119
Short name T347
Test name
Test status
Simulation time 108894677409 ps
CPU time 391.52 seconds
Started Jul 03 07:04:38 PM PDT 24
Finished Jul 03 07:11:10 PM PDT 24
Peak memory 202228 kb
Host smart-3261b374-7215-45b3-a172-43ee27e4b2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566890119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3566890119
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1524567276
Short name T264
Test name
Test status
Simulation time 374706620014 ps
CPU time 229.26 seconds
Started Jul 03 07:04:33 PM PDT 24
Finished Jul 03 07:08:23 PM PDT 24
Peak memory 201928 kb
Host smart-5068e380-ed02-4bac-9a8a-33de7fb65ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524567276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1524567276
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.459959720
Short name T237
Test name
Test status
Simulation time 83468513032 ps
CPU time 144.86 seconds
Started Jul 03 07:06:25 PM PDT 24
Finished Jul 03 07:08:52 PM PDT 24
Peak memory 211748 kb
Host smart-4f1bb190-aeed-4f09-afd6-29a1b1356a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459959720 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.459959720
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2924228480
Short name T341
Test name
Test status
Simulation time 4313110224 ps
CPU time 3.89 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:40 PM PDT 24
Peak memory 201868 kb
Host smart-d58d779b-34e2-4f66-8568-3f9776a17302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924228480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2924228480
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1281640326
Short name T244
Test name
Test status
Simulation time 394027980176 ps
CPU time 304.77 seconds
Started Jul 03 06:54:40 PM PDT 24
Finished Jul 03 06:59:46 PM PDT 24
Peak memory 201892 kb
Host smart-2ccfbabf-f967-44e6-9bdf-f2f079df6b33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281640326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1281640326
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.4076278824
Short name T202
Test name
Test status
Simulation time 82420116805 ps
CPU time 396.79 seconds
Started Jul 03 06:54:52 PM PDT 24
Finished Jul 03 07:01:30 PM PDT 24
Peak memory 202220 kb
Host smart-048af41f-972e-41b1-bc43-b7af26e46bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076278824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4076278824
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3108335023
Short name T286
Test name
Test status
Simulation time 109934940539 ps
CPU time 182.92 seconds
Started Jul 03 06:54:55 PM PDT 24
Finished Jul 03 06:57:59 PM PDT 24
Peak memory 210436 kb
Host smart-0968525c-4046-40d2-8a5a-5a11ee50d4f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108335023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3108335023
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.132608712
Short name T50
Test name
Test status
Simulation time 543499954758 ps
CPU time 329.28 seconds
Started Jul 03 06:55:36 PM PDT 24
Finished Jul 03 07:01:07 PM PDT 24
Peak memory 201936 kb
Host smart-94801d62-80ef-4061-acd9-630aa04e29da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132608712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.132608712
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4227537250
Short name T205
Test name
Test status
Simulation time 112456111550 ps
CPU time 489.47 seconds
Started Jul 03 06:55:54 PM PDT 24
Finished Jul 03 07:04:04 PM PDT 24
Peak memory 210492 kb
Host smart-72e93e96-46a5-4d69-9b7b-97980440828f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227537250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4227537250
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3258705285
Short name T259
Test name
Test status
Simulation time 187929749018 ps
CPU time 70.47 seconds
Started Jul 03 06:58:09 PM PDT 24
Finished Jul 03 06:59:20 PM PDT 24
Peak memory 201892 kb
Host smart-dbcdc435-0fd8-4489-8dad-e439898038f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258705285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3258705285
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3233200609
Short name T37
Test name
Test status
Simulation time 469454225202 ps
CPU time 1416.19 seconds
Started Jul 03 06:58:08 PM PDT 24
Finished Jul 03 07:21:45 PM PDT 24
Peak memory 210392 kb
Host smart-5ebb6bcd-56b7-4bd8-a500-f31bebc71e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233200609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3233200609
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2688239600
Short name T218
Test name
Test status
Simulation time 331472251270 ps
CPU time 415.33 seconds
Started Jul 03 06:58:22 PM PDT 24
Finished Jul 03 07:05:17 PM PDT 24
Peak memory 201984 kb
Host smart-7d6d610c-c765-4548-9d25-6c1a592a9ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688239600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2688239600
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4087077804
Short name T194
Test name
Test status
Simulation time 580902906535 ps
CPU time 269.09 seconds
Started Jul 03 06:58:11 PM PDT 24
Finished Jul 03 07:02:41 PM PDT 24
Peak memory 201984 kb
Host smart-1eb3bd11-39b9-43c5-83ac-593c3a5d9e41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087077804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4087077804
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3844904647
Short name T342
Test name
Test status
Simulation time 86043929248 ps
CPU time 327.38 seconds
Started Jul 03 06:58:47 PM PDT 24
Finished Jul 03 07:04:14 PM PDT 24
Peak memory 202212 kb
Host smart-91e02519-dbf2-4ce9-874b-9a4d2eb40c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844904647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3844904647
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2077031132
Short name T241
Test name
Test status
Simulation time 584567239017 ps
CPU time 1324.78 seconds
Started Jul 03 06:59:23 PM PDT 24
Finished Jul 03 07:21:28 PM PDT 24
Peak memory 201952 kb
Host smart-55a7825d-5d8b-4e34-9069-64aa981cd8e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077031132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2077031132
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2169110308
Short name T210
Test name
Test status
Simulation time 92945769574 ps
CPU time 512.06 seconds
Started Jul 03 06:59:53 PM PDT 24
Finished Jul 03 07:08:26 PM PDT 24
Peak memory 202212 kb
Host smart-80f0a91c-0705-4bc4-a9d4-7c828b0e2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169110308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2169110308
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.668930204
Short name T211
Test name
Test status
Simulation time 80328990729 ps
CPU time 272.63 seconds
Started Jul 03 07:00:07 PM PDT 24
Finished Jul 03 07:04:40 PM PDT 24
Peak memory 202196 kb
Host smart-1ab08d41-b6d9-48cf-9ebb-c27931232e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668930204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.668930204
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.4244998695
Short name T261
Test name
Test status
Simulation time 340690516811 ps
CPU time 176.13 seconds
Started Jul 03 07:04:47 PM PDT 24
Finished Jul 03 07:07:45 PM PDT 24
Peak memory 201916 kb
Host smart-ff2ee8ed-e3fd-409a-8009-60c72b9e7a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244998695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.4244998695
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3717852623
Short name T345
Test name
Test status
Simulation time 90386035251 ps
CPU time 497.03 seconds
Started Jul 03 07:05:24 PM PDT 24
Finished Jul 03 07:13:42 PM PDT 24
Peak memory 202180 kb
Host smart-9cb9695e-8b24-4507-9b37-7fe2bc81a0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717852623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3717852623
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3941020950
Short name T216
Test name
Test status
Simulation time 497412988705 ps
CPU time 41.6 seconds
Started Jul 03 06:52:05 PM PDT 24
Finished Jul 03 06:52:47 PM PDT 24
Peak memory 201916 kb
Host smart-d4a05fce-228e-4661-b89e-b742afc4dd64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941020950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3941020950
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.337897198
Short name T281
Test name
Test status
Simulation time 167536625509 ps
CPU time 343.45 seconds
Started Jul 03 06:51:53 PM PDT 24
Finished Jul 03 06:57:37 PM PDT 24
Peak memory 201988 kb
Host smart-5748ac29-e173-4fbf-ab55-5b861af6780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337897198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.337897198
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.564917306
Short name T155
Test name
Test status
Simulation time 336487921355 ps
CPU time 414.13 seconds
Started Jul 03 07:05:51 PM PDT 24
Finished Jul 03 07:12:48 PM PDT 24
Peak memory 201924 kb
Host smart-e4658ed0-b8b0-4912-8c2f-fa6ca94ca5bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564917306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.564917306
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.888323005
Short name T315
Test name
Test status
Simulation time 167772868788 ps
CPU time 388.54 seconds
Started Jul 03 07:06:21 PM PDT 24
Finished Jul 03 07:12:52 PM PDT 24
Peak memory 201912 kb
Host smart-d459d51a-9d96-4ffb-9f21-ff6c60688002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888323005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.888323005
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1313267344
Short name T121
Test name
Test status
Simulation time 836921612 ps
CPU time 3.23 seconds
Started Jul 03 05:06:33 PM PDT 24
Finished Jul 03 05:06:36 PM PDT 24
Peak memory 201616 kb
Host smart-d2d37021-299a-4af4-bf61-dc1cea2a484f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313267344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1313267344
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2813567864
Short name T127
Test name
Test status
Simulation time 40814741869 ps
CPU time 82.77 seconds
Started Jul 03 05:06:34 PM PDT 24
Finished Jul 03 05:07:57 PM PDT 24
Peak memory 201784 kb
Host smart-4a7ba320-280f-4a08-9428-d5c3d502a491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813567864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2813567864
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.735683148
Short name T131
Test name
Test status
Simulation time 1420259373 ps
CPU time 1.03 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:06:20 PM PDT 24
Peak memory 201456 kb
Host smart-82d9ae67-6c07-46e8-83bd-ee28bc707586
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735683148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.735683148
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2832717319
Short name T904
Test name
Test status
Simulation time 528409032 ps
CPU time 1.3 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:38 PM PDT 24
Peak memory 201560 kb
Host smart-681e4dd8-7ea2-4e76-81ef-5056437802c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832717319 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2832717319
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2578068224
Short name T909
Test name
Test status
Simulation time 298664048 ps
CPU time 1.35 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:06:20 PM PDT 24
Peak memory 201456 kb
Host smart-791c8b0c-c5c6-4aa5-bd0a-823a3a0d393a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578068224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2578068224
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.622627318
Short name T804
Test name
Test status
Simulation time 484330378 ps
CPU time 0.91 seconds
Started Jul 03 05:06:22 PM PDT 24
Finished Jul 03 05:06:24 PM PDT 24
Peak memory 201456 kb
Host smart-fc8b7058-ecc2-40cd-9a1a-16c7fac0721e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622627318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.622627318
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3009441378
Short name T844
Test name
Test status
Simulation time 2151854509 ps
CPU time 2.14 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 201620 kb
Host smart-5782d7cf-64e5-49c5-beb2-a6be851e1eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009441378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3009441378
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.559439801
Short name T836
Test name
Test status
Simulation time 571198861 ps
CPU time 1.34 seconds
Started Jul 03 05:06:22 PM PDT 24
Finished Jul 03 05:06:24 PM PDT 24
Peak memory 201792 kb
Host smart-c5e192dc-92c0-435e-abf3-7c25528649ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559439801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.559439801
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.542102900
Short name T882
Test name
Test status
Simulation time 4509402076 ps
CPU time 4.25 seconds
Started Jul 03 05:06:21 PM PDT 24
Finished Jul 03 05:06:26 PM PDT 24
Peak memory 201772 kb
Host smart-d4bebc2b-8407-4736-8d52-e682540b0606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542102900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.542102900
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1586096365
Short name T125
Test name
Test status
Simulation time 968713315 ps
CPU time 4.21 seconds
Started Jul 03 05:06:35 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 201712 kb
Host smart-02068620-f8cd-468a-8dfb-b6708d7436fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586096365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1586096365
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4164163873
Short name T915
Test name
Test status
Simulation time 41307529224 ps
CPU time 94.46 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:08:11 PM PDT 24
Peak memory 201840 kb
Host smart-0e0f9d76-8389-48dc-a476-46587d97a1fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164163873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4164163873
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2904919747
Short name T893
Test name
Test status
Simulation time 656021023 ps
CPU time 2.14 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 201532 kb
Host smart-eeae1b6a-9cae-4fa2-9bfc-9fa6f75469bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904919747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2904919747
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.233621191
Short name T891
Test name
Test status
Simulation time 472297223 ps
CPU time 1.3 seconds
Started Jul 03 05:06:35 PM PDT 24
Finished Jul 03 05:06:37 PM PDT 24
Peak memory 201560 kb
Host smart-715dd123-325d-419c-a96c-857202f274f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233621191 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.233621191
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1139776451
Short name T138
Test name
Test status
Simulation time 511472753 ps
CPU time 1.06 seconds
Started Jul 03 05:06:38 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 201476 kb
Host smart-cbe32967-7fd4-4c74-ba99-da45dd164bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139776451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1139776451
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.534624569
Short name T899
Test name
Test status
Simulation time 450701242 ps
CPU time 0.91 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:38 PM PDT 24
Peak memory 201464 kb
Host smart-becf40f8-c282-4cf5-bf12-f822abfcf8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534624569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.534624569
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3852201316
Short name T843
Test name
Test status
Simulation time 2592591378 ps
CPU time 5.06 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:41 PM PDT 24
Peak memory 201596 kb
Host smart-25443367-e25e-45a1-adb2-e5325a3ac7ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852201316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3852201316
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1338639665
Short name T71
Test name
Test status
Simulation time 387732563 ps
CPU time 2.32 seconds
Started Jul 03 05:06:34 PM PDT 24
Finished Jul 03 05:06:37 PM PDT 24
Peak memory 201768 kb
Host smart-b28dcf9e-5346-4181-afe2-dae533ef3406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338639665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1338639665
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3822370589
Short name T818
Test name
Test status
Simulation time 4269327596 ps
CPU time 11.69 seconds
Started Jul 03 05:06:35 PM PDT 24
Finished Jul 03 05:06:47 PM PDT 24
Peak memory 201752 kb
Host smart-0b155ced-26d8-44f3-a5bc-33c90f4358b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822370589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3822370589
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3909638345
Short name T910
Test name
Test status
Simulation time 356361296 ps
CPU time 1.63 seconds
Started Jul 03 05:07:11 PM PDT 24
Finished Jul 03 05:07:14 PM PDT 24
Peak memory 201580 kb
Host smart-be0153ff-4851-454c-a079-4ad02f2b186d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909638345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3909638345
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3056900404
Short name T879
Test name
Test status
Simulation time 537559715 ps
CPU time 1.26 seconds
Started Jul 03 05:07:10 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 201464 kb
Host smart-cce2d75c-64b9-459a-8b13-6313f318327d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056900404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3056900404
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.129895744
Short name T811
Test name
Test status
Simulation time 410223704 ps
CPU time 0.9 seconds
Started Jul 03 05:07:08 PM PDT 24
Finished Jul 03 05:07:09 PM PDT 24
Peak memory 201428 kb
Host smart-7d125f97-ce3e-4a1b-a899-4292eb49b611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129895744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.129895744
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2664045676
Short name T848
Test name
Test status
Simulation time 2127772974 ps
CPU time 3.2 seconds
Started Jul 03 05:07:13 PM PDT 24
Finished Jul 03 05:07:17 PM PDT 24
Peak memory 201372 kb
Host smart-3113841c-dc2c-49fa-baef-01fe9ecada6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664045676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2664045676
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1481285795
Short name T65
Test name
Test status
Simulation time 4219517912 ps
CPU time 3.18 seconds
Started Jul 03 05:07:08 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 201804 kb
Host smart-bb1b3b6c-5257-4c78-9278-a165763bac16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481285795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1481285795
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1855882643
Short name T905
Test name
Test status
Simulation time 498674178 ps
CPU time 1.59 seconds
Started Jul 03 05:07:11 PM PDT 24
Finished Jul 03 05:07:13 PM PDT 24
Peak memory 201532 kb
Host smart-859a571e-56ba-4aa8-bdaa-fbc3a4380175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855882643 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1855882643
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.62594027
Short name T847
Test name
Test status
Simulation time 531382499 ps
CPU time 1.88 seconds
Started Jul 03 05:07:12 PM PDT 24
Finished Jul 03 05:07:14 PM PDT 24
Peak memory 201484 kb
Host smart-43dda84d-05b2-45c5-9d52-1b9f66fd53a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62594027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.62594027
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3736656316
Short name T812
Test name
Test status
Simulation time 511043867 ps
CPU time 0.89 seconds
Started Jul 03 05:07:08 PM PDT 24
Finished Jul 03 05:07:10 PM PDT 24
Peak memory 201308 kb
Host smart-453074d5-d957-4324-a7a5-9957a7f14fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736656316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3736656316
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.859270703
Short name T807
Test name
Test status
Simulation time 2594526283 ps
CPU time 2.74 seconds
Started Jul 03 05:07:12 PM PDT 24
Finished Jul 03 05:07:15 PM PDT 24
Peak memory 201572 kb
Host smart-8bd9f4f5-963f-4e26-8c3b-5db3c0e00a15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859270703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.859270703
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.800812588
Short name T73
Test name
Test status
Simulation time 423530517 ps
CPU time 2.86 seconds
Started Jul 03 05:07:13 PM PDT 24
Finished Jul 03 05:07:16 PM PDT 24
Peak memory 201772 kb
Host smart-94184d73-c342-4e49-9818-9ee86cedd804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800812588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.800812588
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2492826828
Short name T66
Test name
Test status
Simulation time 4005238993 ps
CPU time 11.7 seconds
Started Jul 03 05:07:13 PM PDT 24
Finished Jul 03 05:07:25 PM PDT 24
Peak memory 201844 kb
Host smart-b48a76d1-762a-4288-b9f6-8d3fa1a3c3b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492826828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2492826828
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1739320951
Short name T867
Test name
Test status
Simulation time 571352541 ps
CPU time 2.05 seconds
Started Jul 03 05:07:12 PM PDT 24
Finished Jul 03 05:07:15 PM PDT 24
Peak memory 201564 kb
Host smart-04ec583b-8836-4481-837f-9a003fcd96ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739320951 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1739320951
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.634737254
Short name T123
Test name
Test status
Simulation time 360233752 ps
CPU time 1.07 seconds
Started Jul 03 05:07:08 PM PDT 24
Finished Jul 03 05:07:10 PM PDT 24
Peak memory 201504 kb
Host smart-8d449f9f-b14b-4e96-8978-a31740815c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634737254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.634737254
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.82408490
Short name T809
Test name
Test status
Simulation time 304203228 ps
CPU time 1.35 seconds
Started Jul 03 05:07:10 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 201372 kb
Host smart-1c0b75e0-fa90-4709-a781-71850eaa2f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82408490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.82408490
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4172555185
Short name T918
Test name
Test status
Simulation time 520407251 ps
CPU time 1.43 seconds
Started Jul 03 05:07:14 PM PDT 24
Finished Jul 03 05:07:16 PM PDT 24
Peak memory 201736 kb
Host smart-b36fbf53-1578-4469-9c0f-8eb7de3f078d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172555185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4172555185
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.805885486
Short name T832
Test name
Test status
Simulation time 4611187796 ps
CPU time 10.21 seconds
Started Jul 03 05:07:11 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201832 kb
Host smart-1e229f8a-b561-4dfb-8a6e-7126379a9af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805885486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.805885486
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2442083852
Short name T888
Test name
Test status
Simulation time 459877000 ps
CPU time 2.12 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:19 PM PDT 24
Peak memory 201548 kb
Host smart-621dc3f6-1993-4cb5-8a68-fa444969789a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442083852 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2442083852
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2523742436
Short name T827
Test name
Test status
Simulation time 343319765 ps
CPU time 1.57 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:19 PM PDT 24
Peak memory 201484 kb
Host smart-6ef32a09-6afd-4f42-abfa-5d8db3cbb157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523742436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2523742436
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1459076423
Short name T846
Test name
Test status
Simulation time 526417029 ps
CPU time 1.12 seconds
Started Jul 03 05:07:11 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 201444 kb
Host smart-c1d13025-b278-4599-bbee-38748440c300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459076423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1459076423
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.30292419
Short name T881
Test name
Test status
Simulation time 4122053652 ps
CPU time 4.38 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201848 kb
Host smart-76a3e249-2f1a-48c7-8802-92af4e4e04f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30292419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ct
rl_same_csr_outstanding.30292419
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.424023540
Short name T77
Test name
Test status
Simulation time 391596895 ps
CPU time 1.51 seconds
Started Jul 03 05:07:10 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 201528 kb
Host smart-a90a6fcc-3adf-41d6-9d45-4d9bf5832b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424023540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.424023540
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3373962806
Short name T821
Test name
Test status
Simulation time 469539364 ps
CPU time 1.08 seconds
Started Jul 03 05:07:20 PM PDT 24
Finished Jul 03 05:07:21 PM PDT 24
Peak memory 201556 kb
Host smart-d5b89cf7-0d00-4025-8a42-20e0902398c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373962806 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3373962806
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1602196436
Short name T134
Test name
Test status
Simulation time 348134456 ps
CPU time 1.48 seconds
Started Jul 03 05:07:16 PM PDT 24
Finished Jul 03 05:07:18 PM PDT 24
Peak memory 201488 kb
Host smart-e0498d98-fd47-4b33-9ad4-011b371b5e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602196436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1602196436
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2693442151
Short name T877
Test name
Test status
Simulation time 538896879 ps
CPU time 0.95 seconds
Started Jul 03 05:07:16 PM PDT 24
Finished Jul 03 05:07:17 PM PDT 24
Peak memory 201440 kb
Host smart-92ee49e3-4b2e-4f65-b9ba-5ffd7cf5e008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693442151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2693442151
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2289885535
Short name T906
Test name
Test status
Simulation time 2730451202 ps
CPU time 2.11 seconds
Started Jul 03 05:07:19 PM PDT 24
Finished Jul 03 05:07:21 PM PDT 24
Peak memory 201596 kb
Host smart-a60595c2-e63f-4f12-9fc1-ac0b7ae9ca59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289885535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2289885535
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.475604681
Short name T831
Test name
Test status
Simulation time 559671451 ps
CPU time 2.91 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:21 PM PDT 24
Peak memory 217588 kb
Host smart-8c9ed15b-b8c7-4ca9-a624-84b483c56bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475604681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.475604681
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2466448308
Short name T883
Test name
Test status
Simulation time 8285272349 ps
CPU time 7.47 seconds
Started Jul 03 05:07:20 PM PDT 24
Finished Jul 03 05:07:27 PM PDT 24
Peak memory 201832 kb
Host smart-abcd3a50-31f5-4332-ad8a-87723002fcf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466448308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2466448308
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1768645031
Short name T833
Test name
Test status
Simulation time 477068862 ps
CPU time 1.46 seconds
Started Jul 03 05:07:16 PM PDT 24
Finished Jul 03 05:07:18 PM PDT 24
Peak memory 201580 kb
Host smart-fe691a88-56d7-49e0-8ca4-f3f10c918a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768645031 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1768645031
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1196044969
Short name T816
Test name
Test status
Simulation time 491991692 ps
CPU time 0.69 seconds
Started Jul 03 05:07:16 PM PDT 24
Finished Jul 03 05:07:17 PM PDT 24
Peak memory 201440 kb
Host smart-ba8e1567-96aa-491f-88b6-b2790a808cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196044969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1196044969
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2990305819
Short name T34
Test name
Test status
Simulation time 2275060833 ps
CPU time 8.21 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:26 PM PDT 24
Peak memory 201604 kb
Host smart-be32e894-51a9-4dc1-9f66-516d342514cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990305819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2990305819
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1856390906
Short name T839
Test name
Test status
Simulation time 731811721 ps
CPU time 1.77 seconds
Started Jul 03 05:07:20 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201804 kb
Host smart-050628c7-c9de-4f3d-b796-b5e767ddf21c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856390906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1856390906
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.833076339
Short name T914
Test name
Test status
Simulation time 8409422322 ps
CPU time 21.11 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:38 PM PDT 24
Peak memory 201888 kb
Host smart-c570c50d-9058-4630-85b8-b49cc700291d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833076339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.833076339
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3570186641
Short name T22
Test name
Test status
Simulation time 625179517 ps
CPU time 2.22 seconds
Started Jul 03 05:07:21 PM PDT 24
Finished Jul 03 05:07:24 PM PDT 24
Peak memory 201576 kb
Host smart-24073683-e3ec-43de-891c-cdcd9a0a8a5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570186641 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3570186641
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.547998239
Short name T895
Test name
Test status
Simulation time 438800555 ps
CPU time 1.88 seconds
Started Jul 03 05:07:20 PM PDT 24
Finished Jul 03 05:07:23 PM PDT 24
Peak memory 201484 kb
Host smart-2ea4bfee-e464-43aa-88ad-a1c69a3a4316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547998239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.547998239
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1749129866
Short name T824
Test name
Test status
Simulation time 370497046 ps
CPU time 0.83 seconds
Started Jul 03 05:07:22 PM PDT 24
Finished Jul 03 05:07:23 PM PDT 24
Peak memory 201400 kb
Host smart-08c5ff44-f9f9-4cee-b97d-b46623f6bc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749129866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1749129866
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2504512518
Short name T137
Test name
Test status
Simulation time 5074283326 ps
CPU time 15.9 seconds
Started Jul 03 05:07:22 PM PDT 24
Finished Jul 03 05:07:38 PM PDT 24
Peak memory 201788 kb
Host smart-97e624c5-9e30-46a6-bb27-5fb23b466580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504512518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2504512518
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.644831555
Short name T873
Test name
Test status
Simulation time 538107383 ps
CPU time 3.04 seconds
Started Jul 03 05:07:18 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201756 kb
Host smart-e77d7e51-03f2-450a-b1c6-bebb0b92144d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644831555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.644831555
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2002251623
Short name T868
Test name
Test status
Simulation time 4336671413 ps
CPU time 11.64 seconds
Started Jul 03 05:07:17 PM PDT 24
Finished Jul 03 05:07:29 PM PDT 24
Peak memory 201820 kb
Host smart-6f750347-78f7-4136-b27a-fa6e61658e91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002251623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2002251623
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.336514976
Short name T911
Test name
Test status
Simulation time 605460954 ps
CPU time 1.18 seconds
Started Jul 03 05:07:22 PM PDT 24
Finished Jul 03 05:07:23 PM PDT 24
Peak memory 201528 kb
Host smart-1ddf4a26-89cd-4113-84e0-2726fa790f45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336514976 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.336514976
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.334464651
Short name T120
Test name
Test status
Simulation time 326961133 ps
CPU time 1.46 seconds
Started Jul 03 05:07:21 PM PDT 24
Finished Jul 03 05:07:23 PM PDT 24
Peak memory 201380 kb
Host smart-3e308747-fa92-43c8-a2c8-5e56d6760887
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334464651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.334464651
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4055363854
Short name T805
Test name
Test status
Simulation time 340230501 ps
CPU time 1.37 seconds
Started Jul 03 05:07:23 PM PDT 24
Finished Jul 03 05:07:24 PM PDT 24
Peak memory 201380 kb
Host smart-b97eddf4-70cd-4ab3-8ce2-8fb679d76fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055363854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4055363854
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.4252694897
Short name T876
Test name
Test status
Simulation time 5865385540 ps
CPU time 22.19 seconds
Started Jul 03 05:07:22 PM PDT 24
Finished Jul 03 05:07:44 PM PDT 24
Peak memory 201852 kb
Host smart-bab99c63-3ef6-4de0-b17e-f160d9176458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252694897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.4252694897
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3342854428
Short name T842
Test name
Test status
Simulation time 623187660 ps
CPU time 2.91 seconds
Started Jul 03 05:07:22 PM PDT 24
Finished Jul 03 05:07:26 PM PDT 24
Peak memory 209976 kb
Host smart-97f51499-c3f1-46c0-ade6-2bf56a0225f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342854428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3342854428
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1875165374
Short name T857
Test name
Test status
Simulation time 3901299990 ps
CPU time 6.5 seconds
Started Jul 03 05:07:20 PM PDT 24
Finished Jul 03 05:07:27 PM PDT 24
Peak memory 201780 kb
Host smart-e46d6f3c-f22d-4581-beb9-563861279b94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875165374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1875165374
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.588114482
Short name T23
Test name
Test status
Simulation time 502181321 ps
CPU time 2.11 seconds
Started Jul 03 05:07:27 PM PDT 24
Finished Jul 03 05:07:29 PM PDT 24
Peak memory 201564 kb
Host smart-e9629201-cae8-4a7e-a66c-a0e4836b2dc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588114482 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.588114482
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.392402127
Short name T853
Test name
Test status
Simulation time 493893300 ps
CPU time 1.82 seconds
Started Jul 03 05:07:20 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201496 kb
Host smart-a0650277-e6b9-4737-9ec6-ef19e38d2139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392402127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.392402127
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4196742000
Short name T801
Test name
Test status
Simulation time 536259818 ps
CPU time 1.14 seconds
Started Jul 03 05:07:22 PM PDT 24
Finished Jul 03 05:07:23 PM PDT 24
Peak memory 201376 kb
Host smart-bf4c6b9e-d245-4d43-820d-5309f5595485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196742000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4196742000
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1154396154
Short name T880
Test name
Test status
Simulation time 4656351817 ps
CPU time 10.63 seconds
Started Jul 03 05:07:21 PM PDT 24
Finished Jul 03 05:07:33 PM PDT 24
Peak memory 201816 kb
Host smart-620810ae-7b24-49da-bc5f-9d7cda075fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154396154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1154396154
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4049035720
Short name T72
Test name
Test status
Simulation time 563665853 ps
CPU time 2.41 seconds
Started Jul 03 05:07:23 PM PDT 24
Finished Jul 03 05:07:26 PM PDT 24
Peak memory 201712 kb
Host smart-532cafdb-6300-434b-bd0a-66c8815d12ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049035720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4049035720
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.674598174
Short name T822
Test name
Test status
Simulation time 4281144822 ps
CPU time 11.98 seconds
Started Jul 03 05:07:21 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201852 kb
Host smart-20f74b0e-f622-442c-8040-b50e77403b73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674598174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.674598174
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1955606553
Short name T810
Test name
Test status
Simulation time 501476923 ps
CPU time 2.16 seconds
Started Jul 03 05:07:25 PM PDT 24
Finished Jul 03 05:07:28 PM PDT 24
Peak memory 201544 kb
Host smart-1043e851-e5d0-4799-abdc-b0c5bff0f644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955606553 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1955606553
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.581761845
Short name T901
Test name
Test status
Simulation time 450556127 ps
CPU time 0.87 seconds
Started Jul 03 05:07:28 PM PDT 24
Finished Jul 03 05:07:30 PM PDT 24
Peak memory 200944 kb
Host smart-2ad99b53-71f1-40a4-997b-62ec6566d82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581761845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.581761845
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1817848143
Short name T850
Test name
Test status
Simulation time 385293793 ps
CPU time 1.5 seconds
Started Jul 03 05:07:28 PM PDT 24
Finished Jul 03 05:07:30 PM PDT 24
Peak memory 200988 kb
Host smart-54872ad7-2b41-4913-9f7b-ba444e4c207d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817848143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1817848143
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.592465843
Short name T20
Test name
Test status
Simulation time 2483719276 ps
CPU time 8.53 seconds
Started Jul 03 05:07:26 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201652 kb
Host smart-b66bd6b6-3a73-486b-b74c-4728001f6dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592465843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.592465843
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.716977131
Short name T919
Test name
Test status
Simulation time 521363567 ps
CPU time 3.17 seconds
Started Jul 03 05:07:25 PM PDT 24
Finished Jul 03 05:07:28 PM PDT 24
Peak memory 218016 kb
Host smart-9d5a585e-2cc6-4f68-be9d-72399b05b9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716977131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.716977131
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3990219984
Short name T79
Test name
Test status
Simulation time 8065181674 ps
CPU time 20.44 seconds
Started Jul 03 05:07:25 PM PDT 24
Finished Jul 03 05:07:45 PM PDT 24
Peak memory 201836 kb
Host smart-4606e008-c63c-425d-8aa8-0278803f24b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990219984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3990219984
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1361643632
Short name T128
Test name
Test status
Simulation time 415007578 ps
CPU time 2.48 seconds
Started Jul 03 05:06:37 PM PDT 24
Finished Jul 03 05:06:40 PM PDT 24
Peak memory 201728 kb
Host smart-0541634d-3c9a-4371-8bdd-b731ecedaf0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361643632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1361643632
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.544773591
Short name T815
Test name
Test status
Simulation time 28142937904 ps
CPU time 6.5 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:43 PM PDT 24
Peak memory 201772 kb
Host smart-188420ba-7b2a-4c50-9d4b-c88ef8242d93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544773591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.544773591
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1392138658
Short name T139
Test name
Test status
Simulation time 614239540 ps
CPU time 2.2 seconds
Started Jul 03 05:06:37 PM PDT 24
Finished Jul 03 05:06:40 PM PDT 24
Peak memory 201464 kb
Host smart-3d8aef3e-9bd7-4af8-83f7-14a0d8a950eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392138658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1392138658
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1709689047
Short name T897
Test name
Test status
Simulation time 641152635 ps
CPU time 1.06 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:37 PM PDT 24
Peak memory 201592 kb
Host smart-f57cb925-ee4c-4b52-b2f0-dd18636e9db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709689047 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1709689047
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4172700680
Short name T902
Test name
Test status
Simulation time 373866984 ps
CPU time 0.81 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:37 PM PDT 24
Peak memory 201520 kb
Host smart-a9837924-a68e-4d6e-b50f-2651a0e240f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172700680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4172700680
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.717984734
Short name T837
Test name
Test status
Simulation time 378524387 ps
CPU time 1.39 seconds
Started Jul 03 05:06:36 PM PDT 24
Finished Jul 03 05:06:38 PM PDT 24
Peak memory 201420 kb
Host smart-591670f3-7d27-4c4e-9f4b-a65fbabe4303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717984734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.717984734
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1849459299
Short name T830
Test name
Test status
Simulation time 2374625516 ps
CPU time 2.13 seconds
Started Jul 03 05:06:37 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 201592 kb
Host smart-ac77135a-83bf-4ad1-bae0-3f88c3efb7f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849459299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1849459299
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4667980
Short name T913
Test name
Test status
Simulation time 1468944327 ps
CPU time 1.96 seconds
Started Jul 03 05:06:35 PM PDT 24
Finished Jul 03 05:06:37 PM PDT 24
Peak memory 201792 kb
Host smart-7225fefa-8d24-4a53-a4d9-a6354aa19eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4667980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4667980
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1749009594
Short name T862
Test name
Test status
Simulation time 505671277 ps
CPU time 0.97 seconds
Started Jul 03 05:07:26 PM PDT 24
Finished Jul 03 05:07:28 PM PDT 24
Peak memory 201404 kb
Host smart-5457f46c-146d-4ed1-8138-a77fff61e1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749009594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1749009594
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4198610850
Short name T886
Test name
Test status
Simulation time 312813041 ps
CPU time 0.8 seconds
Started Jul 03 05:07:24 PM PDT 24
Finished Jul 03 05:07:25 PM PDT 24
Peak memory 201344 kb
Host smart-463acf93-5d54-4722-b9ec-4d5abeab7b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198610850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4198610850
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1759541389
Short name T872
Test name
Test status
Simulation time 339175058 ps
CPU time 1.42 seconds
Started Jul 03 05:07:26 PM PDT 24
Finished Jul 03 05:07:28 PM PDT 24
Peak memory 201400 kb
Host smart-6499bcef-c758-4b2b-84ec-a93832b8d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759541389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1759541389
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.29828371
Short name T917
Test name
Test status
Simulation time 471018506 ps
CPU time 1.64 seconds
Started Jul 03 05:07:27 PM PDT 24
Finished Jul 03 05:07:29 PM PDT 24
Peak memory 201400 kb
Host smart-e330459c-64f3-4474-a86e-a47acd094116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29828371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.29828371
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2167200539
Short name T866
Test name
Test status
Simulation time 471379037 ps
CPU time 0.91 seconds
Started Jul 03 05:07:28 PM PDT 24
Finished Jul 03 05:07:29 PM PDT 24
Peak memory 201456 kb
Host smart-2823fb71-3bca-4fe3-ba9e-2d542a88578e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167200539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2167200539
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1910528696
Short name T884
Test name
Test status
Simulation time 345326998 ps
CPU time 1.43 seconds
Started Jul 03 05:07:28 PM PDT 24
Finished Jul 03 05:07:30 PM PDT 24
Peak memory 201404 kb
Host smart-4e5ee291-2b06-4ceb-90e5-e18098d1743c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910528696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1910528696
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2420673801
Short name T802
Test name
Test status
Simulation time 293840548 ps
CPU time 1.31 seconds
Started Jul 03 05:07:30 PM PDT 24
Finished Jul 03 05:07:32 PM PDT 24
Peak memory 201368 kb
Host smart-bfcd455e-203d-40cd-adab-b70ce55d2d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420673801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2420673801
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1520460759
Short name T841
Test name
Test status
Simulation time 503618366 ps
CPU time 0.85 seconds
Started Jul 03 05:07:29 PM PDT 24
Finished Jul 03 05:07:30 PM PDT 24
Peak memory 201428 kb
Host smart-7f55478f-bbc2-4302-b4ac-bbb7d266a7e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520460759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1520460759
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2963156035
Short name T823
Test name
Test status
Simulation time 426215353 ps
CPU time 1.62 seconds
Started Jul 03 05:07:34 PM PDT 24
Finished Jul 03 05:07:36 PM PDT 24
Peak memory 201428 kb
Host smart-f01c50d3-ef12-43d0-bc03-1b2fac106006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963156035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2963156035
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4057692297
Short name T864
Test name
Test status
Simulation time 331373739 ps
CPU time 1.43 seconds
Started Jul 03 05:07:32 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201408 kb
Host smart-3529e320-cb76-42e7-be40-550085279175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057692297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4057692297
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3936212404
Short name T871
Test name
Test status
Simulation time 1447621661 ps
CPU time 2.56 seconds
Started Jul 03 05:06:40 PM PDT 24
Finished Jul 03 05:06:43 PM PDT 24
Peak memory 201740 kb
Host smart-9b533a53-80bc-4b8d-a278-8f8c6f61e8a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936212404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3936212404
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1579441890
Short name T126
Test name
Test status
Simulation time 44514544091 ps
CPU time 139.27 seconds
Started Jul 03 05:06:41 PM PDT 24
Finished Jul 03 05:09:01 PM PDT 24
Peak memory 201820 kb
Host smart-1d246bb4-d457-428b-95bb-0023527220fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579441890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1579441890
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2743012874
Short name T916
Test name
Test status
Simulation time 859864100 ps
CPU time 0.9 seconds
Started Jul 03 05:06:41 PM PDT 24
Finished Jul 03 05:06:42 PM PDT 24
Peak memory 201504 kb
Host smart-2cb5af33-e15b-40ae-bc5f-b044c320bde5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743012874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2743012874
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4129787269
Short name T894
Test name
Test status
Simulation time 568003210 ps
CPU time 0.95 seconds
Started Jul 03 05:06:49 PM PDT 24
Finished Jul 03 05:06:50 PM PDT 24
Peak memory 201536 kb
Host smart-bb581975-79c4-4d3c-94a8-34c38e4b15e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129787269 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4129787269
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2054230100
Short name T122
Test name
Test status
Simulation time 445912866 ps
CPU time 1.98 seconds
Started Jul 03 05:06:41 PM PDT 24
Finished Jul 03 05:06:43 PM PDT 24
Peak memory 201452 kb
Host smart-9ffd3d87-c131-4c7e-afbd-59f64726d6b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054230100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2054230100
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3297381433
Short name T870
Test name
Test status
Simulation time 290953600 ps
CPU time 1.18 seconds
Started Jul 03 05:06:37 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 201436 kb
Host smart-fa6afbb3-061b-4dc6-a6ae-b1a5daeb678a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297381433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3297381433
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2803013414
Short name T826
Test name
Test status
Simulation time 4564228937 ps
CPU time 5.96 seconds
Started Jul 03 05:06:42 PM PDT 24
Finished Jul 03 05:06:49 PM PDT 24
Peak memory 201868 kb
Host smart-93ecb1c8-78c8-43ed-90ba-c6f891bf238c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803013414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2803013414
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3972240558
Short name T885
Test name
Test status
Simulation time 541126586 ps
CPU time 3.64 seconds
Started Jul 03 05:06:37 PM PDT 24
Finished Jul 03 05:06:41 PM PDT 24
Peak memory 201844 kb
Host smart-bc0eacd9-9c68-4549-884a-8693c4abfcbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972240558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3972240558
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1987082470
Short name T860
Test name
Test status
Simulation time 485226853 ps
CPU time 0.86 seconds
Started Jul 03 05:07:33 PM PDT 24
Finished Jul 03 05:07:35 PM PDT 24
Peak memory 201444 kb
Host smart-94107c32-35a0-469c-b84e-8a309a509266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987082470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1987082470
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2677166318
Short name T852
Test name
Test status
Simulation time 440912236 ps
CPU time 1.17 seconds
Started Jul 03 05:07:33 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201400 kb
Host smart-0096d6e1-7cd2-4ba6-be21-2a78ac253c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677166318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2677166318
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2896792327
Short name T849
Test name
Test status
Simulation time 421312877 ps
CPU time 1.59 seconds
Started Jul 03 05:07:35 PM PDT 24
Finished Jul 03 05:07:37 PM PDT 24
Peak memory 201428 kb
Host smart-730a08bc-a9cc-4184-9662-eeeb73f831a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896792327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2896792327
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2566482215
Short name T838
Test name
Test status
Simulation time 495075710 ps
CPU time 1.19 seconds
Started Jul 03 05:07:32 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201428 kb
Host smart-f4c71713-cb23-45f9-8397-76c726674214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566482215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2566482215
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3442573592
Short name T806
Test name
Test status
Simulation time 504985612 ps
CPU time 1.24 seconds
Started Jul 03 05:07:32 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201436 kb
Host smart-23885942-0cc8-421d-8f9c-3e59e2d698c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442573592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3442573592
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1311049528
Short name T808
Test name
Test status
Simulation time 338447035 ps
CPU time 1.61 seconds
Started Jul 03 05:07:35 PM PDT 24
Finished Jul 03 05:07:37 PM PDT 24
Peak memory 201424 kb
Host smart-2ba68e4a-af3c-486e-b903-c85745379908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311049528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1311049528
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2239510932
Short name T851
Test name
Test status
Simulation time 508368790 ps
CPU time 1.64 seconds
Started Jul 03 05:07:36 PM PDT 24
Finished Jul 03 05:07:37 PM PDT 24
Peak memory 201428 kb
Host smart-0d0dbd29-e978-49c7-b6e6-d247500cb648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239510932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2239510932
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2557539755
Short name T845
Test name
Test status
Simulation time 419737099 ps
CPU time 1.62 seconds
Started Jul 03 05:07:33 PM PDT 24
Finished Jul 03 05:07:35 PM PDT 24
Peak memory 201432 kb
Host smart-2fc19cd1-861a-4759-b4f2-14d1584cb3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557539755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2557539755
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3900506148
Short name T854
Test name
Test status
Simulation time 366411512 ps
CPU time 1.47 seconds
Started Jul 03 05:07:32 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 201392 kb
Host smart-dd0804a1-1a90-4e6a-98d0-37193f0b4e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900506148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3900506148
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2854466314
Short name T828
Test name
Test status
Simulation time 432201268 ps
CPU time 0.95 seconds
Started Jul 03 05:07:38 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 201428 kb
Host smart-b0e19c34-869a-46f6-a9a3-2185537ed9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854466314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2854466314
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3290505644
Short name T129
Test name
Test status
Simulation time 955115559 ps
CPU time 3.9 seconds
Started Jul 03 05:06:46 PM PDT 24
Finished Jul 03 05:06:50 PM PDT 24
Peak memory 201708 kb
Host smart-7caf7643-3fe2-40d8-8927-712383063bfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290505644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3290505644
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.519003144
Short name T130
Test name
Test status
Simulation time 2384842964 ps
CPU time 4.36 seconds
Started Jul 03 05:06:46 PM PDT 24
Finished Jul 03 05:06:51 PM PDT 24
Peak memory 201800 kb
Host smart-c62b0d8b-4012-4904-a507-aec6f37e7e13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519003144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.519003144
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1568659648
Short name T834
Test name
Test status
Simulation time 1237724698 ps
CPU time 1.46 seconds
Started Jul 03 05:06:44 PM PDT 24
Finished Jul 03 05:06:45 PM PDT 24
Peak memory 201472 kb
Host smart-5678186b-a4c2-4041-ae21-c1c9fdca596c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568659648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1568659648
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1726821626
Short name T814
Test name
Test status
Simulation time 608425580 ps
CPU time 2.3 seconds
Started Jul 03 05:06:48 PM PDT 24
Finished Jul 03 05:06:50 PM PDT 24
Peak memory 201536 kb
Host smart-fd6bed73-e2ac-4e19-a1b4-ff25258ac4e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726821626 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1726821626
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2082035265
Short name T898
Test name
Test status
Simulation time 426108330 ps
CPU time 1.62 seconds
Started Jul 03 05:06:44 PM PDT 24
Finished Jul 03 05:06:46 PM PDT 24
Peak memory 201452 kb
Host smart-9952216a-e036-464a-8bf7-f70ba4e7069b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082035265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2082035265
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1896647505
Short name T863
Test name
Test status
Simulation time 408701862 ps
CPU time 0.7 seconds
Started Jul 03 05:06:49 PM PDT 24
Finished Jul 03 05:06:50 PM PDT 24
Peak memory 201392 kb
Host smart-906b5ec1-ca4a-475b-bfb9-7b516c5ad23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896647505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1896647505
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.370963582
Short name T890
Test name
Test status
Simulation time 2094641307 ps
CPU time 4.91 seconds
Started Jul 03 05:06:47 PM PDT 24
Finished Jul 03 05:06:52 PM PDT 24
Peak memory 201512 kb
Host smart-bd57a943-fef3-4203-9602-c7620e068a56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370963582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.370963582
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1284750072
Short name T855
Test name
Test status
Simulation time 561469127 ps
CPU time 1.32 seconds
Started Jul 03 05:06:45 PM PDT 24
Finished Jul 03 05:06:47 PM PDT 24
Peak memory 201560 kb
Host smart-4259d0aa-6bc8-4154-b321-fda34f598f18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284750072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1284750072
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1259644578
Short name T900
Test name
Test status
Simulation time 8390534172 ps
CPU time 18.12 seconds
Started Jul 03 05:06:43 PM PDT 24
Finished Jul 03 05:07:02 PM PDT 24
Peak memory 201864 kb
Host smart-b96f2c43-fc85-4c70-b464-3c7595be6cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259644578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1259644578
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3325582162
Short name T825
Test name
Test status
Simulation time 371164299 ps
CPU time 0.86 seconds
Started Jul 03 05:07:39 PM PDT 24
Finished Jul 03 05:07:41 PM PDT 24
Peak memory 201380 kb
Host smart-0684af8d-95f5-480f-b0a0-7ae6c2e8a646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325582162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3325582162
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.85161298
Short name T889
Test name
Test status
Simulation time 361208901 ps
CPU time 0.84 seconds
Started Jul 03 05:07:38 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 201428 kb
Host smart-55d48f96-2bb7-4f6a-9124-86c963466f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85161298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.85161298
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3580330053
Short name T819
Test name
Test status
Simulation time 431860554 ps
CPU time 1.18 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 201428 kb
Host smart-da216675-97e4-41de-9c4e-60e0aa816d60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580330053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3580330053
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2412745717
Short name T907
Test name
Test status
Simulation time 476588944 ps
CPU time 0.96 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:38 PM PDT 24
Peak memory 201308 kb
Host smart-f0b1a7d4-9a11-4fc2-900e-8fd5cda7e257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412745717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2412745717
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2256496343
Short name T861
Test name
Test status
Simulation time 533909231 ps
CPU time 1.83 seconds
Started Jul 03 05:07:38 PM PDT 24
Finished Jul 03 05:07:40 PM PDT 24
Peak memory 201372 kb
Host smart-84c56261-714e-4339-bce9-da22ab3af057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256496343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2256496343
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.602271268
Short name T912
Test name
Test status
Simulation time 414046220 ps
CPU time 1.54 seconds
Started Jul 03 05:07:39 PM PDT 24
Finished Jul 03 05:07:41 PM PDT 24
Peak memory 201432 kb
Host smart-f9f2af22-0f0f-424c-9e2b-b974f7e69a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602271268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.602271268
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.749439987
Short name T813
Test name
Test status
Simulation time 541462062 ps
CPU time 0.75 seconds
Started Jul 03 05:07:39 PM PDT 24
Finished Jul 03 05:07:40 PM PDT 24
Peak memory 201428 kb
Host smart-6caef462-80fa-4e3e-a8be-239c856bac8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749439987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.749439987
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2734457375
Short name T820
Test name
Test status
Simulation time 498401628 ps
CPU time 0.93 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 201428 kb
Host smart-c7959a54-ee91-4ac3-9abf-01fe7adeeda9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734457375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2734457375
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1131981338
Short name T865
Test name
Test status
Simulation time 396868102 ps
CPU time 1.56 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 201444 kb
Host smart-19342ae9-2e5d-426f-982f-0a6afaedd2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131981338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1131981338
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2445107811
Short name T896
Test name
Test status
Simulation time 500207200 ps
CPU time 1.76 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 201380 kb
Host smart-6bee11b0-c7cb-4f17-aa73-d18eff6dba46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445107811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2445107811
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.855975169
Short name T856
Test name
Test status
Simulation time 597489961 ps
CPU time 1.32 seconds
Started Jul 03 05:06:51 PM PDT 24
Finished Jul 03 05:06:53 PM PDT 24
Peak memory 201584 kb
Host smart-c6e8ca27-779b-4f58-84a8-fa9a83eaa98e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855975169 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.855975169
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2396818578
Short name T132
Test name
Test status
Simulation time 561647609 ps
CPU time 2.15 seconds
Started Jul 03 05:06:57 PM PDT 24
Finished Jul 03 05:06:59 PM PDT 24
Peak memory 201504 kb
Host smart-9edd86ca-a3a5-4916-806d-b0a37b3c7e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396818578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2396818578
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1361950093
Short name T892
Test name
Test status
Simulation time 436015682 ps
CPU time 0.92 seconds
Started Jul 03 05:06:53 PM PDT 24
Finished Jul 03 05:06:54 PM PDT 24
Peak memory 201424 kb
Host smart-ab77c287-50c8-472a-bd5c-8335745fdfde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361950093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1361950093
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2779215596
Short name T61
Test name
Test status
Simulation time 2860299556 ps
CPU time 9.44 seconds
Started Jul 03 05:06:57 PM PDT 24
Finished Jul 03 05:07:06 PM PDT 24
Peak memory 201620 kb
Host smart-7d8ed4f8-2d94-4c77-90a0-fdad3adc215c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779215596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2779215596
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3558240449
Short name T878
Test name
Test status
Simulation time 1003747115 ps
CPU time 2.67 seconds
Started Jul 03 05:06:57 PM PDT 24
Finished Jul 03 05:07:00 PM PDT 24
Peak memory 211000 kb
Host smart-5cc4b5aa-7018-42d0-80d1-8b82567bc158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558240449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3558240449
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3823255121
Short name T64
Test name
Test status
Simulation time 9344771086 ps
CPU time 6.01 seconds
Started Jul 03 05:06:53 PM PDT 24
Finished Jul 03 05:06:59 PM PDT 24
Peak memory 201848 kb
Host smart-e3a711b3-dd4a-4d31-b402-7bb3edf5510f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823255121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3823255121
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3859207852
Short name T78
Test name
Test status
Simulation time 600806710 ps
CPU time 1.41 seconds
Started Jul 03 05:06:56 PM PDT 24
Finished Jul 03 05:06:58 PM PDT 24
Peak memory 201580 kb
Host smart-4d97f3fb-f2e4-43f9-80fd-949b2a3f277d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859207852 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3859207852
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.705173742
Short name T124
Test name
Test status
Simulation time 455817209 ps
CPU time 1.9 seconds
Started Jul 03 05:07:00 PM PDT 24
Finished Jul 03 05:07:02 PM PDT 24
Peak memory 201380 kb
Host smart-63dec2ad-f73b-4843-9885-5fe7dcb83fca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705173742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.705173742
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1292933413
Short name T858
Test name
Test status
Simulation time 500736431 ps
CPU time 0.92 seconds
Started Jul 03 05:07:02 PM PDT 24
Finished Jul 03 05:07:03 PM PDT 24
Peak memory 201404 kb
Host smart-750579de-c3c5-4863-bdea-5854142500b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292933413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1292933413
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2897244117
Short name T875
Test name
Test status
Simulation time 2176014156 ps
CPU time 5.57 seconds
Started Jul 03 05:06:59 PM PDT 24
Finished Jul 03 05:07:05 PM PDT 24
Peak memory 201496 kb
Host smart-cd2ce813-33ee-4215-8563-9d15fe7cd212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897244117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2897244117
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.422751924
Short name T835
Test name
Test status
Simulation time 670117376 ps
CPU time 2.56 seconds
Started Jul 03 05:06:57 PM PDT 24
Finished Jul 03 05:07:00 PM PDT 24
Peak memory 210932 kb
Host smart-bf710195-2228-4f9e-8f84-799fb4349820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422751924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.422751924
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.562377884
Short name T83
Test name
Test status
Simulation time 4682852845 ps
CPU time 3.63 seconds
Started Jul 03 05:06:58 PM PDT 24
Finished Jul 03 05:07:02 PM PDT 24
Peak memory 201832 kb
Host smart-eb96def1-dbc0-41bb-8c20-88bb2a82ebb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562377884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.562377884
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.26798195
Short name T93
Test name
Test status
Simulation time 635306206 ps
CPU time 1.42 seconds
Started Jul 03 05:07:02 PM PDT 24
Finished Jul 03 05:07:04 PM PDT 24
Peak memory 201552 kb
Host smart-4e4a58d3-9f50-43a3-afbc-f5cb87e9d7f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798195 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.26798195
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2869526529
Short name T903
Test name
Test status
Simulation time 541745835 ps
CPU time 1.17 seconds
Started Jul 03 05:07:01 PM PDT 24
Finished Jul 03 05:07:03 PM PDT 24
Peak memory 201476 kb
Host smart-57e30193-d007-49e6-bdc4-d0b36dfdb6dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869526529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2869526529
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4011132756
Short name T817
Test name
Test status
Simulation time 559923025 ps
CPU time 0.97 seconds
Started Jul 03 05:07:02 PM PDT 24
Finished Jul 03 05:07:03 PM PDT 24
Peak memory 201404 kb
Host smart-b5a3fda6-b53a-451a-8bdb-43852c93a315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011132756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4011132756
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3088847014
Short name T908
Test name
Test status
Simulation time 2142573436 ps
CPU time 2.77 seconds
Started Jul 03 05:06:57 PM PDT 24
Finished Jul 03 05:07:00 PM PDT 24
Peak memory 201448 kb
Host smart-ca08be86-43ab-483c-b022-3784c308470f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088847014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3088847014
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4057192910
Short name T859
Test name
Test status
Simulation time 804150113 ps
CPU time 1.84 seconds
Started Jul 03 05:06:58 PM PDT 24
Finished Jul 03 05:07:00 PM PDT 24
Peak memory 201792 kb
Host smart-b037afe5-cfa5-4a60-b3fe-e75fc4404394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057192910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4057192910
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.701104834
Short name T887
Test name
Test status
Simulation time 9575227962 ps
CPU time 4.95 seconds
Started Jul 03 05:06:59 PM PDT 24
Finished Jul 03 05:07:04 PM PDT 24
Peak memory 201708 kb
Host smart-0c5fbaeb-7fc8-4bce-9bda-2d8256638df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701104834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.701104834
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3888142735
Short name T869
Test name
Test status
Simulation time 407248573 ps
CPU time 1.19 seconds
Started Jul 03 05:07:00 PM PDT 24
Finished Jul 03 05:07:02 PM PDT 24
Peak memory 201612 kb
Host smart-d34d8824-cfeb-4385-b5b5-bf2484635c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888142735 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3888142735
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3554083140
Short name T874
Test name
Test status
Simulation time 526568055 ps
CPU time 2.04 seconds
Started Jul 03 05:07:02 PM PDT 24
Finished Jul 03 05:07:05 PM PDT 24
Peak memory 201480 kb
Host smart-2be854c7-c6b2-4710-a66e-0b0a85b54363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554083140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3554083140
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2370536462
Short name T803
Test name
Test status
Simulation time 368422426 ps
CPU time 1.01 seconds
Started Jul 03 05:06:57 PM PDT 24
Finished Jul 03 05:06:58 PM PDT 24
Peak memory 201440 kb
Host smart-858e25f7-1736-44c8-92aa-4342077483a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370536462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2370536462
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2514483878
Short name T136
Test name
Test status
Simulation time 1911690451 ps
CPU time 4.75 seconds
Started Jul 03 05:07:02 PM PDT 24
Finished Jul 03 05:07:07 PM PDT 24
Peak memory 201516 kb
Host smart-acc3e7b9-a5d8-4e38-8fcb-a373470d3807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514483878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2514483878
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3678708066
Short name T82
Test name
Test status
Simulation time 7947420990 ps
CPU time 18.7 seconds
Started Jul 03 05:07:02 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 201788 kb
Host smart-0b33752a-56eb-444f-9f1e-73f50a5c73ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678708066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3678708066
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4004513711
Short name T80
Test name
Test status
Simulation time 349627117 ps
CPU time 1.57 seconds
Started Jul 03 05:07:08 PM PDT 24
Finished Jul 03 05:07:10 PM PDT 24
Peak memory 201556 kb
Host smart-0eceb2c5-3db8-4c36-8b44-c6d529ab5f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004513711 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4004513711
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1085058807
Short name T133
Test name
Test status
Simulation time 426382990 ps
CPU time 1.84 seconds
Started Jul 03 05:07:08 PM PDT 24
Finished Jul 03 05:07:10 PM PDT 24
Peak memory 201476 kb
Host smart-1be3a743-6a85-4587-9d9a-36162b86e833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085058807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1085058807
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2086793633
Short name T829
Test name
Test status
Simulation time 454273540 ps
CPU time 0.84 seconds
Started Jul 03 05:07:01 PM PDT 24
Finished Jul 03 05:07:02 PM PDT 24
Peak memory 201400 kb
Host smart-9009d368-4f57-4918-a00c-f94d814b832a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086793633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2086793633
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.564067447
Short name T24
Test name
Test status
Simulation time 4239050991 ps
CPU time 12.81 seconds
Started Jul 03 05:07:07 PM PDT 24
Finished Jul 03 05:07:21 PM PDT 24
Peak memory 201816 kb
Host smart-091d7514-acae-4d1a-bfc0-82286511765f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564067447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.564067447
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.886050590
Short name T840
Test name
Test status
Simulation time 551150945 ps
CPU time 2.16 seconds
Started Jul 03 05:07:04 PM PDT 24
Finished Jul 03 05:07:07 PM PDT 24
Peak memory 201788 kb
Host smart-f97968c6-66f3-4d03-822a-11f2df0fd81e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886050590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.886050590
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2039090624
Short name T63
Test name
Test status
Simulation time 8055605588 ps
CPU time 21.22 seconds
Started Jul 03 05:07:04 PM PDT 24
Finished Jul 03 05:07:26 PM PDT 24
Peak memory 201800 kb
Host smart-3a39eef2-b1f4-4a1a-bc48-a3dfae754c7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039090624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2039090624
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.354120955
Short name T689
Test name
Test status
Simulation time 446857772 ps
CPU time 0.93 seconds
Started Jul 03 06:50:33 PM PDT 24
Finished Jul 03 06:50:34 PM PDT 24
Peak memory 201668 kb
Host smart-7b7aa6c8-c9cc-45d0-b1ac-6d415b6640f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354120955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.354120955
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2254822619
Short name T703
Test name
Test status
Simulation time 290363371302 ps
CPU time 4.65 seconds
Started Jul 03 06:50:20 PM PDT 24
Finished Jul 03 06:50:26 PM PDT 24
Peak memory 201916 kb
Host smart-c079e695-754d-4bf6-b789-b610242c1fa6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254822619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2254822619
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2114483763
Short name T539
Test name
Test status
Simulation time 257486521092 ps
CPU time 310.17 seconds
Started Jul 03 06:50:18 PM PDT 24
Finished Jul 03 06:55:30 PM PDT 24
Peak memory 201916 kb
Host smart-2d865741-6ce7-4afc-bf52-a6160ec6e2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114483763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2114483763
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3979559902
Short name T190
Test name
Test status
Simulation time 162058921393 ps
CPU time 385.05 seconds
Started Jul 03 06:50:08 PM PDT 24
Finished Jul 03 06:56:34 PM PDT 24
Peak memory 201904 kb
Host smart-cb9b206f-d01a-47f9-b716-911711f63269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979559902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3979559902
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1706484901
Short name T418
Test name
Test status
Simulation time 163166528670 ps
CPU time 109.74 seconds
Started Jul 03 06:50:14 PM PDT 24
Finished Jul 03 06:52:05 PM PDT 24
Peak memory 201904 kb
Host smart-38992d4e-f269-4ee9-bb81-d46419d4f24c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706484901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1706484901
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.120413813
Short name T278
Test name
Test status
Simulation time 164383307446 ps
CPU time 365.25 seconds
Started Jul 03 06:50:03 PM PDT 24
Finished Jul 03 06:56:09 PM PDT 24
Peak memory 201900 kb
Host smart-368cbabc-e1c5-4aff-addc-a7449103cd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120413813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.120413813
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.98413678
Short name T349
Test name
Test status
Simulation time 487201055940 ps
CPU time 1022.87 seconds
Started Jul 03 06:50:08 PM PDT 24
Finished Jul 03 07:07:12 PM PDT 24
Peak memory 201740 kb
Host smart-1e4c91a3-1d64-43b4-b270-830172ce931d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=98413678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed.98413678
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1412143915
Short name T511
Test name
Test status
Simulation time 456083667302 ps
CPU time 166.42 seconds
Started Jul 03 06:50:15 PM PDT 24
Finished Jul 03 06:53:03 PM PDT 24
Peak memory 201932 kb
Host smart-9dc473bf-c4a0-4111-b70d-71761334faa2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412143915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1412143915
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3117459090
Short name T486
Test name
Test status
Simulation time 197180532538 ps
CPU time 460.54 seconds
Started Jul 03 06:50:14 PM PDT 24
Finished Jul 03 06:57:56 PM PDT 24
Peak memory 201936 kb
Host smart-b44060c5-73ac-4a6f-845d-d57b191aa0ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117459090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3117459090
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3255696037
Short name T503
Test name
Test status
Simulation time 47463738300 ps
CPU time 105.83 seconds
Started Jul 03 06:50:21 PM PDT 24
Finished Jul 03 06:52:08 PM PDT 24
Peak memory 201728 kb
Host smart-fc34e9e9-e8be-4a9a-8464-6888c2f12ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255696037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3255696037
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1363846963
Short name T387
Test name
Test status
Simulation time 3611003215 ps
CPU time 5.29 seconds
Started Jul 03 06:50:17 PM PDT 24
Finished Jul 03 06:50:25 PM PDT 24
Peak memory 201624 kb
Host smart-80a68171-e482-4c12-b4c8-b29bf64abd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363846963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1363846963
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3044454099
Short name T84
Test name
Test status
Simulation time 4704305211 ps
CPU time 11.28 seconds
Started Jul 03 06:50:28 PM PDT 24
Finished Jul 03 06:50:40 PM PDT 24
Peak memory 217168 kb
Host smart-9fc441cc-b276-4eec-a9f2-1c8ef7b5a0ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044454099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3044454099
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2141156853
Short name T656
Test name
Test status
Simulation time 5880570967 ps
CPU time 7.97 seconds
Started Jul 03 06:50:03 PM PDT 24
Finished Jul 03 06:50:11 PM PDT 24
Peak memory 201740 kb
Host smart-967662d7-6f7c-4648-aca9-947e944e9221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141156853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2141156853
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3817603043
Short name T325
Test name
Test status
Simulation time 541119522490 ps
CPU time 442.61 seconds
Started Jul 03 06:50:28 PM PDT 24
Finished Jul 03 06:57:52 PM PDT 24
Peak memory 201940 kb
Host smart-089f7941-c24c-44d7-9add-57c9ed3d4004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817603043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3817603043
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2830356995
Short name T567
Test name
Test status
Simulation time 64294400054 ps
CPU time 215.56 seconds
Started Jul 03 06:50:29 PM PDT 24
Finished Jul 03 06:54:05 PM PDT 24
Peak memory 210508 kb
Host smart-c59fdedc-65dd-4737-a8be-c0df1f92c0e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830356995 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2830356995
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1248184755
Short name T661
Test name
Test status
Simulation time 353218137 ps
CPU time 1.14 seconds
Started Jul 03 06:50:46 PM PDT 24
Finished Jul 03 06:50:48 PM PDT 24
Peak memory 201684 kb
Host smart-c9cc9efe-6a3c-439f-a7a9-b39d59f57059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248184755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1248184755
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1237390116
Short name T309
Test name
Test status
Simulation time 484693550787 ps
CPU time 340.46 seconds
Started Jul 03 06:50:39 PM PDT 24
Finished Jul 03 06:56:20 PM PDT 24
Peak memory 201896 kb
Host smart-ce05394a-7bde-43a5-8f2e-d464a3249155
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237390116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1237390116
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1587144596
Short name T762
Test name
Test status
Simulation time 204413293683 ps
CPU time 107.3 seconds
Started Jul 03 06:50:42 PM PDT 24
Finished Jul 03 06:52:29 PM PDT 24
Peak memory 201844 kb
Host smart-ef9265b0-2802-4a74-abd3-98c9ddeb66a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587144596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1587144596
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.635962276
Short name T750
Test name
Test status
Simulation time 503553793766 ps
CPU time 1194.15 seconds
Started Jul 03 06:50:42 PM PDT 24
Finished Jul 03 07:10:37 PM PDT 24
Peak memory 201900 kb
Host smart-9ca73d77-6046-4722-832f-f9bcc6a56259
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=635962276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.635962276
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1929027928
Short name T432
Test name
Test status
Simulation time 166737969433 ps
CPU time 35.76 seconds
Started Jul 03 06:50:32 PM PDT 24
Finished Jul 03 06:51:09 PM PDT 24
Peak memory 201932 kb
Host smart-20197ffd-3410-4bd6-9e0f-9fda1d97b3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929027928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1929027928
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2944904918
Short name T726
Test name
Test status
Simulation time 169258039618 ps
CPU time 384.66 seconds
Started Jul 03 06:50:37 PM PDT 24
Finished Jul 03 06:57:02 PM PDT 24
Peak memory 201928 kb
Host smart-738933e8-ebe9-4522-acf4-98e4d1807c67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944904918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2944904918
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3946249623
Short name T514
Test name
Test status
Simulation time 403023512571 ps
CPU time 872.57 seconds
Started Jul 03 06:50:42 PM PDT 24
Finished Jul 03 07:05:15 PM PDT 24
Peak memory 201896 kb
Host smart-6fe416fd-9a07-43f1-92ac-a4c2114f44fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946249623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3946249623
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3246941818
Short name T779
Test name
Test status
Simulation time 116919989033 ps
CPU time 440.73 seconds
Started Jul 03 06:50:49 PM PDT 24
Finished Jul 03 06:58:10 PM PDT 24
Peak memory 202208 kb
Host smart-8b703aa2-6bf7-4d71-98df-2f8d4bf796f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246941818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3246941818
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1911094075
Short name T398
Test name
Test status
Simulation time 24959734542 ps
CPU time 56.76 seconds
Started Jul 03 06:50:47 PM PDT 24
Finished Jul 03 06:51:45 PM PDT 24
Peak memory 201716 kb
Host smart-d0389afa-d0b2-4f69-a264-2df12e80dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911094075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1911094075
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3183828627
Short name T6
Test name
Test status
Simulation time 3160375376 ps
CPU time 1.73 seconds
Started Jul 03 06:50:43 PM PDT 24
Finished Jul 03 06:50:46 PM PDT 24
Peak memory 201740 kb
Host smart-14dc267e-ef1e-4a8c-874b-5a14cef41c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183828627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3183828627
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2750515088
Short name T755
Test name
Test status
Simulation time 5798892759 ps
CPU time 13.33 seconds
Started Jul 03 06:50:32 PM PDT 24
Finished Jul 03 06:50:46 PM PDT 24
Peak memory 201708 kb
Host smart-2e1cadb5-b8f1-419a-a89f-0dbafa8061ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750515088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2750515088
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.656343559
Short name T391
Test name
Test status
Simulation time 6657021974 ps
CPU time 4.53 seconds
Started Jul 03 06:50:47 PM PDT 24
Finished Jul 03 06:50:53 PM PDT 24
Peak memory 201708 kb
Host smart-ba49ca0e-d5b4-4b72-8eac-a4a8ac349958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656343559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.656343559
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.700967468
Short name T19
Test name
Test status
Simulation time 139588450679 ps
CPU time 136.14 seconds
Started Jul 03 06:50:47 PM PDT 24
Finished Jul 03 06:53:04 PM PDT 24
Peak memory 210556 kb
Host smart-ba2b9220-bff8-428f-8007-d25ef05a8449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700967468 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.700967468
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.78350924
Short name T786
Test name
Test status
Simulation time 294734880 ps
CPU time 0.97 seconds
Started Jul 03 06:54:54 PM PDT 24
Finished Jul 03 06:54:56 PM PDT 24
Peak memory 201636 kb
Host smart-993f4d67-055a-431b-88b3-0f4108eac615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78350924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.78350924
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3829331086
Short name T276
Test name
Test status
Simulation time 166051552677 ps
CPU time 367.82 seconds
Started Jul 03 06:54:44 PM PDT 24
Finished Jul 03 07:00:52 PM PDT 24
Peak memory 201884 kb
Host smart-8bd79bb7-795b-44c3-a625-d415af11b493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829331086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3829331086
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4175519550
Short name T442
Test name
Test status
Simulation time 493044463375 ps
CPU time 321.1 seconds
Started Jul 03 06:54:40 PM PDT 24
Finished Jul 03 07:00:02 PM PDT 24
Peak memory 201976 kb
Host smart-8d4b5b88-07b4-4c8a-9685-093f3152430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175519550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4175519550
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2536676976
Short name T100
Test name
Test status
Simulation time 331510415099 ps
CPU time 382.01 seconds
Started Jul 03 06:54:40 PM PDT 24
Finished Jul 03 07:01:03 PM PDT 24
Peak memory 201932 kb
Host smart-5f9a6828-2e06-4661-b3c1-abf71e63f5ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536676976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2536676976
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3053389008
Short name T144
Test name
Test status
Simulation time 325401617945 ps
CPU time 173.54 seconds
Started Jul 03 06:54:35 PM PDT 24
Finished Jul 03 06:57:29 PM PDT 24
Peak memory 201924 kb
Host smart-ecbd50ab-fc3a-4178-a95c-59cf580d1493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053389008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3053389008
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.796449582
Short name T197
Test name
Test status
Simulation time 332577552323 ps
CPU time 54.1 seconds
Started Jul 03 06:54:36 PM PDT 24
Finished Jul 03 06:55:30 PM PDT 24
Peak memory 201904 kb
Host smart-3a9b68f7-58ba-415d-ab8e-42e0ea5c9e4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=796449582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.796449582
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3045586187
Short name T485
Test name
Test status
Simulation time 388478511869 ps
CPU time 898.48 seconds
Started Jul 03 06:54:40 PM PDT 24
Finished Jul 03 07:09:39 PM PDT 24
Peak memory 201888 kb
Host smart-97b7be35-2011-4c7a-8c1b-a07dd00aea44
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045586187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3045586187
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.459990261
Short name T495
Test name
Test status
Simulation time 45460615828 ps
CPU time 92.14 seconds
Started Jul 03 06:54:50 PM PDT 24
Finished Jul 03 06:56:23 PM PDT 24
Peak memory 201728 kb
Host smart-fdd5ffa5-668d-425a-95c2-5e2b5c81942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459990261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.459990261
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.792635969
Short name T351
Test name
Test status
Simulation time 3580057535 ps
CPU time 4.85 seconds
Started Jul 03 06:54:50 PM PDT 24
Finished Jul 03 06:54:55 PM PDT 24
Peak memory 201732 kb
Host smart-3a081b93-43f1-4bd9-a753-870e18f72482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792635969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.792635969
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3177133801
Short name T392
Test name
Test status
Simulation time 5551182001 ps
CPU time 13.08 seconds
Started Jul 03 06:54:31 PM PDT 24
Finished Jul 03 06:54:44 PM PDT 24
Peak memory 201744 kb
Host smart-b1a464d1-4cba-4b07-a80d-4b793473787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177133801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3177133801
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3541802887
Short name T225
Test name
Test status
Simulation time 323746668544 ps
CPU time 758.47 seconds
Started Jul 03 06:54:54 PM PDT 24
Finished Jul 03 07:07:34 PM PDT 24
Peak memory 201832 kb
Host smart-df1e0538-6150-44f9-922b-51956968b751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541802887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3541802887
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1185787786
Short name T782
Test name
Test status
Simulation time 327034118834 ps
CPU time 207.7 seconds
Started Jul 03 06:55:08 PM PDT 24
Finished Jul 03 06:58:36 PM PDT 24
Peak memory 201916 kb
Host smart-6c306b8a-7640-4aea-b8a7-80d2266210e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185787786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1185787786
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.752981313
Short name T168
Test name
Test status
Simulation time 171723378754 ps
CPU time 42.24 seconds
Started Jul 03 06:55:12 PM PDT 24
Finished Jul 03 06:55:55 PM PDT 24
Peak memory 201936 kb
Host smart-b6658563-1e99-47af-872c-8c5d9ee41110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752981313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.752981313
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2197997585
Short name T163
Test name
Test status
Simulation time 163740684954 ps
CPU time 256.13 seconds
Started Jul 03 06:55:02 PM PDT 24
Finished Jul 03 06:59:19 PM PDT 24
Peak memory 201928 kb
Host smart-28725471-08f6-416a-8696-4f5fd8d0d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197997585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2197997585
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2479443789
Short name T591
Test name
Test status
Simulation time 163711336322 ps
CPU time 384.95 seconds
Started Jul 03 06:55:03 PM PDT 24
Finished Jul 03 07:01:28 PM PDT 24
Peak memory 201908 kb
Host smart-9325e9b2-ff2c-45d2-bea9-cdedcdf1371c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479443789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2479443789
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1365561415
Short name T146
Test name
Test status
Simulation time 321160950509 ps
CPU time 701.58 seconds
Started Jul 03 06:54:57 PM PDT 24
Finished Jul 03 07:06:39 PM PDT 24
Peak memory 201892 kb
Host smart-1b4fdf81-0413-4bf5-af5f-ffc96a40d44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365561415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1365561415
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3499913350
Short name T493
Test name
Test status
Simulation time 487381805447 ps
CPU time 561.18 seconds
Started Jul 03 06:54:56 PM PDT 24
Finished Jul 03 07:04:19 PM PDT 24
Peak memory 201924 kb
Host smart-2972338c-c902-41fb-a7a4-6541a1b30ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499913350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3499913350
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2429641839
Short name T462
Test name
Test status
Simulation time 601642809786 ps
CPU time 1431.82 seconds
Started Jul 03 06:55:08 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 201876 kb
Host smart-87890148-0e53-4a06-a581-1882fbd3a244
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429641839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2429641839
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.88936737
Short name T670
Test name
Test status
Simulation time 103991354053 ps
CPU time 527.41 seconds
Started Jul 03 06:55:18 PM PDT 24
Finished Jul 03 07:04:06 PM PDT 24
Peak memory 202280 kb
Host smart-0ab01e26-faf4-42a0-bbf0-b5c001b9aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88936737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.88936737
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.751731369
Short name T525
Test name
Test status
Simulation time 32884428819 ps
CPU time 68.92 seconds
Started Jul 03 06:55:16 PM PDT 24
Finished Jul 03 06:56:26 PM PDT 24
Peak memory 201676 kb
Host smart-74f555c4-011f-425c-b9d1-ebd63f6dde15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751731369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.751731369
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1102269345
Short name T554
Test name
Test status
Simulation time 5384534409 ps
CPU time 4.05 seconds
Started Jul 03 06:55:12 PM PDT 24
Finished Jul 03 06:55:17 PM PDT 24
Peak memory 201712 kb
Host smart-a351f57d-b8fc-4b92-bf16-c4def51e6c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102269345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1102269345
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3442453525
Short name T466
Test name
Test status
Simulation time 5673382523 ps
CPU time 14.07 seconds
Started Jul 03 06:54:58 PM PDT 24
Finished Jul 03 06:55:13 PM PDT 24
Peak memory 201688 kb
Host smart-ce61ce0b-cb37-4483-8554-5e1c5473d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442453525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3442453525
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3895248452
Short name T652
Test name
Test status
Simulation time 157270770534 ps
CPU time 91.15 seconds
Started Jul 03 06:55:17 PM PDT 24
Finished Jul 03 06:56:49 PM PDT 24
Peak memory 202076 kb
Host smart-d2984396-7a0c-4d3e-8141-dfe90affcdaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895248452 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3895248452
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1231329136
Short name T743
Test name
Test status
Simulation time 420864190 ps
CPU time 1.65 seconds
Started Jul 03 06:55:35 PM PDT 24
Finished Jul 03 06:55:37 PM PDT 24
Peak memory 201652 kb
Host smart-4af6dfaf-81ea-4359-a737-e56461229073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231329136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1231329136
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.589308707
Short name T775
Test name
Test status
Simulation time 323313548753 ps
CPU time 160.45 seconds
Started Jul 03 06:55:35 PM PDT 24
Finished Jul 03 06:58:16 PM PDT 24
Peak memory 201924 kb
Host smart-d84c26b3-cb37-4a1e-8c89-a6577661ead0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589308707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.589308707
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2688009977
Short name T142
Test name
Test status
Simulation time 164531950323 ps
CPU time 148.05 seconds
Started Jul 03 06:55:28 PM PDT 24
Finished Jul 03 06:57:57 PM PDT 24
Peak memory 201908 kb
Host smart-e450fafb-e143-4283-a31f-b26c0bc75016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688009977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2688009977
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.346048865
Short name T395
Test name
Test status
Simulation time 162028049847 ps
CPU time 98.59 seconds
Started Jul 03 06:55:28 PM PDT 24
Finished Jul 03 06:57:07 PM PDT 24
Peak memory 201968 kb
Host smart-da1535a9-bde7-464c-b10d-abc859883e9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=346048865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.346048865
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2281326153
Short name T500
Test name
Test status
Simulation time 96043755613 ps
CPU time 356.2 seconds
Started Jul 03 06:55:34 PM PDT 24
Finished Jul 03 07:01:31 PM PDT 24
Peak memory 202204 kb
Host smart-974bd63b-6f41-4b36-b6df-70f1383828c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281326153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2281326153
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.876063916
Short name T359
Test name
Test status
Simulation time 32613366621 ps
CPU time 19.49 seconds
Started Jul 03 06:55:39 PM PDT 24
Finished Jul 03 06:55:59 PM PDT 24
Peak memory 201712 kb
Host smart-72ad568c-3dea-4166-a63a-ac9bb02553c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876063916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.876063916
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.21315481
Short name T571
Test name
Test status
Simulation time 5342653385 ps
CPU time 12.13 seconds
Started Jul 03 06:55:31 PM PDT 24
Finished Jul 03 06:55:43 PM PDT 24
Peak memory 201684 kb
Host smart-8938705b-a9dd-4f55-8c92-9861aa500aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21315481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.21315481
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.385712306
Short name T87
Test name
Test status
Simulation time 5649730442 ps
CPU time 6.69 seconds
Started Jul 03 06:55:29 PM PDT 24
Finished Jul 03 06:55:36 PM PDT 24
Peak memory 201724 kb
Host smart-40131be2-6835-4e3f-a9d1-29d99b1bf6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385712306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.385712306
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2411205445
Short name T196
Test name
Test status
Simulation time 333712897517 ps
CPU time 703 seconds
Started Jul 03 06:55:35 PM PDT 24
Finished Jul 03 07:07:19 PM PDT 24
Peak memory 201916 kb
Host smart-2634189a-4748-401e-8a54-8596b9efac36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411205445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2411205445
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3001798357
Short name T718
Test name
Test status
Simulation time 150344626832 ps
CPU time 246.82 seconds
Started Jul 03 06:55:34 PM PDT 24
Finished Jul 03 06:59:42 PM PDT 24
Peak memory 210580 kb
Host smart-c94e42e5-48c7-46f4-b744-8d48ccb7b7c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001798357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3001798357
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2340222152
Short name T662
Test name
Test status
Simulation time 466261462 ps
CPU time 0.78 seconds
Started Jul 03 06:55:53 PM PDT 24
Finished Jul 03 06:55:54 PM PDT 24
Peak memory 201640 kb
Host smart-0ad540f3-f186-444e-a5b3-f483599a3c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340222152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2340222152
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.168916153
Short name T679
Test name
Test status
Simulation time 165229408013 ps
CPU time 59.16 seconds
Started Jul 03 06:55:54 PM PDT 24
Finished Jul 03 06:56:54 PM PDT 24
Peak memory 201924 kb
Host smart-f3b6b139-ca03-422e-b4b6-120ae74b2069
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168916153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.168916153
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1859382684
Short name T749
Test name
Test status
Simulation time 173459431290 ps
CPU time 428.44 seconds
Started Jul 03 06:55:54 PM PDT 24
Finished Jul 03 07:03:03 PM PDT 24
Peak memory 201924 kb
Host smart-f3f5f86e-8efd-455f-a75a-ac407a1501d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859382684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1859382684
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3737616253
Short name T321
Test name
Test status
Simulation time 161085366610 ps
CPU time 199.94 seconds
Started Jul 03 06:55:45 PM PDT 24
Finished Jul 03 06:59:06 PM PDT 24
Peak memory 201924 kb
Host smart-e61f95e7-d706-4e6c-a398-adec9dc7678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737616253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3737616253
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.821462393
Short name T632
Test name
Test status
Simulation time 164002690640 ps
CPU time 118.05 seconds
Started Jul 03 06:55:44 PM PDT 24
Finished Jul 03 06:57:43 PM PDT 24
Peak memory 201860 kb
Host smart-ab22ae77-65b7-4562-abb9-3f74d363280c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=821462393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.821462393
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2168979666
Short name T682
Test name
Test status
Simulation time 155995296040 ps
CPU time 118.56 seconds
Started Jul 03 06:55:35 PM PDT 24
Finished Jul 03 06:57:34 PM PDT 24
Peak memory 201968 kb
Host smart-7bbc9c6b-4888-49cf-b66d-0921c7546604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168979666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2168979666
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.248474442
Short name T109
Test name
Test status
Simulation time 486651835369 ps
CPU time 508.46 seconds
Started Jul 03 06:55:40 PM PDT 24
Finished Jul 03 07:04:09 PM PDT 24
Peak memory 201900 kb
Host smart-b0c224ae-ea95-46b6-a2dc-91589de6e4de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=248474442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.248474442
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1258436660
Short name T149
Test name
Test status
Simulation time 480656448401 ps
CPU time 268.99 seconds
Started Jul 03 06:55:45 PM PDT 24
Finished Jul 03 07:00:14 PM PDT 24
Peak memory 201880 kb
Host smart-63320ab7-3a72-458c-a897-504ec86c7b00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258436660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1258436660
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1195980342
Short name T475
Test name
Test status
Simulation time 392708135416 ps
CPU time 852.82 seconds
Started Jul 03 06:55:48 PM PDT 24
Finished Jul 03 07:10:02 PM PDT 24
Peak memory 201928 kb
Host smart-37a1d90f-1784-4a1b-b712-ecdb25a88356
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195980342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1195980342
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3925461202
Short name T516
Test name
Test status
Simulation time 104846073095 ps
CPU time 411.96 seconds
Started Jul 03 06:55:49 PM PDT 24
Finished Jul 03 07:02:42 PM PDT 24
Peak memory 202280 kb
Host smart-fe59a170-b9de-451b-a31a-ee73a2753924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925461202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3925461202
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3622055898
Short name T615
Test name
Test status
Simulation time 41974006474 ps
CPU time 25.69 seconds
Started Jul 03 06:55:54 PM PDT 24
Finished Jul 03 06:56:20 PM PDT 24
Peak memory 201736 kb
Host smart-3a119da7-1596-46e2-8e0b-952aae5f6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622055898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3622055898
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.916706957
Short name T723
Test name
Test status
Simulation time 5438064756 ps
CPU time 2.29 seconds
Started Jul 03 06:55:50 PM PDT 24
Finished Jul 03 06:55:53 PM PDT 24
Peak memory 201672 kb
Host smart-bec3c3cc-6432-4489-9f53-35594277c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916706957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.916706957
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.4255252263
Short name T592
Test name
Test status
Simulation time 5893719336 ps
CPU time 11.16 seconds
Started Jul 03 06:55:34 PM PDT 24
Finished Jul 03 06:55:46 PM PDT 24
Peak memory 201732 kb
Host smart-47090206-e7c9-4dbb-acf0-d168b88159d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255252263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.4255252263
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3991899278
Short name T736
Test name
Test status
Simulation time 80309579018 ps
CPU time 66.67 seconds
Started Jul 03 06:55:49 PM PDT 24
Finished Jul 03 06:56:56 PM PDT 24
Peak memory 210516 kb
Host smart-67a4416a-f291-4c4c-ba88-8cce5b386943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991899278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3991899278
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.406154962
Short name T386
Test name
Test status
Simulation time 352277207 ps
CPU time 0.78 seconds
Started Jul 03 06:56:17 PM PDT 24
Finished Jul 03 06:56:18 PM PDT 24
Peak memory 201668 kb
Host smart-ac216299-2cb1-4ffe-9f7d-b98b8375fc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406154962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.406154962
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.91556648
Short name T768
Test name
Test status
Simulation time 328081598203 ps
CPU time 738.61 seconds
Started Jul 03 06:56:02 PM PDT 24
Finished Jul 03 07:08:21 PM PDT 24
Peak memory 201964 kb
Host smart-79b3d219-6169-4f5f-b46c-5145d174662b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91556648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gatin
g.91556648
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.417940712
Short name T630
Test name
Test status
Simulation time 332180509310 ps
CPU time 766.88 seconds
Started Jul 03 06:56:03 PM PDT 24
Finished Jul 03 07:08:51 PM PDT 24
Peak memory 202000 kb
Host smart-6f575afa-05eb-4805-9dc0-632280f50e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417940712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.417940712
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4038869167
Short name T175
Test name
Test status
Simulation time 164352189337 ps
CPU time 385.31 seconds
Started Jul 03 06:55:58 PM PDT 24
Finished Jul 03 07:02:24 PM PDT 24
Peak memory 202000 kb
Host smart-7cdb99dd-ec7c-4794-9452-671a60a13d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038869167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4038869167
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2337856107
Short name T646
Test name
Test status
Simulation time 487993689596 ps
CPU time 97.26 seconds
Started Jul 03 06:55:59 PM PDT 24
Finished Jul 03 06:57:37 PM PDT 24
Peak memory 201908 kb
Host smart-df0596be-8933-4b16-906d-2be8cf506700
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337856107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2337856107
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2775971277
Short name T617
Test name
Test status
Simulation time 491121551409 ps
CPU time 550.96 seconds
Started Jul 03 06:56:01 PM PDT 24
Finished Jul 03 07:05:13 PM PDT 24
Peak memory 201992 kb
Host smart-88938048-38eb-461c-b2be-7fcb84f85db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775971277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2775971277
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2902915156
Short name T710
Test name
Test status
Simulation time 160641717846 ps
CPU time 92.93 seconds
Started Jul 03 06:56:01 PM PDT 24
Finished Jul 03 06:57:35 PM PDT 24
Peak memory 201920 kb
Host smart-68492515-466a-4302-8699-d899b4b70683
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902915156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2902915156
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3652302442
Short name T695
Test name
Test status
Simulation time 188978300475 ps
CPU time 200.42 seconds
Started Jul 03 06:56:04 PM PDT 24
Finished Jul 03 06:59:26 PM PDT 24
Peak memory 201952 kb
Host smart-cff76baa-dc35-4a06-8a30-9a6300b86199
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652302442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3652302442
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1599647917
Short name T563
Test name
Test status
Simulation time 197329577197 ps
CPU time 113.94 seconds
Started Jul 03 06:56:04 PM PDT 24
Finished Jul 03 06:57:59 PM PDT 24
Peak memory 201884 kb
Host smart-c15e74aa-e548-4ab3-8084-1b1efdf86e5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599647917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1599647917
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1878764481
Short name T57
Test name
Test status
Simulation time 121198490829 ps
CPU time 632.92 seconds
Started Jul 03 06:56:13 PM PDT 24
Finished Jul 03 07:06:46 PM PDT 24
Peak memory 202188 kb
Host smart-ca1528de-8d08-4b47-ae1a-fec78bbf99c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878764481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1878764481
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4029035176
Short name T559
Test name
Test status
Simulation time 30714491783 ps
CPU time 63.67 seconds
Started Jul 03 06:56:12 PM PDT 24
Finished Jul 03 06:57:16 PM PDT 24
Peak memory 201724 kb
Host smart-0f8b42de-323d-4708-9e5d-78aaab949597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029035176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4029035176
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.194904383
Short name T454
Test name
Test status
Simulation time 3595369849 ps
CPU time 2.66 seconds
Started Jul 03 06:56:14 PM PDT 24
Finished Jul 03 06:56:17 PM PDT 24
Peak memory 201704 kb
Host smart-425ec60c-a703-483b-ae28-f23ff726d594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194904383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.194904383
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3902777139
Short name T520
Test name
Test status
Simulation time 5844725644 ps
CPU time 3.87 seconds
Started Jul 03 06:55:57 PM PDT 24
Finished Jul 03 06:56:01 PM PDT 24
Peak memory 201728 kb
Host smart-2e58c2bc-345e-409a-8c2c-8ed7509398fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902777139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3902777139
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2004693367
Short name T227
Test name
Test status
Simulation time 606249573037 ps
CPU time 1779.96 seconds
Started Jul 03 06:56:18 PM PDT 24
Finished Jul 03 07:25:59 PM PDT 24
Peak memory 210444 kb
Host smart-0f37076c-7e7b-454e-9011-54347ba62957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004693367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2004693367
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.821228041
Short name T17
Test name
Test status
Simulation time 37191881540 ps
CPU time 49.54 seconds
Started Jul 03 06:56:14 PM PDT 24
Finished Jul 03 06:57:04 PM PDT 24
Peak memory 210564 kb
Host smart-f1f857e9-ae42-417b-8c15-baf2ba97737d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821228041 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.821228041
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.500636544
Short name T600
Test name
Test status
Simulation time 452771298 ps
CPU time 1.59 seconds
Started Jul 03 06:56:44 PM PDT 24
Finished Jul 03 06:56:46 PM PDT 24
Peak memory 201680 kb
Host smart-5b2040d0-b70a-47d0-b4bd-929824ca21ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500636544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.500636544
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.13466652
Short name T182
Test name
Test status
Simulation time 352952124416 ps
CPU time 140.92 seconds
Started Jul 03 06:56:32 PM PDT 24
Finished Jul 03 06:58:53 PM PDT 24
Peak memory 201912 kb
Host smart-74dc9069-fb97-42f0-a59e-5f4eef75b7d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13466652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gatin
g.13466652
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2429669417
Short name T712
Test name
Test status
Simulation time 179075240308 ps
CPU time 416.59 seconds
Started Jul 03 06:56:36 PM PDT 24
Finished Jul 03 07:03:33 PM PDT 24
Peak memory 201900 kb
Host smart-0416da4e-378d-4f73-a022-0aa74ecc459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429669417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2429669417
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2046658544
Short name T644
Test name
Test status
Simulation time 494891198893 ps
CPU time 273.14 seconds
Started Jul 03 06:56:30 PM PDT 24
Finished Jul 03 07:01:03 PM PDT 24
Peak memory 201872 kb
Host smart-bf8acdbd-efb2-4d88-9808-adf0e4323204
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046658544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2046658544
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3191885010
Short name T766
Test name
Test status
Simulation time 168409908218 ps
CPU time 347.85 seconds
Started Jul 03 06:56:25 PM PDT 24
Finished Jul 03 07:02:14 PM PDT 24
Peak memory 201912 kb
Host smart-e15a48ef-b62d-4f9c-b57c-4cc1f2f5d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191885010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3191885010
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.4208653925
Short name T99
Test name
Test status
Simulation time 169124129886 ps
CPU time 199.23 seconds
Started Jul 03 06:56:28 PM PDT 24
Finished Jul 03 06:59:47 PM PDT 24
Peak memory 201872 kb
Host smart-eab0069d-5e40-45b4-834c-79d51fe4f880
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208653925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.4208653925
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1687162985
Short name T176
Test name
Test status
Simulation time 267093324466 ps
CPU time 594.03 seconds
Started Jul 03 06:56:31 PM PDT 24
Finished Jul 03 07:06:25 PM PDT 24
Peak memory 201920 kb
Host smart-e437e029-7e12-4ba3-b61c-1ea7eb4b7d06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687162985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1687162985
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3004686578
Short name T113
Test name
Test status
Simulation time 195648187766 ps
CPU time 126.97 seconds
Started Jul 03 06:56:32 PM PDT 24
Finished Jul 03 06:58:39 PM PDT 24
Peak memory 201864 kb
Host smart-ed369632-f98b-4aa5-afca-b9c9abc52adb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004686578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3004686578
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1577195514
Short name T697
Test name
Test status
Simulation time 98839811025 ps
CPU time 345.57 seconds
Started Jul 03 06:56:41 PM PDT 24
Finished Jul 03 07:02:27 PM PDT 24
Peak memory 202184 kb
Host smart-2fd75d70-e875-498e-8ef4-1237f39a0b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577195514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1577195514
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1610908617
Short name T668
Test name
Test status
Simulation time 44203950760 ps
CPU time 104.69 seconds
Started Jul 03 06:56:36 PM PDT 24
Finished Jul 03 06:58:21 PM PDT 24
Peak memory 201716 kb
Host smart-cdd483ee-2e52-4838-a29d-36080abdd7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610908617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1610908617
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3714273226
Short name T758
Test name
Test status
Simulation time 5491520861 ps
CPU time 13.24 seconds
Started Jul 03 06:56:36 PM PDT 24
Finished Jul 03 06:56:50 PM PDT 24
Peak memory 201736 kb
Host smart-840aad6a-03ae-409a-a441-e72e5cdb6078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714273226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3714273226
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4063071449
Short name T671
Test name
Test status
Simulation time 5933954882 ps
CPU time 14.81 seconds
Started Jul 03 06:56:22 PM PDT 24
Finished Jul 03 06:56:38 PM PDT 24
Peak memory 201736 kb
Host smart-d5444a28-2a94-439e-b17f-0e568dfeec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063071449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4063071449
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.781560103
Short name T297
Test name
Test status
Simulation time 592465101323 ps
CPU time 1677.86 seconds
Started Jul 03 06:56:46 PM PDT 24
Finished Jul 03 07:24:45 PM PDT 24
Peak memory 202232 kb
Host smart-941f6cb8-0fd4-46ad-9f97-9abab5be67a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781560103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
781560103
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1755809365
Short name T783
Test name
Test status
Simulation time 39327977220 ps
CPU time 73.29 seconds
Started Jul 03 06:56:41 PM PDT 24
Finished Jul 03 06:57:54 PM PDT 24
Peak memory 216592 kb
Host smart-7231f3d7-e8da-4685-9614-98408515f6c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755809365 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1755809365
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2839348108
Short name T570
Test name
Test status
Simulation time 377274764 ps
CPU time 1.48 seconds
Started Jul 03 06:57:15 PM PDT 24
Finished Jul 03 06:57:17 PM PDT 24
Peak memory 201648 kb
Host smart-29e239ad-8bc1-441f-b7ac-690dccb7261f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839348108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2839348108
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.119024680
Short name T283
Test name
Test status
Simulation time 487855556195 ps
CPU time 181.41 seconds
Started Jul 03 06:57:01 PM PDT 24
Finished Jul 03 07:00:03 PM PDT 24
Peak memory 201896 kb
Host smart-a71b4368-6037-47e6-92d6-95c3d8faf104
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119024680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.119024680
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3349305999
Short name T558
Test name
Test status
Simulation time 165125354817 ps
CPU time 36.08 seconds
Started Jul 03 06:56:56 PM PDT 24
Finished Jul 03 06:57:33 PM PDT 24
Peak memory 201872 kb
Host smart-27769446-3bf6-4319-8e86-bb39b619d3d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349305999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3349305999
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1227826617
Short name T471
Test name
Test status
Simulation time 328356412311 ps
CPU time 737.52 seconds
Started Jul 03 06:56:49 PM PDT 24
Finished Jul 03 07:09:07 PM PDT 24
Peak memory 201960 kb
Host smart-cbdc2931-4119-4488-8078-96a630d572bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227826617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1227826617
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1259233255
Short name T576
Test name
Test status
Simulation time 321255421711 ps
CPU time 205.5 seconds
Started Jul 03 06:56:55 PM PDT 24
Finished Jul 03 07:00:21 PM PDT 24
Peak memory 201976 kb
Host smart-e4f65ce2-1873-409b-8ce7-397976904583
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259233255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1259233255
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.269749759
Short name T285
Test name
Test status
Simulation time 643157114964 ps
CPU time 215.08 seconds
Started Jul 03 06:56:57 PM PDT 24
Finished Jul 03 07:00:32 PM PDT 24
Peak memory 201928 kb
Host smart-4e1e31b0-a686-4eb2-813f-6aaceac939a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269749759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.269749759
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1497690487
Short name T152
Test name
Test status
Simulation time 616648050202 ps
CPU time 356.16 seconds
Started Jul 03 06:56:59 PM PDT 24
Finished Jul 03 07:02:56 PM PDT 24
Peak memory 201884 kb
Host smart-5d02e269-66bc-4c21-b35a-8cde4e57ea39
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497690487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1497690487
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.515973065
Short name T547
Test name
Test status
Simulation time 69782122182 ps
CPU time 402.39 seconds
Started Jul 03 06:57:09 PM PDT 24
Finished Jul 03 07:03:52 PM PDT 24
Peak memory 202144 kb
Host smart-236c737b-9119-4cde-98c4-55c7c18c3341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515973065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.515973065
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1472399568
Short name T408
Test name
Test status
Simulation time 34721119563 ps
CPU time 31.72 seconds
Started Jul 03 06:57:05 PM PDT 24
Finished Jul 03 06:57:37 PM PDT 24
Peak memory 201700 kb
Host smart-29dd4b2d-1cfd-4e32-8f23-66820c02afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472399568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1472399568
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2397601004
Short name T641
Test name
Test status
Simulation time 3126898372 ps
CPU time 7.86 seconds
Started Jul 03 06:56:59 PM PDT 24
Finished Jul 03 06:57:08 PM PDT 24
Peak memory 201732 kb
Host smart-00910226-c47b-4db2-929b-8374f1680560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397601004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2397601004
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2991938120
Short name T528
Test name
Test status
Simulation time 5690611083 ps
CPU time 5.04 seconds
Started Jul 03 06:56:45 PM PDT 24
Finished Jul 03 06:56:51 PM PDT 24
Peak memory 201660 kb
Host smart-549e18d6-103b-4c66-87e5-60dbe8642c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991938120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2991938120
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.823212163
Short name T18
Test name
Test status
Simulation time 79198877279 ps
CPU time 184.85 seconds
Started Jul 03 06:57:07 PM PDT 24
Finished Jul 03 07:00:13 PM PDT 24
Peak memory 218224 kb
Host smart-cbd91322-aa3e-4bb2-a0d9-ea9d0d7617fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823212163 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.823212163
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3765098730
Short name T767
Test name
Test status
Simulation time 310789762 ps
CPU time 0.99 seconds
Started Jul 03 06:57:30 PM PDT 24
Finished Jul 03 06:57:32 PM PDT 24
Peak memory 201596 kb
Host smart-2ea60c02-2601-4ea9-90c0-704306fc1ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765098730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3765098730
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3252256256
Short name T337
Test name
Test status
Simulation time 329724488046 ps
CPU time 132.19 seconds
Started Jul 03 06:57:26 PM PDT 24
Finished Jul 03 06:59:39 PM PDT 24
Peak memory 201952 kb
Host smart-34e2fd47-2bd3-4144-aa26-a1f6cb556f7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252256256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3252256256
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1353448930
Short name T338
Test name
Test status
Simulation time 396029573093 ps
CPU time 243.57 seconds
Started Jul 03 06:57:25 PM PDT 24
Finished Jul 03 07:01:29 PM PDT 24
Peak memory 201920 kb
Host smart-946afea7-a2e2-4fa4-9b9c-82f1c8c8cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353448930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1353448930
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2147823094
Short name T748
Test name
Test status
Simulation time 318418600625 ps
CPU time 293.2 seconds
Started Jul 03 06:57:18 PM PDT 24
Finished Jul 03 07:02:12 PM PDT 24
Peak memory 201932 kb
Host smart-6ae7c675-f11e-42a6-bf45-df1edf4e387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147823094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2147823094
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1934532526
Short name T119
Test name
Test status
Simulation time 169784308152 ps
CPU time 407.2 seconds
Started Jul 03 06:57:22 PM PDT 24
Finished Jul 03 07:04:10 PM PDT 24
Peak memory 201920 kb
Host smart-8794207b-1a1e-46ed-9ccf-7d22f251337d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934532526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1934532526
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.4235527791
Short name T195
Test name
Test status
Simulation time 333063462732 ps
CPU time 819.48 seconds
Started Jul 03 06:57:12 PM PDT 24
Finished Jul 03 07:10:52 PM PDT 24
Peak memory 201904 kb
Host smart-96d4c7d9-26e2-4bf4-b811-db95295aac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235527791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.4235527791
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1889436470
Short name T799
Test name
Test status
Simulation time 322913596571 ps
CPU time 195.76 seconds
Started Jul 03 06:57:16 PM PDT 24
Finished Jul 03 07:00:32 PM PDT 24
Peak memory 201812 kb
Host smart-82c0bc33-977e-45fc-8f70-f3ae5afdfa95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889436470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1889436470
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2921808442
Short name T713
Test name
Test status
Simulation time 449129338887 ps
CPU time 1045.62 seconds
Started Jul 03 06:57:23 PM PDT 24
Finished Jul 03 07:14:49 PM PDT 24
Peak memory 201948 kb
Host smart-8148cc5c-18f6-4044-af40-084fef4d47d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921808442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2921808442
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3053492240
Short name T642
Test name
Test status
Simulation time 605033495494 ps
CPU time 658.01 seconds
Started Jul 03 06:57:23 PM PDT 24
Finished Jul 03 07:08:22 PM PDT 24
Peak memory 201900 kb
Host smart-14c78c61-99c3-4f2c-b37c-02ae5e50e165
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053492240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3053492240
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.142490981
Short name T474
Test name
Test status
Simulation time 79404283840 ps
CPU time 248.73 seconds
Started Jul 03 06:57:28 PM PDT 24
Finished Jul 03 07:01:38 PM PDT 24
Peak memory 202280 kb
Host smart-7259c271-bacf-4900-b9b5-f2e45ff9752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142490981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.142490981
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1852228902
Short name T519
Test name
Test status
Simulation time 29505865079 ps
CPU time 16.7 seconds
Started Jul 03 06:57:27 PM PDT 24
Finished Jul 03 06:57:44 PM PDT 24
Peak memory 201736 kb
Host smart-5d98cf8d-09d1-4bcc-97bc-e2377720a39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852228902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1852228902
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3937525165
Short name T705
Test name
Test status
Simulation time 5202350195 ps
CPU time 3.5 seconds
Started Jul 03 06:57:27 PM PDT 24
Finished Jul 03 06:57:31 PM PDT 24
Peak memory 201712 kb
Host smart-81675782-2c62-4a3e-a05a-1fb159d4d58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937525165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3937525165
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3977085741
Short name T569
Test name
Test status
Simulation time 5697702435 ps
CPU time 14.07 seconds
Started Jul 03 06:57:14 PM PDT 24
Finished Jul 03 06:57:28 PM PDT 24
Peak memory 201724 kb
Host smart-ffcfc946-2901-4d77-83b4-8169223317fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977085741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3977085741
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3195172901
Short name T618
Test name
Test status
Simulation time 812626820910 ps
CPU time 1540.84 seconds
Started Jul 03 06:57:31 PM PDT 24
Finished Jul 03 07:23:13 PM PDT 24
Peak memory 218624 kb
Host smart-57e7633f-30de-4009-9b3f-d900198bcaf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195172901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3195172901
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2512059266
Short name T44
Test name
Test status
Simulation time 55685578854 ps
CPU time 66 seconds
Started Jul 03 06:57:31 PM PDT 24
Finished Jul 03 06:58:38 PM PDT 24
Peak memory 210236 kb
Host smart-d7ae9c41-59f7-437d-b330-92ca81eb2179
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512059266 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2512059266
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.635316032
Short name T711
Test name
Test status
Simulation time 481115590 ps
CPU time 1.73 seconds
Started Jul 03 06:57:50 PM PDT 24
Finished Jul 03 06:57:52 PM PDT 24
Peak memory 201672 kb
Host smart-2ab91ff2-42f2-44d4-8a2d-c54f81650b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635316032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.635316032
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3567195673
Short name T686
Test name
Test status
Simulation time 163582274075 ps
CPU time 339.11 seconds
Started Jul 03 06:57:45 PM PDT 24
Finished Jul 03 07:03:25 PM PDT 24
Peak memory 201944 kb
Host smart-ed7b6b98-0ccf-4b7c-b28a-4c0f12bd0281
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567195673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3567195673
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.34138718
Short name T172
Test name
Test status
Simulation time 484445725757 ps
CPU time 215.84 seconds
Started Jul 03 06:57:50 PM PDT 24
Finished Jul 03 07:01:27 PM PDT 24
Peak memory 201928 kb
Host smart-6bf83c13-37ba-4b97-904f-c62c489623c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34138718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.34138718
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2224131614
Short name T290
Test name
Test status
Simulation time 160933254058 ps
CPU time 383.33 seconds
Started Jul 03 06:57:41 PM PDT 24
Finished Jul 03 07:04:05 PM PDT 24
Peak memory 201940 kb
Host smart-ddb683e1-2178-4d5d-aa8d-f4fe293f2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224131614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2224131614
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.990046417
Short name T370
Test name
Test status
Simulation time 492264266529 ps
CPU time 603.25 seconds
Started Jul 03 06:57:42 PM PDT 24
Finished Jul 03 07:07:46 PM PDT 24
Peak memory 201912 kb
Host smart-7f90b202-106c-4008-9ffc-3bf94d4a24f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=990046417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.990046417
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2639751279
Short name T517
Test name
Test status
Simulation time 326236357739 ps
CPU time 716.57 seconds
Started Jul 03 06:57:36 PM PDT 24
Finished Jul 03 07:09:33 PM PDT 24
Peak memory 201888 kb
Host smart-3968d605-4cbc-47c9-acbb-b1d8f751aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639751279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2639751279
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2425237785
Short name T645
Test name
Test status
Simulation time 330002007743 ps
CPU time 364.52 seconds
Started Jul 03 06:57:34 PM PDT 24
Finished Jul 03 07:03:39 PM PDT 24
Peak memory 201864 kb
Host smart-05dec7f4-dd71-4e41-8d92-92dac2660dc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425237785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2425237785
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.100239958
Short name T653
Test name
Test status
Simulation time 176898020495 ps
CPU time 136.19 seconds
Started Jul 03 06:57:39 PM PDT 24
Finished Jul 03 06:59:56 PM PDT 24
Peak memory 201988 kb
Host smart-b949cd25-544b-4547-9d99-75c1cbb59445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100239958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.100239958
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1292699120
Short name T103
Test name
Test status
Simulation time 203275024187 ps
CPU time 389.08 seconds
Started Jul 03 06:57:39 PM PDT 24
Finished Jul 03 07:04:09 PM PDT 24
Peak memory 201920 kb
Host smart-079690df-b51a-4ac0-8abc-df7f2afeb719
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292699120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1292699120
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1679166156
Short name T198
Test name
Test status
Simulation time 120839587846 ps
CPU time 646.11 seconds
Started Jul 03 06:57:49 PM PDT 24
Finished Jul 03 07:08:36 PM PDT 24
Peak memory 202204 kb
Host smart-f0b55ea7-69b2-4837-bbfd-f6aac30c76a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679166156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1679166156
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4143610647
Short name T458
Test name
Test status
Simulation time 25655514073 ps
CPU time 14.19 seconds
Started Jul 03 06:57:49 PM PDT 24
Finished Jul 03 06:58:04 PM PDT 24
Peak memory 201616 kb
Host smart-4b26a9c4-f619-4acc-b2eb-d1edbb554bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143610647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4143610647
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1900828919
Short name T404
Test name
Test status
Simulation time 5541030073 ps
CPU time 6.67 seconds
Started Jul 03 06:57:51 PM PDT 24
Finished Jul 03 06:57:58 PM PDT 24
Peak memory 201720 kb
Host smart-f273f138-ba01-433e-a493-37b594e7e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900828919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1900828919
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.644720210
Short name T609
Test name
Test status
Simulation time 5980333666 ps
CPU time 14.53 seconds
Started Jul 03 06:57:36 PM PDT 24
Finished Jul 03 06:57:52 PM PDT 24
Peak memory 201712 kb
Host smart-876bc88f-92e0-4681-9229-f84f2223b3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644720210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.644720210
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1995093221
Short name T7
Test name
Test status
Simulation time 175980928285 ps
CPU time 194.03 seconds
Started Jul 03 06:57:51 PM PDT 24
Finished Jul 03 07:01:06 PM PDT 24
Peak memory 201912 kb
Host smart-5ca731aa-4b39-4abc-acde-bcda7321b520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995093221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1995093221
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.55272993
Short name T561
Test name
Test status
Simulation time 108738068221 ps
CPU time 35.36 seconds
Started Jul 03 06:57:48 PM PDT 24
Finished Jul 03 06:58:24 PM PDT 24
Peak memory 211284 kb
Host smart-bee7284d-f86a-4989-a8d6-30870a44fae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55272993 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.55272993
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2843061883
Short name T673
Test name
Test status
Simulation time 533406832 ps
CPU time 0.93 seconds
Started Jul 03 06:58:08 PM PDT 24
Finished Jul 03 06:58:10 PM PDT 24
Peak memory 201632 kb
Host smart-9e7b4d42-ac79-40a9-91f6-6284edde7c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843061883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2843061883
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.963555734
Short name T284
Test name
Test status
Simulation time 503898598547 ps
CPU time 846.82 seconds
Started Jul 03 06:58:08 PM PDT 24
Finished Jul 03 07:12:16 PM PDT 24
Peak memory 201980 kb
Host smart-fbafcb35-2b2a-4c26-9c38-9fcab15b4d48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963555734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.963555734
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2575058645
Short name T358
Test name
Test status
Simulation time 167475227169 ps
CPU time 392.41 seconds
Started Jul 03 06:58:03 PM PDT 24
Finished Jul 03 07:04:37 PM PDT 24
Peak memory 201916 kb
Host smart-36d6c9ed-dedd-42bc-bc37-487bbc1bd538
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575058645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2575058645
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.752924271
Short name T13
Test name
Test status
Simulation time 320378793710 ps
CPU time 40.96 seconds
Started Jul 03 06:58:06 PM PDT 24
Finished Jul 03 06:58:48 PM PDT 24
Peak memory 201924 kb
Host smart-ef9288b4-4efa-45f8-8872-88d94118d7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752924271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.752924271
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1246361038
Short name T480
Test name
Test status
Simulation time 494986542070 ps
CPU time 299.17 seconds
Started Jul 03 06:58:06 PM PDT 24
Finished Jul 03 07:03:06 PM PDT 24
Peak memory 201912 kb
Host smart-dccfddf4-4a79-461d-b247-f91dda43b424
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246361038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1246361038
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2415941523
Short name T239
Test name
Test status
Simulation time 611445979513 ps
CPU time 897.67 seconds
Started Jul 03 06:58:03 PM PDT 24
Finished Jul 03 07:13:01 PM PDT 24
Peak memory 201892 kb
Host smart-31ec01df-0295-4e60-842d-20809a87afc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415941523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2415941523
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.615395237
Short name T429
Test name
Test status
Simulation time 415008721163 ps
CPU time 245.53 seconds
Started Jul 03 06:58:08 PM PDT 24
Finished Jul 03 07:02:15 PM PDT 24
Peak memory 201864 kb
Host smart-2cf07534-a05d-4531-8f4d-47bf1331cfb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615395237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.615395237
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3653058602
Short name T450
Test name
Test status
Simulation time 124556230672 ps
CPU time 629.41 seconds
Started Jul 03 06:58:08 PM PDT 24
Finished Jul 03 07:08:38 PM PDT 24
Peak memory 202208 kb
Host smart-e93ea8e9-31ca-41eb-a288-7c063131f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653058602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3653058602
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2129704701
Short name T658
Test name
Test status
Simulation time 22473337343 ps
CPU time 8.07 seconds
Started Jul 03 06:58:08 PM PDT 24
Finished Jul 03 06:58:16 PM PDT 24
Peak memory 201688 kb
Host smart-7d616a11-1bb0-4553-9649-d091a77c1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129704701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2129704701
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1492011931
Short name T640
Test name
Test status
Simulation time 3482048393 ps
CPU time 2.79 seconds
Started Jul 03 06:58:06 PM PDT 24
Finished Jul 03 06:58:09 PM PDT 24
Peak memory 201712 kb
Host smart-72e263db-c7d6-43ae-bd61-76da8c3d540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492011931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1492011931
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2430578435
Short name T708
Test name
Test status
Simulation time 5801085138 ps
CPU time 2.24 seconds
Started Jul 03 06:57:53 PM PDT 24
Finished Jul 03 06:57:56 PM PDT 24
Peak memory 201760 kb
Host smart-bc896bb9-caba-4b32-a59c-0cbe8a72761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430578435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2430578435
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.732064048
Short name T597
Test name
Test status
Simulation time 338013116 ps
CPU time 1.38 seconds
Started Jul 03 06:51:24 PM PDT 24
Finished Jul 03 06:51:26 PM PDT 24
Peak memory 201672 kb
Host smart-488d181e-2b64-4e17-a329-33a28d6d233c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732064048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.732064048
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3070882712
Short name T608
Test name
Test status
Simulation time 344679078976 ps
CPU time 704.96 seconds
Started Jul 03 06:51:00 PM PDT 24
Finished Jul 03 07:02:46 PM PDT 24
Peak memory 201984 kb
Host smart-10c20cbf-70d5-475e-ac65-008f6b395da8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070882712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3070882712
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1946868709
Short name T687
Test name
Test status
Simulation time 567149935185 ps
CPU time 1261.95 seconds
Started Jul 03 06:51:11 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 201900 kb
Host smart-2be675af-5c7a-430d-bf48-06aacc715e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946868709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1946868709
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4106911427
Short name T224
Test name
Test status
Simulation time 489125641680 ps
CPU time 521.45 seconds
Started Jul 03 06:51:00 PM PDT 24
Finished Jul 03 06:59:42 PM PDT 24
Peak memory 201948 kb
Host smart-223353e6-70f4-49e2-8b5b-deff43cf7da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106911427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4106911427
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3382704906
Short name T573
Test name
Test status
Simulation time 326513574676 ps
CPU time 372.01 seconds
Started Jul 03 06:51:01 PM PDT 24
Finished Jul 03 06:57:14 PM PDT 24
Peak memory 201928 kb
Host smart-d7a1fc6a-1f98-4ec8-84ce-a50fa96e8fac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382704906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3382704906
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1433970433
Short name T173
Test name
Test status
Simulation time 493252487048 ps
CPU time 125.36 seconds
Started Jul 03 06:51:02 PM PDT 24
Finished Jul 03 06:53:08 PM PDT 24
Peak memory 201912 kb
Host smart-183ea23b-f3e0-49df-82d1-d7f7a7c821ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433970433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1433970433
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.313260568
Short name T796
Test name
Test status
Simulation time 331963683194 ps
CPU time 209.38 seconds
Started Jul 03 06:51:00 PM PDT 24
Finished Jul 03 06:54:30 PM PDT 24
Peak memory 201936 kb
Host smart-70f325ba-bd14-4672-8bef-4780e948651d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=313260568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.313260568
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1147912433
Short name T572
Test name
Test status
Simulation time 349806455193 ps
CPU time 848.97 seconds
Started Jul 03 06:51:01 PM PDT 24
Finished Jul 03 07:05:11 PM PDT 24
Peak memory 201868 kb
Host smart-9c0bbe95-9080-41a0-9dc4-5a5437b5eacc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147912433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1147912433
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1708429083
Short name T538
Test name
Test status
Simulation time 604987509733 ps
CPU time 739.28 seconds
Started Jul 03 06:51:01 PM PDT 24
Finished Jul 03 07:03:21 PM PDT 24
Peak memory 201960 kb
Host smart-433bbedb-6879-4bbb-869e-05e7a702267b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708429083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1708429083
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3883884137
Short name T344
Test name
Test status
Simulation time 72897689708 ps
CPU time 234.48 seconds
Started Jul 03 06:51:21 PM PDT 24
Finished Jul 03 06:55:16 PM PDT 24
Peak memory 202224 kb
Host smart-fed7f61c-adbb-48af-8eec-ef5c720b29e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883884137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3883884137
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3488695905
Short name T715
Test name
Test status
Simulation time 38388810309 ps
CPU time 19.75 seconds
Started Jul 03 06:51:15 PM PDT 24
Finished Jul 03 06:51:35 PM PDT 24
Peak memory 201744 kb
Host smart-d0d42e0e-c819-46e1-8c70-0eeabff1916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488695905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3488695905
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4269818410
Short name T701
Test name
Test status
Simulation time 4592113549 ps
CPU time 10.52 seconds
Started Jul 03 06:51:12 PM PDT 24
Finished Jul 03 06:51:23 PM PDT 24
Peak memory 201724 kb
Host smart-239efc3c-0813-48c0-ba6e-3e5ea2b3fdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269818410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4269818410
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1515834770
Short name T85
Test name
Test status
Simulation time 7744933760 ps
CPU time 4.74 seconds
Started Jul 03 06:51:26 PM PDT 24
Finished Jul 03 06:51:32 PM PDT 24
Peak memory 218260 kb
Host smart-2dbd888d-90cc-4d46-958c-5ff999b8f1cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515834770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1515834770
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2260070723
Short name T583
Test name
Test status
Simulation time 5806429470 ps
CPU time 4.62 seconds
Started Jul 03 06:50:57 PM PDT 24
Finished Jul 03 06:51:02 PM PDT 24
Peak memory 201732 kb
Host smart-c6d8b6c6-c34f-40fe-a75f-b47350e0de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260070723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2260070723
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1883897284
Short name T399
Test name
Test status
Simulation time 14152914382 ps
CPU time 17.22 seconds
Started Jul 03 06:51:20 PM PDT 24
Finished Jul 03 06:51:37 PM PDT 24
Peak memory 201700 kb
Host smart-6dd3cbb0-697e-4a28-911e-4fb0022de924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883897284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1883897284
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.873999665
Short name T607
Test name
Test status
Simulation time 70334178073 ps
CPU time 37.53 seconds
Started Jul 03 06:51:21 PM PDT 24
Finished Jul 03 06:51:59 PM PDT 24
Peak memory 210572 kb
Host smart-20fdb53e-8917-4728-bc25-464a20f09f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873999665 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.873999665
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2098054161
Short name T384
Test name
Test status
Simulation time 511417602 ps
CPU time 1.73 seconds
Started Jul 03 06:58:27 PM PDT 24
Finished Jul 03 06:58:29 PM PDT 24
Peak memory 201652 kb
Host smart-e801036f-1efc-4d4a-af69-777af5e8735e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098054161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2098054161
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.324353659
Short name T145
Test name
Test status
Simulation time 486504935328 ps
CPU time 555.33 seconds
Started Jul 03 06:58:12 PM PDT 24
Finished Jul 03 07:07:28 PM PDT 24
Peak memory 201892 kb
Host smart-a41d7ce2-8fd3-4bf3-85ee-302589ce37d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324353659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.324353659
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2928774441
Short name T32
Test name
Test status
Simulation time 335328147048 ps
CPU time 377.61 seconds
Started Jul 03 06:58:10 PM PDT 24
Finished Jul 03 07:04:28 PM PDT 24
Peak memory 201832 kb
Host smart-32cde14f-41e7-43f0-864d-b36485388309
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928774441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2928774441
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.573925956
Short name T635
Test name
Test status
Simulation time 167675437602 ps
CPU time 189.13 seconds
Started Jul 03 06:58:14 PM PDT 24
Finished Jul 03 07:01:24 PM PDT 24
Peak memory 201904 kb
Host smart-bff59072-0c23-4b30-a203-e8ed294a62b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573925956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.573925956
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.811225836
Short name T657
Test name
Test status
Simulation time 483414522326 ps
CPU time 850.71 seconds
Started Jul 03 06:58:10 PM PDT 24
Finished Jul 03 07:12:21 PM PDT 24
Peak memory 201940 kb
Host smart-93249893-d140-43e2-9513-b0269d5c5813
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=811225836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.811225836
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1686631086
Short name T494
Test name
Test status
Simulation time 602200550682 ps
CPU time 734.18 seconds
Started Jul 03 06:58:18 PM PDT 24
Finished Jul 03 07:10:32 PM PDT 24
Peak memory 201884 kb
Host smart-716568cf-de67-4ebc-9532-a686506f3121
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686631086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1686631086
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.967416406
Short name T346
Test name
Test status
Simulation time 74306318506 ps
CPU time 269.46 seconds
Started Jul 03 06:58:27 PM PDT 24
Finished Jul 03 07:02:56 PM PDT 24
Peak memory 202176 kb
Host smart-29247985-9a23-4892-a33f-e8eab54440db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967416406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.967416406
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3864506190
Short name T732
Test name
Test status
Simulation time 38203579465 ps
CPU time 81.47 seconds
Started Jul 03 06:58:22 PM PDT 24
Finished Jul 03 06:59:45 PM PDT 24
Peak memory 201692 kb
Host smart-a6bfa7d4-fc46-4c3b-a488-609dcc030e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864506190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3864506190
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.622547381
Short name T350
Test name
Test status
Simulation time 3206047188 ps
CPU time 2.52 seconds
Started Jul 03 06:58:22 PM PDT 24
Finished Jul 03 06:58:26 PM PDT 24
Peak memory 201740 kb
Host smart-94c69263-15db-455e-8f60-7cdc519febac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622547381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.622547381
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1876081137
Short name T696
Test name
Test status
Simulation time 5717862334 ps
CPU time 9.77 seconds
Started Jul 03 06:58:11 PM PDT 24
Finished Jul 03 06:58:22 PM PDT 24
Peak memory 201708 kb
Host smart-d89e52bf-4f7f-497d-b5ac-00159dbbeb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876081137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1876081137
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1761522565
Short name T738
Test name
Test status
Simulation time 232453994630 ps
CPU time 1113.31 seconds
Started Jul 03 06:58:25 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 210372 kb
Host smart-c19113b1-ddc0-4fe5-bef5-f8a311550a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761522565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1761522565
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1829266262
Short name T740
Test name
Test status
Simulation time 10000155487 ps
CPU time 6.27 seconds
Started Jul 03 06:58:25 PM PDT 24
Finished Jul 03 06:58:32 PM PDT 24
Peak memory 210312 kb
Host smart-fdcc0718-1a09-49c8-a052-e91532bfcb14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829266262 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1829266262
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.751888010
Short name T733
Test name
Test status
Simulation time 331485380 ps
CPU time 1.41 seconds
Started Jul 03 06:58:46 PM PDT 24
Finished Jul 03 06:58:48 PM PDT 24
Peak memory 201664 kb
Host smart-694fee1f-83ae-4293-acfa-f08e42a6fa4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751888010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.751888010
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2787622707
Short name T116
Test name
Test status
Simulation time 196095229723 ps
CPU time 387.4 seconds
Started Jul 03 06:58:34 PM PDT 24
Finished Jul 03 07:05:02 PM PDT 24
Peak memory 201924 kb
Host smart-64aa5300-3347-46fc-8c58-23ffc629417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787622707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2787622707
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3027465602
Short name T298
Test name
Test status
Simulation time 490183352264 ps
CPU time 287.07 seconds
Started Jul 03 06:58:31 PM PDT 24
Finished Jul 03 07:03:18 PM PDT 24
Peak memory 201940 kb
Host smart-fb0cb81b-0b99-464a-91f3-e2f099527f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027465602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3027465602
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3680562327
Short name T410
Test name
Test status
Simulation time 170369142468 ps
CPU time 33.32 seconds
Started Jul 03 06:58:36 PM PDT 24
Finished Jul 03 06:59:11 PM PDT 24
Peak memory 201844 kb
Host smart-8217aab5-5869-4c8c-a6a1-ba098965d238
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680562327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3680562327
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.4136529434
Short name T621
Test name
Test status
Simulation time 328026868053 ps
CPU time 194.54 seconds
Started Jul 03 06:58:31 PM PDT 24
Finished Jul 03 07:01:46 PM PDT 24
Peak memory 201960 kb
Host smart-76c06d91-bfa1-4e30-866f-11d7c1a8af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136529434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4136529434
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4035217464
Short name T363
Test name
Test status
Simulation time 324442212685 ps
CPU time 181.18 seconds
Started Jul 03 06:58:32 PM PDT 24
Finished Jul 03 07:01:33 PM PDT 24
Peak memory 201972 kb
Host smart-22712e4f-3f34-4f4e-b07c-84ff9e1913ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035217464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4035217464
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3303584736
Short name T326
Test name
Test status
Simulation time 364592277037 ps
CPU time 431.15 seconds
Started Jul 03 06:58:36 PM PDT 24
Finished Jul 03 07:05:48 PM PDT 24
Peak memory 201868 kb
Host smart-4603373f-e3ce-4262-8e4d-ab6381fb671e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303584736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3303584736
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.881930659
Short name T439
Test name
Test status
Simulation time 205685910656 ps
CPU time 116.95 seconds
Started Jul 03 06:58:35 PM PDT 24
Finished Jul 03 07:00:33 PM PDT 24
Peak memory 201880 kb
Host smart-638841ef-9301-4fc3-a716-9279aa5397cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881930659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.881930659
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1675930748
Short name T367
Test name
Test status
Simulation time 43449011130 ps
CPU time 52.82 seconds
Started Jul 03 06:58:39 PM PDT 24
Finished Jul 03 06:59:32 PM PDT 24
Peak memory 201724 kb
Host smart-a402a7aa-35dd-49b7-8021-fe4cce2ae413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675930748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1675930748
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1094283368
Short name T356
Test name
Test status
Simulation time 4303186823 ps
CPU time 5.57 seconds
Started Jul 03 06:58:38 PM PDT 24
Finished Jul 03 06:58:44 PM PDT 24
Peak memory 201556 kb
Host smart-bbc1df6d-7b7e-41a4-8a38-411a44977311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094283368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1094283368
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.884922496
Short name T47
Test name
Test status
Simulation time 5596331280 ps
CPU time 4.37 seconds
Started Jul 03 06:58:31 PM PDT 24
Finished Jul 03 06:58:36 PM PDT 24
Peak memory 201720 kb
Host smart-a070860c-eb39-4c05-af8f-f5243a281db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884922496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.884922496
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1014708821
Short name T800
Test name
Test status
Simulation time 232878412909 ps
CPU time 38.72 seconds
Started Jul 03 06:58:45 PM PDT 24
Finished Jul 03 06:59:24 PM PDT 24
Peak memory 201932 kb
Host smart-f457f725-0123-463f-873e-8bc286eba4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014708821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1014708821
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1237907544
Short name T378
Test name
Test status
Simulation time 312537017 ps
CPU time 0.81 seconds
Started Jul 03 06:58:56 PM PDT 24
Finished Jul 03 06:58:58 PM PDT 24
Peak memory 201632 kb
Host smart-391a65a2-17b3-42e8-841b-2853af94bb32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237907544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1237907544
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3940462192
Short name T323
Test name
Test status
Simulation time 329125390832 ps
CPU time 176.04 seconds
Started Jul 03 06:58:49 PM PDT 24
Finished Jul 03 07:01:46 PM PDT 24
Peak memory 202004 kb
Host smart-24358b71-3acd-457f-af04-e79f55b46aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940462192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3940462192
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3573171131
Short name T611
Test name
Test status
Simulation time 332536396126 ps
CPU time 201.43 seconds
Started Jul 03 06:58:48 PM PDT 24
Finished Jul 03 07:02:10 PM PDT 24
Peak memory 201896 kb
Host smart-7319d0d5-1030-4340-adee-e4dc61d9dbeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573171131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3573171131
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1432131354
Short name T154
Test name
Test status
Simulation time 489120877073 ps
CPU time 244.62 seconds
Started Jul 03 06:58:44 PM PDT 24
Finished Jul 03 07:02:49 PM PDT 24
Peak memory 201904 kb
Host smart-4e0084c8-18e3-4c76-a04d-0bb10dccafbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432131354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1432131354
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2906145217
Short name T382
Test name
Test status
Simulation time 492037168516 ps
CPU time 616.63 seconds
Started Jul 03 06:58:44 PM PDT 24
Finished Jul 03 07:09:01 PM PDT 24
Peak memory 201860 kb
Host smart-13f25b69-e40e-49e1-a07a-d2ba37c4747f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906145217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2906145217
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.958619631
Short name T319
Test name
Test status
Simulation time 380341991318 ps
CPU time 765.45 seconds
Started Jul 03 06:58:51 PM PDT 24
Finished Jul 03 07:11:38 PM PDT 24
Peak memory 201940 kb
Host smart-14d9ed01-f3e1-4a79-92b7-bf622e9b592e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958619631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.958619631
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.105331931
Short name T415
Test name
Test status
Simulation time 408773760365 ps
CPU time 689.83 seconds
Started Jul 03 06:58:50 PM PDT 24
Finished Jul 03 07:10:21 PM PDT 24
Peak memory 201984 kb
Host smart-be583bef-52e7-4354-93dc-5ab7b1d63491
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105331931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.105331931
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2958350472
Short name T650
Test name
Test status
Simulation time 122049515041 ps
CPU time 406.55 seconds
Started Jul 03 06:58:58 PM PDT 24
Finished Jul 03 07:05:45 PM PDT 24
Peak memory 202216 kb
Host smart-40d63857-6b58-461b-af55-5441e2ee7cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958350472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2958350472
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.72628786
Short name T406
Test name
Test status
Simulation time 33629648035 ps
CPU time 19.2 seconds
Started Jul 03 06:58:59 PM PDT 24
Finished Jul 03 06:59:19 PM PDT 24
Peak memory 201720 kb
Host smart-f9bcc954-1f57-4225-b437-191b81113478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72628786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.72628786
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.365516192
Short name T421
Test name
Test status
Simulation time 3299500174 ps
CPU time 3.61 seconds
Started Jul 03 06:58:57 PM PDT 24
Finished Jul 03 06:59:01 PM PDT 24
Peak memory 201716 kb
Host smart-88e5aa96-239b-49b6-8095-4fc54c50b4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365516192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.365516192
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.93741642
Short name T106
Test name
Test status
Simulation time 5658176923 ps
CPU time 4.07 seconds
Started Jul 03 06:58:43 PM PDT 24
Finished Jul 03 06:58:47 PM PDT 24
Peak memory 201716 kb
Host smart-1c9199ed-a25a-4a29-b5a5-24027d23295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93741642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.93741642
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.8128592
Short name T704
Test name
Test status
Simulation time 323518544640 ps
CPU time 140.68 seconds
Started Jul 03 06:58:56 PM PDT 24
Finished Jul 03 07:01:17 PM PDT 24
Peak memory 201980 kb
Host smart-8cccce3e-cc12-4be5-a583-58baa0bd6a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8128592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.8128592
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4086510961
Short name T534
Test name
Test status
Simulation time 547477908 ps
CPU time 0.89 seconds
Started Jul 03 06:59:15 PM PDT 24
Finished Jul 03 06:59:17 PM PDT 24
Peak memory 201672 kb
Host smart-665129d9-8a31-4f02-9eb6-c701b5b9f426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086510961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4086510961
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3371547065
Short name T339
Test name
Test status
Simulation time 458203197141 ps
CPU time 499.24 seconds
Started Jul 03 06:59:06 PM PDT 24
Finished Jul 03 07:07:26 PM PDT 24
Peak memory 201932 kb
Host smart-46867c28-c26c-4e22-b043-930b8e6b36e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371547065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3371547065
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4281336267
Short name T536
Test name
Test status
Simulation time 493058419763 ps
CPU time 579.97 seconds
Started Jul 03 06:59:02 PM PDT 24
Finished Jul 03 07:08:42 PM PDT 24
Peak memory 201852 kb
Host smart-3d481592-aef9-4891-bfa8-215fc96df23f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281336267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4281336267
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4208780511
Short name T629
Test name
Test status
Simulation time 336101301781 ps
CPU time 380.69 seconds
Started Jul 03 06:59:02 PM PDT 24
Finished Jul 03 07:05:23 PM PDT 24
Peak memory 201908 kb
Host smart-3f6fea21-a537-48c0-bb26-12af17146786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208780511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4208780511
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2237545254
Short name T423
Test name
Test status
Simulation time 325056703675 ps
CPU time 762.48 seconds
Started Jul 03 06:59:00 PM PDT 24
Finished Jul 03 07:11:43 PM PDT 24
Peak memory 201984 kb
Host smart-61b98bcd-ac06-4f6a-b3ce-7f809802d3ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237545254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2237545254
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.99782849
Short name T220
Test name
Test status
Simulation time 244018341625 ps
CPU time 128.83 seconds
Started Jul 03 06:59:07 PM PDT 24
Finished Jul 03 07:01:16 PM PDT 24
Peak memory 201916 kb
Host smart-f3a86a18-3c5d-444f-b038-1cc15be13475
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99782849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_w
akeup.99782849
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1716304035
Short name T388
Test name
Test status
Simulation time 600003391094 ps
CPU time 1410.98 seconds
Started Jul 03 06:59:05 PM PDT 24
Finished Jul 03 07:22:36 PM PDT 24
Peak memory 201876 kb
Host smart-e250d843-66a0-423b-b045-b7a6aec889f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716304035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1716304035
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1817466888
Short name T343
Test name
Test status
Simulation time 85578995067 ps
CPU time 381.11 seconds
Started Jul 03 06:59:11 PM PDT 24
Finished Jul 03 07:05:33 PM PDT 24
Peak memory 202164 kb
Host smart-cc97a0e6-968e-4a83-ae0d-f1df9b6339d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817466888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1817466888
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2215174535
Short name T448
Test name
Test status
Simulation time 27026827322 ps
CPU time 16.03 seconds
Started Jul 03 06:59:11 PM PDT 24
Finished Jul 03 06:59:27 PM PDT 24
Peak memory 201724 kb
Host smart-1d3e2f93-ad0d-48e1-bd3a-0f092ddff36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215174535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2215174535
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3632493438
Short name T606
Test name
Test status
Simulation time 4685765012 ps
CPU time 11.83 seconds
Started Jul 03 06:59:05 PM PDT 24
Finished Jul 03 06:59:18 PM PDT 24
Peak memory 201692 kb
Host smart-56ba86aa-5887-4366-8369-aa3db6ca925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632493438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3632493438
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2638121524
Short name T747
Test name
Test status
Simulation time 5946897125 ps
CPU time 8.1 seconds
Started Jul 03 06:58:55 PM PDT 24
Finished Jul 03 06:59:04 PM PDT 24
Peak memory 201736 kb
Host smart-99fc697b-a633-451e-a38d-44b6190bcdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638121524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2638121524
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1742797236
Short name T452
Test name
Test status
Simulation time 499184359 ps
CPU time 0.91 seconds
Started Jul 03 06:59:33 PM PDT 24
Finished Jul 03 06:59:34 PM PDT 24
Peak memory 201664 kb
Host smart-a48cba8e-4487-4eb9-9b51-8bf633f8f14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742797236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1742797236
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3850736333
Short name T177
Test name
Test status
Simulation time 191896708463 ps
CPU time 177.15 seconds
Started Jul 03 06:59:29 PM PDT 24
Finished Jul 03 07:02:26 PM PDT 24
Peak memory 201908 kb
Host smart-7699ee14-0867-457d-8453-5bbdabc5e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850736333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3850736333
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3399786625
Short name T27
Test name
Test status
Simulation time 333344725026 ps
CPU time 197.69 seconds
Started Jul 03 06:59:18 PM PDT 24
Finished Jul 03 07:02:36 PM PDT 24
Peak memory 201880 kb
Host smart-a99930c1-84e1-4bc6-aafa-a73976abaeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399786625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3399786625
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2896848402
Short name T414
Test name
Test status
Simulation time 325255600708 ps
CPU time 203.12 seconds
Started Jul 03 06:59:20 PM PDT 24
Finished Jul 03 07:02:43 PM PDT 24
Peak memory 201896 kb
Host smart-5ddaab6d-8605-4f05-99b0-e50e19d9348c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896848402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2896848402
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.326338615
Short name T789
Test name
Test status
Simulation time 160805761135 ps
CPU time 94.09 seconds
Started Jul 03 06:59:15 PM PDT 24
Finished Jul 03 07:00:50 PM PDT 24
Peak memory 201932 kb
Host smart-199db03a-fa96-488d-9150-e43b054de307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326338615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.326338615
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2710516066
Short name T483
Test name
Test status
Simulation time 164549065535 ps
CPU time 387.23 seconds
Started Jul 03 06:59:14 PM PDT 24
Finished Jul 03 07:05:41 PM PDT 24
Peak memory 201932 kb
Host smart-f81ea5e6-8df3-442d-b719-2da58a36c675
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710516066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2710516066
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2397752199
Short name T674
Test name
Test status
Simulation time 384876774660 ps
CPU time 867.22 seconds
Started Jul 03 06:59:25 PM PDT 24
Finished Jul 03 07:13:53 PM PDT 24
Peak memory 201912 kb
Host smart-8f7f122d-4d0d-4f9f-abeb-ca664e178591
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397752199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2397752199
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2724391157
Short name T203
Test name
Test status
Simulation time 79198764907 ps
CPU time 379.8 seconds
Started Jul 03 06:59:30 PM PDT 24
Finished Jul 03 07:05:50 PM PDT 24
Peak memory 202044 kb
Host smart-792e5412-7839-4a65-bad5-8ce711a4dc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724391157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2724391157
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4096315474
Short name T443
Test name
Test status
Simulation time 23034107084 ps
CPU time 53.02 seconds
Started Jul 03 06:59:28 PM PDT 24
Finished Jul 03 07:00:22 PM PDT 24
Peak memory 201712 kb
Host smart-759443f8-011d-4e21-a939-b03199b5a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096315474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4096315474
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2501320583
Short name T31
Test name
Test status
Simulation time 4477320531 ps
CPU time 3.03 seconds
Started Jul 03 06:59:28 PM PDT 24
Finished Jul 03 06:59:31 PM PDT 24
Peak memory 201716 kb
Host smart-13c47e04-c3be-46b3-9335-78f7ac0d97bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501320583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2501320583
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.959725925
Short name T502
Test name
Test status
Simulation time 5942962828 ps
CPU time 14.57 seconds
Started Jul 03 06:59:14 PM PDT 24
Finished Jul 03 06:59:29 PM PDT 24
Peak memory 201748 kb
Host smart-e4e6a920-39b3-4043-b907-7b8c0dae447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959725925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.959725925
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.558587963
Short name T36
Test name
Test status
Simulation time 436713308379 ps
CPU time 1346.8 seconds
Started Jul 03 06:59:34 PM PDT 24
Finished Jul 03 07:22:02 PM PDT 24
Peak memory 210424 kb
Host smart-4567da1e-a11b-4480-a290-1984a5796b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558587963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
558587963
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2212447999
Short name T161
Test name
Test status
Simulation time 146308032641 ps
CPU time 68.33 seconds
Started Jul 03 06:59:33 PM PDT 24
Finished Jul 03 07:00:42 PM PDT 24
Peak memory 210600 kb
Host smart-569ad615-1f7a-44de-bf36-38b977c8458c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212447999 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2212447999
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1391395836
Short name T562
Test name
Test status
Simulation time 452005856 ps
CPU time 0.93 seconds
Started Jul 03 06:59:53 PM PDT 24
Finished Jul 03 06:59:55 PM PDT 24
Peak memory 201672 kb
Host smart-d25c3571-8c54-4942-a65e-20446b0f1ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391395836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1391395836
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.601697970
Short name T249
Test name
Test status
Simulation time 517235883574 ps
CPU time 1090.92 seconds
Started Jul 03 06:59:47 PM PDT 24
Finished Jul 03 07:17:59 PM PDT 24
Peak memory 201884 kb
Host smart-4eefbd15-b45f-4f80-af75-2f91bbd83cb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601697970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.601697970
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1640721483
Short name T314
Test name
Test status
Simulation time 513495955834 ps
CPU time 329.59 seconds
Started Jul 03 06:59:47 PM PDT 24
Finished Jul 03 07:05:17 PM PDT 24
Peak memory 201884 kb
Host smart-1102a546-85d6-43ca-8fcd-ccec9737f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640721483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1640721483
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.199938059
Short name T11
Test name
Test status
Simulation time 336642018322 ps
CPU time 411.78 seconds
Started Jul 03 06:59:43 PM PDT 24
Finished Jul 03 07:06:35 PM PDT 24
Peak memory 201856 kb
Host smart-dd57775a-d703-4937-8291-7d8cdbcecc9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=199938059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.199938059
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.643600132
Short name T187
Test name
Test status
Simulation time 489579113443 ps
CPU time 153.34 seconds
Started Jul 03 06:59:38 PM PDT 24
Finished Jul 03 07:02:12 PM PDT 24
Peak memory 201992 kb
Host smart-f618ab13-e5e0-41b3-b055-b25623229414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643600132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.643600132
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3486885208
Short name T89
Test name
Test status
Simulation time 161746494030 ps
CPU time 354.95 seconds
Started Jul 03 06:59:38 PM PDT 24
Finished Jul 03 07:05:33 PM PDT 24
Peak memory 201900 kb
Host smart-16ae6c64-33df-4ec5-9483-56738ba98454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486885208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3486885208
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3853924874
Short name T335
Test name
Test status
Simulation time 353206674646 ps
CPU time 274.95 seconds
Started Jul 03 06:59:44 PM PDT 24
Finished Jul 03 07:04:19 PM PDT 24
Peak memory 201936 kb
Host smart-403b6e13-a4ad-4efc-b543-01aaa95fe7e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853924874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3853924874
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.475046408
Short name T688
Test name
Test status
Simulation time 412453705488 ps
CPU time 170.2 seconds
Started Jul 03 06:59:42 PM PDT 24
Finished Jul 03 07:02:33 PM PDT 24
Peak memory 201912 kb
Host smart-36b0a8ac-d4c4-4c0f-a305-50f81d5c21e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475046408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.475046408
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2218941432
Short name T409
Test name
Test status
Simulation time 38403679577 ps
CPU time 56.09 seconds
Started Jul 03 06:59:45 PM PDT 24
Finished Jul 03 07:00:42 PM PDT 24
Peak memory 201712 kb
Host smart-e16d2ca3-cd77-4aa7-9625-b6a9e14ab73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218941432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2218941432
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2293870610
Short name T10
Test name
Test status
Simulation time 4856566109 ps
CPU time 3.42 seconds
Started Jul 03 06:59:46 PM PDT 24
Finished Jul 03 06:59:50 PM PDT 24
Peak memory 201732 kb
Host smart-762dd827-0411-4e6f-a26d-98fd4f306cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293870610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2293870610
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3995486034
Short name T637
Test name
Test status
Simulation time 5945794488 ps
CPU time 7.05 seconds
Started Jul 03 06:59:37 PM PDT 24
Finished Jul 03 06:59:45 PM PDT 24
Peak memory 201704 kb
Host smart-19631509-a048-4242-97ef-425bbfea0ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995486034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3995486034
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3077371433
Short name T301
Test name
Test status
Simulation time 499364479142 ps
CPU time 1119.44 seconds
Started Jul 03 06:59:53 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 201884 kb
Host smart-218a6c61-89ce-4b41-87d5-3ce603e0f4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077371433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3077371433
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3143631858
Short name T15
Test name
Test status
Simulation time 81222837288 ps
CPU time 171.26 seconds
Started Jul 03 06:59:51 PM PDT 24
Finished Jul 03 07:02:43 PM PDT 24
Peak memory 217952 kb
Host smart-0d9b9b45-727c-49e9-b13d-c1863011e754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143631858 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3143631858
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2046818740
Short name T357
Test name
Test status
Simulation time 541479255 ps
CPU time 1.22 seconds
Started Jul 03 07:00:05 PM PDT 24
Finished Jul 03 07:00:07 PM PDT 24
Peak memory 201676 kb
Host smart-6592d623-1580-413d-9500-4811bc9ec5ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046818740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2046818740
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.755279236
Short name T257
Test name
Test status
Simulation time 166527717438 ps
CPU time 380.33 seconds
Started Jul 03 07:00:05 PM PDT 24
Finished Jul 03 07:06:26 PM PDT 24
Peak memory 201984 kb
Host smart-04a0ef70-9a75-48ca-b8cf-7d4b60fe48a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755279236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.755279236
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1707311391
Short name T274
Test name
Test status
Simulation time 491482485616 ps
CPU time 1083.29 seconds
Started Jul 03 07:00:00 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 201988 kb
Host smart-c189aa8c-8abc-48f5-8a3c-30d0fb04133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707311391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1707311391
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2481960332
Short name T543
Test name
Test status
Simulation time 333649508902 ps
CPU time 54.62 seconds
Started Jul 03 07:00:01 PM PDT 24
Finished Jul 03 07:00:56 PM PDT 24
Peak memory 201896 kb
Host smart-060311e1-5af5-4f35-ad23-e661291be158
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481960332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2481960332
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2947831555
Short name T734
Test name
Test status
Simulation time 328814135837 ps
CPU time 356.7 seconds
Started Jul 03 06:59:51 PM PDT 24
Finished Jul 03 07:05:48 PM PDT 24
Peak memory 201932 kb
Host smart-f45fefd9-4113-45c5-bb13-b4c80f0aa560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947831555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2947831555
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1410848847
Short name T88
Test name
Test status
Simulation time 331472253134 ps
CPU time 736.06 seconds
Started Jul 03 06:59:58 PM PDT 24
Finished Jul 03 07:12:14 PM PDT 24
Peak memory 201920 kb
Host smart-2eb2e20b-1f4a-4909-8c63-df8bf268ca2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410848847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1410848847
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3455918856
Short name T447
Test name
Test status
Simulation time 174911257594 ps
CPU time 195.84 seconds
Started Jul 03 07:00:01 PM PDT 24
Finished Jul 03 07:03:17 PM PDT 24
Peak memory 201928 kb
Host smart-acf42efa-a91b-4dd7-a4d9-f54336450a19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455918856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3455918856
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1375799903
Short name T115
Test name
Test status
Simulation time 592674483613 ps
CPU time 1234.04 seconds
Started Jul 03 07:00:00 PM PDT 24
Finished Jul 03 07:20:34 PM PDT 24
Peak memory 201884 kb
Host smart-9eb8691f-951c-4a50-8547-d129d0d45bae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375799903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1375799903
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2023482919
Short name T401
Test name
Test status
Simulation time 43739164549 ps
CPU time 96.49 seconds
Started Jul 03 07:00:06 PM PDT 24
Finished Jul 03 07:01:43 PM PDT 24
Peak memory 201728 kb
Host smart-d91a1425-3131-4b23-af27-2be1d9ce6d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023482919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2023482919
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1555201977
Short name T375
Test name
Test status
Simulation time 4443865608 ps
CPU time 6.08 seconds
Started Jul 03 07:00:05 PM PDT 24
Finished Jul 03 07:00:12 PM PDT 24
Peak memory 201724 kb
Host smart-f60c7df1-21a5-43a8-b23e-dbf6e34f4512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555201977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1555201977
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3900925494
Short name T722
Test name
Test status
Simulation time 6090086411 ps
CPU time 1.71 seconds
Started Jul 03 06:59:51 PM PDT 24
Finished Jul 03 06:59:53 PM PDT 24
Peak memory 201676 kb
Host smart-b48c14ef-a1e4-481c-b44e-cd67e74c99f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900925494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3900925494
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3602160032
Short name T419
Test name
Test status
Simulation time 9289121424 ps
CPU time 21.56 seconds
Started Jul 03 07:00:05 PM PDT 24
Finished Jul 03 07:00:27 PM PDT 24
Peak memory 201712 kb
Host smart-d1887847-316d-4928-bba9-91c4b3144b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602160032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3602160032
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.959227757
Short name T773
Test name
Test status
Simulation time 66405837876 ps
CPU time 144.23 seconds
Started Jul 03 07:00:07 PM PDT 24
Finished Jul 03 07:02:31 PM PDT 24
Peak memory 210628 kb
Host smart-5d1a2524-86ae-4f78-95ee-412f35e76f24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959227757 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.959227757
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2794971515
Short name T383
Test name
Test status
Simulation time 319588990 ps
CPU time 0.77 seconds
Started Jul 03 07:00:24 PM PDT 24
Finished Jul 03 07:00:26 PM PDT 24
Peak memory 201664 kb
Host smart-c0549324-b6e6-48b0-9b99-35b586fc73db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794971515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2794971515
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.4031123025
Short name T186
Test name
Test status
Simulation time 527031240536 ps
CPU time 65.99 seconds
Started Jul 03 07:00:15 PM PDT 24
Finished Jul 03 07:01:21 PM PDT 24
Peak memory 201916 kb
Host smart-aaf9410b-7bd9-474e-b890-5306ea9f53af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031123025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.4031123025
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3647605845
Short name T504
Test name
Test status
Simulation time 171014593070 ps
CPU time 210.6 seconds
Started Jul 03 07:00:17 PM PDT 24
Finished Jul 03 07:03:48 PM PDT 24
Peak memory 201984 kb
Host smart-c73f91b0-43f9-4d0d-983a-9eec9a7bf13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647605845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3647605845
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1417826125
Short name T655
Test name
Test status
Simulation time 164240659220 ps
CPU time 58.31 seconds
Started Jul 03 07:00:10 PM PDT 24
Finished Jul 03 07:01:09 PM PDT 24
Peak memory 201880 kb
Host smart-7a680f84-1b79-44b7-9412-4ad9ac1f3385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417826125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1417826125
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.41022811
Short name T590
Test name
Test status
Simulation time 162876848112 ps
CPU time 184.58 seconds
Started Jul 03 07:00:16 PM PDT 24
Finished Jul 03 07:03:21 PM PDT 24
Peak memory 201920 kb
Host smart-5d520af9-b528-440f-9a48-f2ed5c131038
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=41022811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt
_fixed.41022811
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.710776672
Short name T279
Test name
Test status
Simulation time 488563562093 ps
CPU time 544.67 seconds
Started Jul 03 07:00:10 PM PDT 24
Finished Jul 03 07:09:15 PM PDT 24
Peak memory 201880 kb
Host smart-4533e239-6dde-405a-863c-74703adfe710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710776672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.710776672
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1554184589
Short name T584
Test name
Test status
Simulation time 332018987586 ps
CPU time 212.78 seconds
Started Jul 03 07:00:11 PM PDT 24
Finished Jul 03 07:03:44 PM PDT 24
Peak memory 201944 kb
Host smart-518c1937-ed5e-4379-9ce0-5bb8721d72e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554184589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1554184589
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1057773422
Short name T53
Test name
Test status
Simulation time 574338964077 ps
CPU time 1203.1 seconds
Started Jul 03 07:00:15 PM PDT 24
Finished Jul 03 07:20:19 PM PDT 24
Peak memory 201948 kb
Host smart-1901aed0-7271-4413-8bd1-da7efd1f59ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057773422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1057773422
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3439131531
Short name T752
Test name
Test status
Simulation time 197925310088 ps
CPU time 105.74 seconds
Started Jul 03 07:00:14 PM PDT 24
Finished Jul 03 07:02:00 PM PDT 24
Peak memory 201904 kb
Host smart-d60f0b18-5e10-44e5-b67e-fceefe756b3e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439131531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3439131531
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3573520709
Short name T445
Test name
Test status
Simulation time 62132423970 ps
CPU time 244.08 seconds
Started Jul 03 07:00:23 PM PDT 24
Finished Jul 03 07:04:27 PM PDT 24
Peak memory 202184 kb
Host smart-de2959dc-4d12-449f-9ddb-911102fde540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573520709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3573520709
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3684359729
Short name T424
Test name
Test status
Simulation time 47984828543 ps
CPU time 57.74 seconds
Started Jul 03 07:00:25 PM PDT 24
Finished Jul 03 07:01:23 PM PDT 24
Peak memory 201688 kb
Host smart-f036e3f1-562f-4d96-b3a1-34aa0829391f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684359729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3684359729
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.37736028
Short name T164
Test name
Test status
Simulation time 4638631434 ps
CPU time 8.32 seconds
Started Jul 03 07:00:14 PM PDT 24
Finished Jul 03 07:00:23 PM PDT 24
Peak memory 201700 kb
Host smart-1cf7add9-8f02-4a80-8467-08eafc2efe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37736028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.37736028
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.22923116
Short name T348
Test name
Test status
Simulation time 5871348803 ps
CPU time 14.23 seconds
Started Jul 03 07:00:10 PM PDT 24
Finished Jul 03 07:00:24 PM PDT 24
Peak memory 201724 kb
Host smart-a3b465d2-13fb-4676-82b1-901aa0685360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22923116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.22923116
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3394021444
Short name T157
Test name
Test status
Simulation time 2414478301238 ps
CPU time 3012.13 seconds
Started Jul 03 07:00:24 PM PDT 24
Finished Jul 03 07:50:37 PM PDT 24
Peak memory 210376 kb
Host smart-40d91a6e-c3cf-4af8-8341-49ed906a3325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394021444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3394021444
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3428526713
Short name T431
Test name
Test status
Simulation time 19308551850 ps
CPU time 95.96 seconds
Started Jul 03 07:00:23 PM PDT 24
Finished Jul 03 07:02:00 PM PDT 24
Peak memory 210512 kb
Host smart-d7e45e43-d15b-4a00-b784-a86db9009de5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428526713 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3428526713
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2742523977
Short name T417
Test name
Test status
Simulation time 427110504 ps
CPU time 0.78 seconds
Started Jul 03 07:04:35 PM PDT 24
Finished Jul 03 07:04:37 PM PDT 24
Peak memory 201668 kb
Host smart-3a98ab69-d3f3-40b9-a5a5-b9149273d8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742523977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2742523977
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1758436433
Short name T282
Test name
Test status
Simulation time 204913836882 ps
CPU time 476.53 seconds
Started Jul 03 07:04:37 PM PDT 24
Finished Jul 03 07:12:35 PM PDT 24
Peak memory 201964 kb
Host smart-3949fc9a-e3a6-4b06-bb45-14b6f5cdf6b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758436433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1758436433
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3675442500
Short name T267
Test name
Test status
Simulation time 188464556054 ps
CPU time 233.98 seconds
Started Jul 03 07:04:34 PM PDT 24
Finished Jul 03 07:08:29 PM PDT 24
Peak memory 201928 kb
Host smart-7354b8d4-1811-4451-a24c-d87f27bdc03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675442500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3675442500
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1186905909
Short name T90
Test name
Test status
Simulation time 326275077969 ps
CPU time 186.44 seconds
Started Jul 03 07:04:36 PM PDT 24
Finished Jul 03 07:07:44 PM PDT 24
Peak memory 201988 kb
Host smart-71deb2fa-82c1-44b7-9de2-c93352b9cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186905909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1186905909
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3977758803
Short name T361
Test name
Test status
Simulation time 320677904603 ps
CPU time 193.51 seconds
Started Jul 03 07:04:35 PM PDT 24
Finished Jul 03 07:07:49 PM PDT 24
Peak memory 201908 kb
Host smart-630dd52c-93ec-495c-ba73-e37cb9c1828e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977758803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3977758803
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1090820319
Short name T465
Test name
Test status
Simulation time 335921646584 ps
CPU time 71.4 seconds
Started Jul 03 07:04:37 PM PDT 24
Finished Jul 03 07:05:50 PM PDT 24
Peak memory 201908 kb
Host smart-8c098673-03db-4986-9651-d44052f0ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090820319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1090820319
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.288986399
Short name T521
Test name
Test status
Simulation time 493633947694 ps
CPU time 1102.58 seconds
Started Jul 03 07:04:39 PM PDT 24
Finished Jul 03 07:23:02 PM PDT 24
Peak memory 201900 kb
Host smart-e5d12483-51e5-47f0-a6b7-abe9fd2e92b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288986399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.288986399
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.229287111
Short name T52
Test name
Test status
Simulation time 338447820357 ps
CPU time 108.28 seconds
Started Jul 03 07:04:35 PM PDT 24
Finished Jul 03 07:06:24 PM PDT 24
Peak memory 201948 kb
Host smart-a1033a63-52e0-4a20-9a51-d29e014b3b2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229287111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.229287111
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3962690730
Short name T444
Test name
Test status
Simulation time 614874258725 ps
CPU time 270.37 seconds
Started Jul 03 07:04:36 PM PDT 24
Finished Jul 03 07:09:07 PM PDT 24
Peak memory 201800 kb
Host smart-b7b807d6-228c-46f9-8c26-ee384f90a8c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962690730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3962690730
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.368256648
Short name T396
Test name
Test status
Simulation time 41385708464 ps
CPU time 85.77 seconds
Started Jul 03 07:04:34 PM PDT 24
Finished Jul 03 07:06:01 PM PDT 24
Peak memory 201708 kb
Host smart-03b346fb-37de-49ba-8734-db9316505063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368256648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.368256648
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.573920836
Short name T721
Test name
Test status
Simulation time 4678872118 ps
CPU time 1.86 seconds
Started Jul 03 07:04:33 PM PDT 24
Finished Jul 03 07:04:35 PM PDT 24
Peak memory 201724 kb
Host smart-b092471e-4933-4a22-b4e2-3cd8c291c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573920836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.573920836
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.842289131
Short name T581
Test name
Test status
Simulation time 5590214482 ps
CPU time 14.09 seconds
Started Jul 03 07:00:26 PM PDT 24
Finished Jul 03 07:00:41 PM PDT 24
Peak memory 201736 kb
Host smart-492f1533-e5fb-44ad-8f28-332605a0dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842289131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.842289131
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2210651457
Short name T45
Test name
Test status
Simulation time 60607289586 ps
CPU time 140.56 seconds
Started Jul 03 07:04:35 PM PDT 24
Finished Jul 03 07:06:56 PM PDT 24
Peak memory 210760 kb
Host smart-505e2bb2-faf0-4c75-9a14-950506c01cb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210651457 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2210651457
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.748331272
Short name T524
Test name
Test status
Simulation time 404353414 ps
CPU time 1.44 seconds
Started Jul 03 07:04:39 PM PDT 24
Finished Jul 03 07:04:42 PM PDT 24
Peak memory 201652 kb
Host smart-874966ed-0dfb-4d69-8e74-7019a2756325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748331272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.748331272
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3960834897
Short name T771
Test name
Test status
Simulation time 170378349758 ps
CPU time 109.01 seconds
Started Jul 03 07:04:38 PM PDT 24
Finished Jul 03 07:06:28 PM PDT 24
Peak memory 201980 kb
Host smart-4d4a5adb-2309-41c1-88dd-9173d2e68424
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960834897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3960834897
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.852064923
Short name T265
Test name
Test status
Simulation time 163165077320 ps
CPU time 93.61 seconds
Started Jul 03 07:04:39 PM PDT 24
Finished Jul 03 07:06:13 PM PDT 24
Peak memory 201984 kb
Host smart-3f758d1b-b592-4b42-a8d6-e5dd15a63387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852064923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.852064923
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.253148594
Short name T331
Test name
Test status
Simulation time 320104204088 ps
CPU time 761.88 seconds
Started Jul 03 07:04:40 PM PDT 24
Finished Jul 03 07:17:24 PM PDT 24
Peak memory 201912 kb
Host smart-0c627ce4-1292-4572-bd09-f903374568c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253148594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.253148594
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.213904684
Short name T422
Test name
Test status
Simulation time 488555850007 ps
CPU time 1159.18 seconds
Started Jul 03 07:04:39 PM PDT 24
Finished Jul 03 07:24:00 PM PDT 24
Peak memory 201884 kb
Host smart-98bba3a8-e1cc-4383-9a1d-d3fd59dd0d22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=213904684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.213904684
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1413778144
Short name T143
Test name
Test status
Simulation time 494098412007 ps
CPU time 321.3 seconds
Started Jul 03 07:04:37 PM PDT 24
Finished Jul 03 07:10:00 PM PDT 24
Peak memory 201908 kb
Host smart-b238cfd6-38ce-4a7f-a7c6-4dbb4d427c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413778144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1413778144
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1603930135
Short name T379
Test name
Test status
Simulation time 164085627125 ps
CPU time 394.27 seconds
Started Jul 03 07:04:40 PM PDT 24
Finished Jul 03 07:11:16 PM PDT 24
Peak memory 201892 kb
Host smart-e85e389d-8452-4367-858a-0dc7c03db1b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603930135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1603930135
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4008111915
Short name T785
Test name
Test status
Simulation time 380475596620 ps
CPU time 207.96 seconds
Started Jul 03 07:04:39 PM PDT 24
Finished Jul 03 07:08:09 PM PDT 24
Peak memory 201908 kb
Host smart-f034293b-d52e-449b-a625-605142e15957
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008111915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4008111915
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4069739947
Short name T199
Test name
Test status
Simulation time 122159937255 ps
CPU time 620.09 seconds
Started Jul 03 07:04:38 PM PDT 24
Finished Jul 03 07:14:59 PM PDT 24
Peak memory 202188 kb
Host smart-387440b4-1e01-4cfd-8177-560c870dd676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069739947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4069739947
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1406795243
Short name T791
Test name
Test status
Simulation time 27047739373 ps
CPU time 59.92 seconds
Started Jul 03 07:04:38 PM PDT 24
Finished Jul 03 07:05:39 PM PDT 24
Peak memory 201668 kb
Host smart-da83622e-d093-4f38-a66d-6ae808a8ab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406795243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1406795243
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1837491381
Short name T798
Test name
Test status
Simulation time 3383685230 ps
CPU time 2.68 seconds
Started Jul 03 07:04:40 PM PDT 24
Finished Jul 03 07:04:44 PM PDT 24
Peak memory 201696 kb
Host smart-3c7ac3fb-886a-4097-8011-863c901e1877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837491381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1837491381
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1646895400
Short name T737
Test name
Test status
Simulation time 5976952186 ps
CPU time 13.99 seconds
Started Jul 03 07:04:35 PM PDT 24
Finished Jul 03 07:04:50 PM PDT 24
Peak memory 201740 kb
Host smart-2470543a-bccb-41f1-8f52-37cfa8e4211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646895400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1646895400
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3732328678
Short name T530
Test name
Test status
Simulation time 511437677584 ps
CPU time 974.76 seconds
Started Jul 03 07:04:40 PM PDT 24
Finished Jul 03 07:20:56 PM PDT 24
Peak memory 210380 kb
Host smart-3567fd50-3b04-46f9-a44d-0d955bd8cdb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732328678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3732328678
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2147132906
Short name T457
Test name
Test status
Simulation time 37469337232 ps
CPU time 46.59 seconds
Started Jul 03 07:04:39 PM PDT 24
Finished Jul 03 07:05:27 PM PDT 24
Peak memory 202024 kb
Host smart-a7c763bf-dec5-4fb2-bde0-45c43c9b8334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147132906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2147132906
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.167539017
Short name T557
Test name
Test status
Simulation time 417155634 ps
CPU time 1.57 seconds
Started Jul 03 06:51:44 PM PDT 24
Finished Jul 03 06:51:46 PM PDT 24
Peak memory 201668 kb
Host smart-f60ae4ab-2712-4ce7-a196-1fec319cc65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167539017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.167539017
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1479098726
Short name T548
Test name
Test status
Simulation time 175945086305 ps
CPU time 103.69 seconds
Started Jul 03 06:51:35 PM PDT 24
Finished Jul 03 06:53:19 PM PDT 24
Peak memory 201912 kb
Host smart-0a66e3a5-d516-47ad-bf2b-858860c817af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479098726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1479098726
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2022256587
Short name T234
Test name
Test status
Simulation time 498361024256 ps
CPU time 553.58 seconds
Started Jul 03 06:51:39 PM PDT 24
Finished Jul 03 07:00:53 PM PDT 24
Peak memory 201912 kb
Host smart-3dc2c5fb-8838-4e30-bbd7-034073c8bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022256587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2022256587
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1591613302
Short name T95
Test name
Test status
Simulation time 321598577598 ps
CPU time 766.83 seconds
Started Jul 03 06:51:25 PM PDT 24
Finished Jul 03 07:04:12 PM PDT 24
Peak memory 201888 kb
Host smart-11a8b6f9-f616-42eb-a3de-25338a719724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591613302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1591613302
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3075279100
Short name T619
Test name
Test status
Simulation time 159887470401 ps
CPU time 366.19 seconds
Started Jul 03 06:51:24 PM PDT 24
Finished Jul 03 06:57:31 PM PDT 24
Peak memory 201916 kb
Host smart-f51d86d1-e2a6-4bf5-ae93-830955cf0b19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075279100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3075279100
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1836513588
Short name T148
Test name
Test status
Simulation time 495579631579 ps
CPU time 570.23 seconds
Started Jul 03 06:51:25 PM PDT 24
Finished Jul 03 07:00:56 PM PDT 24
Peak memory 201932 kb
Host smart-9fa40816-79d7-4afb-911a-0262db595bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836513588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1836513588
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1079856477
Short name T651
Test name
Test status
Simulation time 330224608027 ps
CPU time 706.22 seconds
Started Jul 03 06:51:28 PM PDT 24
Finished Jul 03 07:03:15 PM PDT 24
Peak memory 201876 kb
Host smart-de079160-61ce-403a-b753-0f7c9d6f7f8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079856477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1079856477
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.200153
Short name T636
Test name
Test status
Simulation time 520060390342 ps
CPU time 308.38 seconds
Started Jul 03 06:51:28 PM PDT 24
Finished Jul 03 06:56:37 PM PDT 24
Peak memory 201808 kb
Host smart-1a44190d-a128-4883-ad88-8af92041b723
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_wa
keup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_wake
up.200153
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1775063918
Short name T742
Test name
Test status
Simulation time 624891673000 ps
CPU time 749.52 seconds
Started Jul 03 06:51:35 PM PDT 24
Finished Jul 03 07:04:05 PM PDT 24
Peak memory 201920 kb
Host smart-6a08c787-a8de-468d-8e31-791208d27aab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775063918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1775063918
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1246135260
Short name T667
Test name
Test status
Simulation time 134396998915 ps
CPU time 599.35 seconds
Started Jul 03 06:51:38 PM PDT 24
Finished Jul 03 07:01:38 PM PDT 24
Peak memory 202284 kb
Host smart-72746a51-9876-4b57-bc24-df2ff2eba571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246135260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1246135260
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2509057388
Short name T549
Test name
Test status
Simulation time 37954775139 ps
CPU time 22.62 seconds
Started Jul 03 06:51:39 PM PDT 24
Finished Jul 03 06:52:02 PM PDT 24
Peak memory 201724 kb
Host smart-78c05051-7767-41e5-a212-b97a754d092b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509057388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2509057388
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.650435895
Short name T654
Test name
Test status
Simulation time 4806205731 ps
CPU time 3.36 seconds
Started Jul 03 06:51:40 PM PDT 24
Finished Jul 03 06:51:43 PM PDT 24
Peak memory 201736 kb
Host smart-ad045835-7072-4126-8bd4-885679d5e45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650435895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.650435895
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3700545339
Short name T69
Test name
Test status
Simulation time 4611480906 ps
CPU time 3.2 seconds
Started Jul 03 06:51:44 PM PDT 24
Finished Jul 03 06:51:48 PM PDT 24
Peak memory 217180 kb
Host smart-84ffe794-8a10-4281-a4e8-27da9370d156
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700545339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3700545339
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.62931463
Short name T604
Test name
Test status
Simulation time 5927481069 ps
CPU time 1.54 seconds
Started Jul 03 06:51:25 PM PDT 24
Finished Jul 03 06:51:27 PM PDT 24
Peak memory 201728 kb
Host smart-f79cb766-164a-4c2d-bcc5-3d486b89bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62931463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.62931463
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2524806331
Short name T296
Test name
Test status
Simulation time 518890275441 ps
CPU time 363.42 seconds
Started Jul 03 06:51:44 PM PDT 24
Finished Jul 03 06:57:48 PM PDT 24
Peak memory 201928 kb
Host smart-d067684b-c503-4008-ab75-736648bcc214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524806331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2524806331
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1720013703
Short name T649
Test name
Test status
Simulation time 310852198 ps
CPU time 1.37 seconds
Started Jul 03 07:04:44 PM PDT 24
Finished Jul 03 07:04:46 PM PDT 24
Peak memory 201680 kb
Host smart-27c3689c-f184-4ee3-aa97-07a6d8c02ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720013703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1720013703
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3705970432
Short name T96
Test name
Test status
Simulation time 164301113143 ps
CPU time 99.8 seconds
Started Jul 03 07:04:42 PM PDT 24
Finished Jul 03 07:06:23 PM PDT 24
Peak memory 202008 kb
Host smart-bc8b8a02-dc33-4dd2-baad-d8ec9e06097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705970432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3705970432
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.753230055
Short name T30
Test name
Test status
Simulation time 495379033442 ps
CPU time 266.54 seconds
Started Jul 03 07:04:42 PM PDT 24
Finished Jul 03 07:09:10 PM PDT 24
Peak memory 201864 kb
Host smart-b0199984-52c7-42aa-bdc1-76445f026267
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=753230055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.753230055
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2486335956
Short name T253
Test name
Test status
Simulation time 334863987943 ps
CPU time 187.52 seconds
Started Jul 03 07:04:45 PM PDT 24
Finished Jul 03 07:07:54 PM PDT 24
Peak memory 201920 kb
Host smart-1e7383f4-44e6-4274-80e1-6f4c597fca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486335956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2486335956
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1507569954
Short name T490
Test name
Test status
Simulation time 323478511143 ps
CPU time 575.32 seconds
Started Jul 03 07:04:44 PM PDT 24
Finished Jul 03 07:14:20 PM PDT 24
Peak memory 201812 kb
Host smart-4f6a288d-2ce5-439c-9a1d-f57af8f5ab44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507569954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1507569954
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2783642743
Short name T716
Test name
Test status
Simulation time 529503870489 ps
CPU time 279.95 seconds
Started Jul 03 07:04:44 PM PDT 24
Finished Jul 03 07:09:25 PM PDT 24
Peak memory 201932 kb
Host smart-9875b3b0-f74d-4cab-aae5-5d718adf1e28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783642743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2783642743
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1532723349
Short name T588
Test name
Test status
Simulation time 400294030119 ps
CPU time 213.45 seconds
Started Jul 03 07:04:47 PM PDT 24
Finished Jul 03 07:08:22 PM PDT 24
Peak memory 201912 kb
Host smart-f7a46099-6ae0-48d8-bcab-3349e5dcdc2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532723349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1532723349
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.561008079
Short name T58
Test name
Test status
Simulation time 80797749559 ps
CPU time 294.06 seconds
Started Jul 03 07:04:45 PM PDT 24
Finished Jul 03 07:09:40 PM PDT 24
Peak memory 202268 kb
Host smart-a461369e-3fc1-4ed1-87c8-6086eec58a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561008079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.561008079
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3594892583
Short name T526
Test name
Test status
Simulation time 47222777625 ps
CPU time 53.72 seconds
Started Jul 03 07:04:46 PM PDT 24
Finished Jul 03 07:05:41 PM PDT 24
Peak memory 201732 kb
Host smart-96d325d1-cb38-4c46-a766-218108d6f70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594892583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3594892583
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1769575212
Short name T544
Test name
Test status
Simulation time 3447692476 ps
CPU time 3.79 seconds
Started Jul 03 07:04:42 PM PDT 24
Finished Jul 03 07:04:47 PM PDT 24
Peak memory 201732 kb
Host smart-0292bae8-321d-4520-a116-4d5d3f604049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769575212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1769575212
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3128908183
Short name T577
Test name
Test status
Simulation time 5775595256 ps
CPU time 3.91 seconds
Started Jul 03 07:04:40 PM PDT 24
Finished Jul 03 07:04:45 PM PDT 24
Peak memory 201732 kb
Host smart-c72ad5c6-4cda-4d45-a1e7-9bbd520da005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128908183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3128908183
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2752183401
Short name T795
Test name
Test status
Simulation time 47696663292 ps
CPU time 115.02 seconds
Started Jul 03 07:04:48 PM PDT 24
Finished Jul 03 07:06:44 PM PDT 24
Peak memory 201720 kb
Host smart-53414e59-8d25-499a-a2da-384cc3100440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752183401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2752183401
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1269706375
Short name T299
Test name
Test status
Simulation time 424563064407 ps
CPU time 302.99 seconds
Started Jul 03 07:04:47 PM PDT 24
Finished Jul 03 07:09:51 PM PDT 24
Peak memory 210552 kb
Host smart-5e1a0966-e9e9-4682-ab12-f5194239b597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269706375 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1269706375
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.4233133197
Short name T14
Test name
Test status
Simulation time 426574876 ps
CPU time 1.65 seconds
Started Jul 03 07:04:53 PM PDT 24
Finished Jul 03 07:04:55 PM PDT 24
Peak memory 201652 kb
Host smart-64c436f5-b152-433b-a18c-b463e6808776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233133197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.4233133197
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4273116181
Short name T587
Test name
Test status
Simulation time 331628334509 ps
CPU time 716.56 seconds
Started Jul 03 07:04:49 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 201920 kb
Host smart-f9247de0-0d7c-4f02-8dbf-06ea53aeb675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273116181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4273116181
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3633560324
Short name T612
Test name
Test status
Simulation time 327167051963 ps
CPU time 722.5 seconds
Started Jul 03 07:04:50 PM PDT 24
Finished Jul 03 07:16:54 PM PDT 24
Peak memory 201884 kb
Host smart-6ca7711b-b49c-4f68-a468-374c9e748a0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633560324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3633560324
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.548546936
Short name T307
Test name
Test status
Simulation time 329843601430 ps
CPU time 728.65 seconds
Started Jul 03 07:04:54 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 201980 kb
Host smart-6392ef96-89a2-471d-8cfb-ab98126e487c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548546936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.548546936
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2859880207
Short name T420
Test name
Test status
Simulation time 318776777292 ps
CPU time 147.85 seconds
Started Jul 03 07:04:50 PM PDT 24
Finished Jul 03 07:07:19 PM PDT 24
Peak memory 201928 kb
Host smart-4c96fb33-5697-4675-bbdb-ed5ff82de4a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859880207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2859880207
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.4165815883
Short name T729
Test name
Test status
Simulation time 348808491009 ps
CPU time 422.79 seconds
Started Jul 03 07:04:50 PM PDT 24
Finished Jul 03 07:11:54 PM PDT 24
Peak memory 201940 kb
Host smart-cfb8a7b4-f9a9-4ae9-8b9a-a3483d43a34a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165815883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.4165815883
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3460712625
Short name T459
Test name
Test status
Simulation time 197673358942 ps
CPU time 453.39 seconds
Started Jul 03 07:04:49 PM PDT 24
Finished Jul 03 07:12:23 PM PDT 24
Peak memory 201872 kb
Host smart-74b5a67a-a313-4c3f-9646-8f28ca11272f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460712625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3460712625
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2969543317
Short name T790
Test name
Test status
Simulation time 105307200265 ps
CPU time 339.55 seconds
Started Jul 03 07:04:56 PM PDT 24
Finished Jul 03 07:10:37 PM PDT 24
Peak memory 202204 kb
Host smart-c6721fa5-8556-458d-8f05-caf8a43d4416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969543317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2969543317
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2399456939
Short name T676
Test name
Test status
Simulation time 36450288406 ps
CPU time 9.71 seconds
Started Jul 03 07:04:52 PM PDT 24
Finished Jul 03 07:05:03 PM PDT 24
Peak memory 201672 kb
Host smart-0e586db2-697b-452a-bfcc-191b97940888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399456939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2399456939
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.322173088
Short name T478
Test name
Test status
Simulation time 4983643272 ps
CPU time 11.72 seconds
Started Jul 03 07:04:48 PM PDT 24
Finished Jul 03 07:05:00 PM PDT 24
Peak memory 201736 kb
Host smart-2eefbeb7-4bf4-45c6-a0e9-9c7724bdcc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322173088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.322173088
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.807803108
Short name T488
Test name
Test status
Simulation time 5870403458 ps
CPU time 1.77 seconds
Started Jul 03 07:04:48 PM PDT 24
Finished Jul 03 07:04:51 PM PDT 24
Peak memory 201736 kb
Host smart-28fcaacb-194c-4406-ab6f-89c3fb638984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807803108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.807803108
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.64823540
Short name T594
Test name
Test status
Simulation time 226873873771 ps
CPU time 1140.39 seconds
Started Jul 03 07:04:54 PM PDT 24
Finished Jul 03 07:23:56 PM PDT 24
Peak memory 202204 kb
Host smart-547377fe-3d68-40ad-b353-bda2d4ba930d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64823540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.64823540
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.205478352
Short name T506
Test name
Test status
Simulation time 37651375563 ps
CPU time 43.82 seconds
Started Jul 03 07:04:54 PM PDT 24
Finished Jul 03 07:05:39 PM PDT 24
Peak memory 210248 kb
Host smart-ea986ed2-4bdb-442a-8fd7-47ee251009dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205478352 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.205478352
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2460636504
Short name T477
Test name
Test status
Simulation time 363919948 ps
CPU time 0.89 seconds
Started Jul 03 07:05:01 PM PDT 24
Finished Jul 03 07:05:04 PM PDT 24
Peak memory 201596 kb
Host smart-1d9d0f7b-1173-4625-af7e-338ae9576af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460636504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2460636504
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2396216267
Short name T672
Test name
Test status
Simulation time 171691930267 ps
CPU time 103.91 seconds
Started Jul 03 07:04:54 PM PDT 24
Finished Jul 03 07:06:40 PM PDT 24
Peak memory 201916 kb
Host smart-1d0237dd-5ff7-4446-979a-2038889c7f59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396216267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2396216267
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3404547245
Short name T774
Test name
Test status
Simulation time 329552272454 ps
CPU time 184.21 seconds
Started Jul 03 07:04:56 PM PDT 24
Finished Jul 03 07:08:02 PM PDT 24
Peak memory 201884 kb
Host smart-ff8e9e13-6075-4d13-acd8-e8d744c8aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404547245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3404547245
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.967834908
Short name T3
Test name
Test status
Simulation time 164610152372 ps
CPU time 99.72 seconds
Started Jul 03 07:04:52 PM PDT 24
Finished Jul 03 07:06:33 PM PDT 24
Peak memory 201928 kb
Host smart-66a887a3-2235-4fb8-b7fc-d9a795301e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967834908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.967834908
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.985502224
Short name T416
Test name
Test status
Simulation time 494927377940 ps
CPU time 523.99 seconds
Started Jul 03 07:04:55 PM PDT 24
Finished Jul 03 07:13:41 PM PDT 24
Peak memory 201980 kb
Host smart-5f5c3834-fbac-41dc-96ff-3fde300f677c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=985502224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.985502224
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.962638157
Short name T255
Test name
Test status
Simulation time 327057602030 ps
CPU time 383.19 seconds
Started Jul 03 07:04:55 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 201968 kb
Host smart-2c08747a-5f4c-4115-8719-7fd34ab1ac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962638157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.962638157
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3523366889
Short name T464
Test name
Test status
Simulation time 161513002868 ps
CPU time 339.25 seconds
Started Jul 03 07:04:56 PM PDT 24
Finished Jul 03 07:10:38 PM PDT 24
Peak memory 201944 kb
Host smart-9837e2e8-d9d4-4772-ac1d-a50dbe25a8bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523366889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3523366889
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1899224678
Short name T191
Test name
Test status
Simulation time 588398116664 ps
CPU time 332.74 seconds
Started Jul 03 07:04:57 PM PDT 24
Finished Jul 03 07:10:31 PM PDT 24
Peak memory 201964 kb
Host smart-b1e1629a-c3a6-4462-a835-27c871dae8ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899224678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1899224678
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4027482511
Short name T108
Test name
Test status
Simulation time 202429319148 ps
CPU time 436.85 seconds
Started Jul 03 07:04:54 PM PDT 24
Finished Jul 03 07:12:12 PM PDT 24
Peak memory 201920 kb
Host smart-f1d69497-4416-45ba-a1a0-45404f9ccc9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027482511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4027482511
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3718498161
Short name T643
Test name
Test status
Simulation time 100063198159 ps
CPU time 423.4 seconds
Started Jul 03 07:05:02 PM PDT 24
Finished Jul 03 07:12:07 PM PDT 24
Peak memory 202204 kb
Host smart-0f898fac-999d-4e30-89da-4e8f3ee9403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718498161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3718498161
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3937554922
Short name T397
Test name
Test status
Simulation time 35311664852 ps
CPU time 39.67 seconds
Started Jul 03 07:05:00 PM PDT 24
Finished Jul 03 07:05:41 PM PDT 24
Peak memory 201684 kb
Host smart-b43c180e-23f0-4c4a-835a-687665bb3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937554922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3937554922
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4234673232
Short name T620
Test name
Test status
Simulation time 2803064926 ps
CPU time 7.82 seconds
Started Jul 03 07:05:00 PM PDT 24
Finished Jul 03 07:05:09 PM PDT 24
Peak memory 201720 kb
Host smart-0bea826e-0064-4c36-939d-994641b0e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234673232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4234673232
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1846618424
Short name T627
Test name
Test status
Simulation time 5778630262 ps
CPU time 3.92 seconds
Started Jul 03 07:04:53 PM PDT 24
Finished Jul 03 07:04:58 PM PDT 24
Peak memory 201732 kb
Host smart-0691be38-62a8-46f3-8e39-81a6ef92b3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846618424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1846618424
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2602567401
Short name T754
Test name
Test status
Simulation time 340555733619 ps
CPU time 198.19 seconds
Started Jul 03 07:05:01 PM PDT 24
Finished Jul 03 07:08:21 PM PDT 24
Peak memory 201844 kb
Host smart-cb904fa7-717f-4782-8eb8-8c4cfb61a86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602567401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2602567401
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3416160638
Short name T328
Test name
Test status
Simulation time 42947563499 ps
CPU time 99.63 seconds
Started Jul 03 07:04:57 PM PDT 24
Finished Jul 03 07:06:38 PM PDT 24
Peak memory 202048 kb
Host smart-f6be3828-6692-446a-9599-99b681434cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416160638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3416160638
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3927026190
Short name T598
Test name
Test status
Simulation time 315915794 ps
CPU time 1 seconds
Started Jul 03 07:05:10 PM PDT 24
Finished Jul 03 07:05:12 PM PDT 24
Peak memory 201660 kb
Host smart-e34d87df-5049-4166-ae1c-04c711d354d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927026190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3927026190
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2226938158
Short name T770
Test name
Test status
Simulation time 330172317715 ps
CPU time 195.4 seconds
Started Jul 03 07:05:06 PM PDT 24
Finished Jul 03 07:08:22 PM PDT 24
Peak memory 201900 kb
Host smart-2655d3b1-fbde-40de-a80a-5c1149e8a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226938158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2226938158
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2359849841
Short name T529
Test name
Test status
Simulation time 479723125426 ps
CPU time 297.59 seconds
Started Jul 03 07:05:03 PM PDT 24
Finished Jul 03 07:10:02 PM PDT 24
Peak memory 201864 kb
Host smart-1bbcd6f8-f197-46d4-9ca3-cb3172123ac6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359849841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2359849841
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.316317727
Short name T263
Test name
Test status
Simulation time 322440082815 ps
CPU time 669.48 seconds
Started Jul 03 07:05:05 PM PDT 24
Finished Jul 03 07:16:16 PM PDT 24
Peak memory 201964 kb
Host smart-88266e78-46d4-4fe7-aad0-d5e885ad7f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316317727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.316317727
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3103502084
Short name T678
Test name
Test status
Simulation time 325574492905 ps
CPU time 771.04 seconds
Started Jul 03 07:05:03 PM PDT 24
Finished Jul 03 07:17:55 PM PDT 24
Peak memory 202000 kb
Host smart-dd1b6307-c51b-4576-a21f-3666c819e36d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103502084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3103502084
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1583052510
Short name T294
Test name
Test status
Simulation time 370066264539 ps
CPU time 209.82 seconds
Started Jul 03 07:05:04 PM PDT 24
Finished Jul 03 07:08:35 PM PDT 24
Peak memory 201920 kb
Host smart-3d424a2f-4d91-4ba6-9c2e-c7951b82b893
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583052510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1583052510
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1153913992
Short name T603
Test name
Test status
Simulation time 201820460201 ps
CPU time 454.11 seconds
Started Jul 03 07:05:05 PM PDT 24
Finished Jul 03 07:12:40 PM PDT 24
Peak memory 201916 kb
Host smart-674ee67b-a89e-4651-a4cb-d414dc8c6778
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153913992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1153913992
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2439166085
Short name T469
Test name
Test status
Simulation time 95287655169 ps
CPU time 339.99 seconds
Started Jul 03 07:05:04 PM PDT 24
Finished Jul 03 07:10:46 PM PDT 24
Peak memory 202204 kb
Host smart-ef287e2d-1fff-45c9-8b2d-d10aeababb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439166085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2439166085
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2514747059
Short name T625
Test name
Test status
Simulation time 25281073090 ps
CPU time 26.79 seconds
Started Jul 03 07:05:04 PM PDT 24
Finished Jul 03 07:05:32 PM PDT 24
Peak memory 201720 kb
Host smart-cd311988-593d-4886-a7d4-fc0b02f6f112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514747059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2514747059
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3945857751
Short name T553
Test name
Test status
Simulation time 4833930449 ps
CPU time 12.45 seconds
Started Jul 03 07:05:05 PM PDT 24
Finished Jul 03 07:05:19 PM PDT 24
Peak memory 201728 kb
Host smart-aba7d405-7fc1-44ca-bdb1-9804a8f25ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945857751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3945857751
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.705067874
Short name T535
Test name
Test status
Simulation time 5809226562 ps
CPU time 3.98 seconds
Started Jul 03 07:05:01 PM PDT 24
Finished Jul 03 07:05:07 PM PDT 24
Peak memory 201700 kb
Host smart-a57306f6-c99e-4303-921e-acf1d8669ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705067874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.705067874
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3061587581
Short name T666
Test name
Test status
Simulation time 253989618359 ps
CPU time 154.6 seconds
Started Jul 03 07:05:09 PM PDT 24
Finished Jul 03 07:07:44 PM PDT 24
Peak memory 201968 kb
Host smart-d16e29db-7a6f-4a3f-8306-62f51e82aa28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061587581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3061587581
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.988430589
Short name T295
Test name
Test status
Simulation time 87504773458 ps
CPU time 101.73 seconds
Started Jul 03 07:05:05 PM PDT 24
Finished Jul 03 07:06:48 PM PDT 24
Peak memory 210304 kb
Host smart-329cc050-a729-4923-a3f7-cc9b58aad794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988430589 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.988430589
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3635652097
Short name T792
Test name
Test status
Simulation time 490999085 ps
CPU time 1.13 seconds
Started Jul 03 07:05:14 PM PDT 24
Finished Jul 03 07:05:16 PM PDT 24
Peak memory 201576 kb
Host smart-af1fa5c0-ddeb-4b51-ac24-125ecaa31737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635652097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3635652097
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3242683454
Short name T330
Test name
Test status
Simulation time 367481133996 ps
CPU time 909.21 seconds
Started Jul 03 07:05:13 PM PDT 24
Finished Jul 03 07:20:23 PM PDT 24
Peak memory 201904 kb
Host smart-5769216f-1208-498a-bb54-94c2ef06283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242683454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3242683454
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4164446407
Short name T491
Test name
Test status
Simulation time 335240778174 ps
CPU time 773.93 seconds
Started Jul 03 07:05:08 PM PDT 24
Finished Jul 03 07:18:03 PM PDT 24
Peak memory 202012 kb
Host smart-b61fdca8-bcdf-48a6-b372-d7ebbd847c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164446407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4164446407
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1853036403
Short name T709
Test name
Test status
Simulation time 167873199588 ps
CPU time 394.13 seconds
Started Jul 03 07:05:08 PM PDT 24
Finished Jul 03 07:11:43 PM PDT 24
Peak memory 201880 kb
Host smart-6632908d-a7b2-4d08-be50-1d369d7c745a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853036403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1853036403
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1595484308
Short name T104
Test name
Test status
Simulation time 162286679119 ps
CPU time 188.75 seconds
Started Jul 03 07:05:09 PM PDT 24
Finished Jul 03 07:08:19 PM PDT 24
Peak memory 201844 kb
Host smart-d7420547-f266-4e42-88ad-8f02585c5378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595484308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1595484308
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2222110857
Short name T117
Test name
Test status
Simulation time 335047218230 ps
CPU time 382.13 seconds
Started Jul 03 07:05:08 PM PDT 24
Finished Jul 03 07:11:31 PM PDT 24
Peak memory 201992 kb
Host smart-cfc36523-83b2-4a1f-abf8-d71bc0a52a9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222110857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2222110857
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2756259905
Short name T310
Test name
Test status
Simulation time 450964203387 ps
CPU time 497.41 seconds
Started Jul 03 07:05:09 PM PDT 24
Finished Jul 03 07:13:27 PM PDT 24
Peak memory 201952 kb
Host smart-f1378396-d4d6-48fc-9072-ed7205637895
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756259905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2756259905
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4155246723
Short name T364
Test name
Test status
Simulation time 199890209926 ps
CPU time 235.74 seconds
Started Jul 03 07:05:13 PM PDT 24
Finished Jul 03 07:09:10 PM PDT 24
Peak memory 201884 kb
Host smart-773a0017-ebef-42ee-bb45-61a0145464dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155246723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4155246723
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1164881194
Short name T213
Test name
Test status
Simulation time 133480821988 ps
CPU time 437.52 seconds
Started Jul 03 07:05:15 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 202176 kb
Host smart-fc22fe88-5cfc-4964-a111-9cf0cc1c71f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164881194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1164881194
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1983995816
Short name T551
Test name
Test status
Simulation time 23098672196 ps
CPU time 9.3 seconds
Started Jul 03 07:05:15 PM PDT 24
Finished Jul 03 07:05:26 PM PDT 24
Peak memory 201684 kb
Host smart-d846a334-afee-401e-b37b-4901e8c88e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983995816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1983995816
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3967076488
Short name T568
Test name
Test status
Simulation time 3425870978 ps
CPU time 2.02 seconds
Started Jul 03 07:05:14 PM PDT 24
Finished Jul 03 07:05:18 PM PDT 24
Peak memory 201660 kb
Host smart-a0f523bb-7d40-450b-ac34-dc06d7e77d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967076488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3967076488
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4209755489
Short name T683
Test name
Test status
Simulation time 5676250991 ps
CPU time 13.32 seconds
Started Jul 03 07:05:11 PM PDT 24
Finished Jul 03 07:05:26 PM PDT 24
Peak memory 201708 kb
Host smart-0a76037a-9edb-42af-93ec-47eccc7609f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209755489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4209755489
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.179881839
Short name T270
Test name
Test status
Simulation time 170125379101 ps
CPU time 97.6 seconds
Started Jul 03 07:05:14 PM PDT 24
Finished Jul 03 07:06:53 PM PDT 24
Peak memory 201968 kb
Host smart-c1e5d674-4a4b-47d7-a7ff-f0c1433adb4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179881839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
179881839
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1012339889
Short name T316
Test name
Test status
Simulation time 132158308662 ps
CPU time 147.39 seconds
Started Jul 03 07:05:13 PM PDT 24
Finished Jul 03 07:07:42 PM PDT 24
Peak memory 210556 kb
Host smart-85b6c0b0-de2a-4102-aca8-e87c5c48db79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012339889 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1012339889
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3853165632
Short name T472
Test name
Test status
Simulation time 424832801 ps
CPU time 1.07 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:05:20 PM PDT 24
Peak memory 201656 kb
Host smart-6b99fc9b-9f8f-4b88-bb76-f1910e676c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853165632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3853165632
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.29599169
Short name T541
Test name
Test status
Simulation time 168292398947 ps
CPU time 357.97 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:11:18 PM PDT 24
Peak memory 201900 kb
Host smart-67b07249-6fc6-471c-8b2d-aa93f847b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29599169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.29599169
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3496227538
Short name T169
Test name
Test status
Simulation time 497451708114 ps
CPU time 1086.82 seconds
Started Jul 03 07:05:19 PM PDT 24
Finished Jul 03 07:23:28 PM PDT 24
Peak memory 201996 kb
Host smart-64a4e0d1-a4f3-4805-aa61-31fc0d17e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496227538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3496227538
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2748314143
Short name T751
Test name
Test status
Simulation time 326591547552 ps
CPU time 461.4 seconds
Started Jul 03 07:05:20 PM PDT 24
Finished Jul 03 07:13:03 PM PDT 24
Peak memory 201896 kb
Host smart-39778d03-8ccf-4c0b-be10-d600f02ee621
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748314143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2748314143
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4105943061
Short name T717
Test name
Test status
Simulation time 169252398312 ps
CPU time 374.49 seconds
Started Jul 03 07:05:13 PM PDT 24
Finished Jul 03 07:11:28 PM PDT 24
Peak memory 201892 kb
Host smart-40248a6a-586d-452f-aded-d1960774a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105943061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4105943061
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4206243491
Short name T453
Test name
Test status
Simulation time 164276370448 ps
CPU time 373.8 seconds
Started Jul 03 07:05:15 PM PDT 24
Finished Jul 03 07:11:30 PM PDT 24
Peak memory 201932 kb
Host smart-d6d84762-1d2b-4be3-bbad-57877a57a7a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206243491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4206243491
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3425622769
Short name T246
Test name
Test status
Simulation time 534971003510 ps
CPU time 1040.15 seconds
Started Jul 03 07:05:23 PM PDT 24
Finished Jul 03 07:22:44 PM PDT 24
Peak memory 201996 kb
Host smart-e136e0ae-475c-4d2d-a9be-71ba08d645fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425622769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3425622769
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3289415254
Short name T98
Test name
Test status
Simulation time 377474848582 ps
CPU time 214.33 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:08:54 PM PDT 24
Peak memory 201864 kb
Host smart-c4d8c0c6-a0bb-4432-9a92-648b3d8a6bbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289415254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3289415254
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.832979364
Short name T41
Test name
Test status
Simulation time 78502557990 ps
CPU time 266.21 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:09:47 PM PDT 24
Peak memory 202216 kb
Host smart-e7729810-ed6f-4ca8-9ccc-fa01d28da082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832979364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.832979364
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1139637518
Short name T430
Test name
Test status
Simulation time 37868834836 ps
CPU time 43.57 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:06:03 PM PDT 24
Peak memory 201728 kb
Host smart-34e06248-fa7c-4c92-a760-bd283f3f19c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139637518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1139637518
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3258052345
Short name T745
Test name
Test status
Simulation time 4357344751 ps
CPU time 6.33 seconds
Started Jul 03 07:05:21 PM PDT 24
Finished Jul 03 07:05:28 PM PDT 24
Peak memory 201736 kb
Host smart-c1dfa94a-54fb-4d45-9e18-320c662c3b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258052345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3258052345
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3890093310
Short name T371
Test name
Test status
Simulation time 6135930818 ps
CPU time 1.76 seconds
Started Jul 03 07:05:15 PM PDT 24
Finished Jul 03 07:05:18 PM PDT 24
Peak memory 201724 kb
Host smart-10cbffbe-5b0b-48e9-af8d-195ecfe17078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890093310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3890093310
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.816789129
Short name T33
Test name
Test status
Simulation time 3777475165 ps
CPU time 9.66 seconds
Started Jul 03 07:05:21 PM PDT 24
Finished Jul 03 07:05:32 PM PDT 24
Peak memory 201728 kb
Host smart-662f5283-56e8-4483-87d4-3fabdda69a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816789129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
816789129
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4068940307
Short name T638
Test name
Test status
Simulation time 42824962961 ps
CPU time 117.37 seconds
Started Jul 03 07:05:18 PM PDT 24
Finished Jul 03 07:07:18 PM PDT 24
Peak memory 210620 kb
Host smart-8a5bdedb-d806-4777-bb45-8cf9659d2040
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068940307 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4068940307
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1787914844
Short name T550
Test name
Test status
Simulation time 360612700 ps
CPU time 1.36 seconds
Started Jul 03 07:05:29 PM PDT 24
Finished Jul 03 07:05:31 PM PDT 24
Peak memory 201648 kb
Host smart-05c1cbbc-e65b-40bf-93a4-2e5917908291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787914844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1787914844
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4132078578
Short name T797
Test name
Test status
Simulation time 186905248084 ps
CPU time 367.16 seconds
Started Jul 03 07:05:25 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 201908 kb
Host smart-c4caf7f1-005c-4d76-bafd-9959c891e08d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132078578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4132078578
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3398224485
Short name T639
Test name
Test status
Simulation time 166722176865 ps
CPU time 92.25 seconds
Started Jul 03 07:05:24 PM PDT 24
Finished Jul 03 07:06:57 PM PDT 24
Peak memory 201912 kb
Host smart-1dbeea7d-e2ee-4c89-8798-1b3e768bad2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398224485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3398224485
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3473481856
Short name T499
Test name
Test status
Simulation time 323594421935 ps
CPU time 188.66 seconds
Started Jul 03 07:05:17 PM PDT 24
Finished Jul 03 07:08:26 PM PDT 24
Peak memory 201968 kb
Host smart-e3da37a8-9bcc-4e8d-a829-da0fcfce834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473481856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3473481856
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.608838754
Short name T735
Test name
Test status
Simulation time 164786206871 ps
CPU time 200.39 seconds
Started Jul 03 07:05:22 PM PDT 24
Finished Jul 03 07:08:43 PM PDT 24
Peak memory 201896 kb
Host smart-824bc282-4fb5-4a11-888f-c6d2b6e82710
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=608838754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.608838754
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1473506494
Short name T312
Test name
Test status
Simulation time 502271455812 ps
CPU time 582.01 seconds
Started Jul 03 07:05:19 PM PDT 24
Finished Jul 03 07:15:03 PM PDT 24
Peak memory 201936 kb
Host smart-2ab858bd-ae56-40e2-8d58-2fbaf5df75ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473506494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1473506494
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2556179115
Short name T555
Test name
Test status
Simulation time 492272278456 ps
CPU time 1181.19 seconds
Started Jul 03 07:05:19 PM PDT 24
Finished Jul 03 07:25:02 PM PDT 24
Peak memory 201924 kb
Host smart-d844f393-3f51-4e87-884c-f9bc427f835c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556179115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2556179115
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4124389339
Short name T311
Test name
Test status
Simulation time 415832312308 ps
CPU time 952.36 seconds
Started Jul 03 07:05:23 PM PDT 24
Finished Jul 03 07:21:16 PM PDT 24
Peak memory 201992 kb
Host smart-e66f9888-dcf4-44fb-b359-f02c237fe836
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124389339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4124389339
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2815861857
Short name T794
Test name
Test status
Simulation time 395870656617 ps
CPU time 844.49 seconds
Started Jul 03 07:05:24 PM PDT 24
Finished Jul 03 07:19:30 PM PDT 24
Peak memory 201904 kb
Host smart-c546d38d-93dd-42e2-b032-a1e13088825c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815861857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2815861857
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.149397933
Short name T605
Test name
Test status
Simulation time 41989464843 ps
CPU time 91.36 seconds
Started Jul 03 07:05:23 PM PDT 24
Finished Jul 03 07:06:56 PM PDT 24
Peak memory 201692 kb
Host smart-81f52bef-89d0-4bcd-bb4d-24be12af22e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149397933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.149397933
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4082845791
Short name T449
Test name
Test status
Simulation time 3853187155 ps
CPU time 8.42 seconds
Started Jul 03 07:05:24 PM PDT 24
Finished Jul 03 07:05:34 PM PDT 24
Peak memory 201732 kb
Host smart-62027179-ea1c-4327-a587-629cac510bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082845791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4082845791
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3381270679
Short name T162
Test name
Test status
Simulation time 5608938599 ps
CPU time 7.14 seconds
Started Jul 03 07:05:19 PM PDT 24
Finished Jul 03 07:05:28 PM PDT 24
Peak memory 201696 kb
Host smart-eecb8f8c-e11f-48e8-8aeb-abd7b979b251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381270679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3381270679
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1763556380
Short name T229
Test name
Test status
Simulation time 136179534279 ps
CPU time 116.82 seconds
Started Jul 03 07:05:23 PM PDT 24
Finished Jul 03 07:07:21 PM PDT 24
Peak memory 210548 kb
Host smart-7599a6b8-074b-425d-9c65-c22f890bb142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763556380 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1763556380
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1000501421
Short name T110
Test name
Test status
Simulation time 519182590 ps
CPU time 0.9 seconds
Started Jul 03 07:05:33 PM PDT 24
Finished Jul 03 07:05:35 PM PDT 24
Peak memory 201652 kb
Host smart-af851cf1-1235-4819-883c-a72a7121c910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000501421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1000501421
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2437828730
Short name T165
Test name
Test status
Simulation time 169098961245 ps
CPU time 52.55 seconds
Started Jul 03 07:05:29 PM PDT 24
Finished Jul 03 07:06:22 PM PDT 24
Peak memory 201912 kb
Host smart-aa49f71f-ba12-4e31-a16a-03565cb59257
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437828730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2437828730
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2627717313
Short name T334
Test name
Test status
Simulation time 166016309571 ps
CPU time 381.08 seconds
Started Jul 03 07:05:30 PM PDT 24
Finished Jul 03 07:11:52 PM PDT 24
Peak memory 201956 kb
Host smart-0ddfa03e-43b8-4e4a-bf24-c74b79c102b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627717313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2627717313
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.990654641
Short name T739
Test name
Test status
Simulation time 165477023021 ps
CPU time 114.57 seconds
Started Jul 03 07:05:32 PM PDT 24
Finished Jul 03 07:07:27 PM PDT 24
Peak memory 201944 kb
Host smart-befd9929-e010-4cbe-9754-10f3d523b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990654641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.990654641
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4065798588
Short name T690
Test name
Test status
Simulation time 484964307390 ps
CPU time 608.34 seconds
Started Jul 03 07:05:28 PM PDT 24
Finished Jul 03 07:15:38 PM PDT 24
Peak memory 201736 kb
Host smart-5924eeea-7bcb-4f4a-bb46-96a370c96ab9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065798588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4065798588
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1595246778
Short name T579
Test name
Test status
Simulation time 485196137040 ps
CPU time 586.57 seconds
Started Jul 03 07:05:30 PM PDT 24
Finished Jul 03 07:15:17 PM PDT 24
Peak memory 201888 kb
Host smart-edd5c4de-42b6-458e-af1c-380fa2e0389c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595246778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1595246778
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2524367330
Short name T425
Test name
Test status
Simulation time 328211564492 ps
CPU time 687.68 seconds
Started Jul 03 07:05:30 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 201940 kb
Host smart-eff0007c-b9dd-4338-9566-d92ff83f2391
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524367330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2524367330
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.423364879
Short name T470
Test name
Test status
Simulation time 619761241214 ps
CPU time 362.59 seconds
Started Jul 03 07:05:31 PM PDT 24
Finished Jul 03 07:11:34 PM PDT 24
Peak memory 201916 kb
Host smart-fc94fa6e-ea39-4b63-bd70-fd2088362971
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423364879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.423364879
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2612724790
Short name T560
Test name
Test status
Simulation time 97289788662 ps
CPU time 336.02 seconds
Started Jul 03 07:05:35 PM PDT 24
Finished Jul 03 07:11:12 PM PDT 24
Peak memory 202196 kb
Host smart-524a6a57-365d-44a9-8f21-96b75f5962c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612724790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2612724790
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1914463374
Short name T381
Test name
Test status
Simulation time 23948055455 ps
CPU time 28.47 seconds
Started Jul 03 07:05:34 PM PDT 24
Finished Jul 03 07:06:04 PM PDT 24
Peak memory 201688 kb
Host smart-8514ab18-5e3f-4b4a-9607-b8ebb5d56a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914463374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1914463374
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2782160445
Short name T365
Test name
Test status
Simulation time 3156101880 ps
CPU time 7.19 seconds
Started Jul 03 07:05:27 PM PDT 24
Finished Jul 03 07:05:35 PM PDT 24
Peak memory 201708 kb
Host smart-fe7b4df8-90af-4f5e-9d0f-917d22c66980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782160445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2782160445
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2685418209
Short name T692
Test name
Test status
Simulation time 5837030157 ps
CPU time 13.34 seconds
Started Jul 03 07:05:27 PM PDT 24
Finished Jul 03 07:05:42 PM PDT 24
Peak memory 201736 kb
Host smart-60340193-abd4-4269-bf4f-64e16aa44e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685418209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2685418209
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1803676924
Short name T268
Test name
Test status
Simulation time 526258689294 ps
CPU time 594.92 seconds
Started Jul 03 07:05:33 PM PDT 24
Finished Jul 03 07:15:29 PM PDT 24
Peak memory 201916 kb
Host smart-de158e7f-8e42-4446-93ed-1be138fb9185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803676924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1803676924
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3429421233
Short name T46
Test name
Test status
Simulation time 252573370443 ps
CPU time 140.29 seconds
Started Jul 03 07:05:33 PM PDT 24
Finished Jul 03 07:07:55 PM PDT 24
Peak memory 210312 kb
Host smart-4c131643-8d0e-4379-88b6-408624729c06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429421233 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3429421233
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2799915691
Short name T552
Test name
Test status
Simulation time 523324273 ps
CPU time 0.84 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:05:41 PM PDT 24
Peak memory 201652 kb
Host smart-5e29d794-e206-45df-81cc-fc04efa41f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799915691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2799915691
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1046924620
Short name T277
Test name
Test status
Simulation time 533637851355 ps
CPU time 1066.54 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:23:29 PM PDT 24
Peak memory 201916 kb
Host smart-9beb0ec5-b9b3-4141-b972-500a1a504ac0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046924620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1046924620
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2345250551
Short name T226
Test name
Test status
Simulation time 498482150017 ps
CPU time 1066.97 seconds
Started Jul 03 07:05:34 PM PDT 24
Finished Jul 03 07:23:22 PM PDT 24
Peak memory 201988 kb
Host smart-92d623fa-c6ee-446e-abb2-928bb72f8acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345250551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2345250551
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.167718846
Short name T373
Test name
Test status
Simulation time 496766500559 ps
CPU time 1062.71 seconds
Started Jul 03 07:05:40 PM PDT 24
Finished Jul 03 07:23:24 PM PDT 24
Peak memory 201904 kb
Host smart-f1e19f4c-c6b4-4208-ae20-087d4d362359
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=167718846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.167718846
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2413049181
Short name T647
Test name
Test status
Simulation time 163069852042 ps
CPU time 356.31 seconds
Started Jul 03 07:05:36 PM PDT 24
Finished Jul 03 07:11:33 PM PDT 24
Peak memory 201916 kb
Host smart-68ea6246-6a52-43fb-ae63-3ca0fddb697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413049181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2413049181
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3683385671
Short name T389
Test name
Test status
Simulation time 166164992240 ps
CPU time 87 seconds
Started Jul 03 07:05:35 PM PDT 24
Finished Jul 03 07:07:03 PM PDT 24
Peak memory 201812 kb
Host smart-8b93a7aa-1fce-49dc-bdf6-7c423493ffb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683385671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3683385671
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3261806110
Short name T707
Test name
Test status
Simulation time 184164456981 ps
CPU time 112.56 seconds
Started Jul 03 07:05:38 PM PDT 24
Finished Jul 03 07:07:31 PM PDT 24
Peak memory 201916 kb
Host smart-5910de94-7987-46bf-a591-143848b93e74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261806110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3261806110
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.56235338
Short name T394
Test name
Test status
Simulation time 386866056570 ps
CPU time 464.91 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:13:26 PM PDT 24
Peak memory 201892 kb
Host smart-9e7ebe8e-b764-4911-85b5-5467716d302c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56235338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.a
dc_ctrl_filters_wakeup_fixed.56235338
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1361777936
Short name T207
Test name
Test status
Simulation time 99764111780 ps
CPU time 503.26 seconds
Started Jul 03 07:05:40 PM PDT 24
Finished Jul 03 07:14:05 PM PDT 24
Peak memory 202280 kb
Host smart-afa1d5d2-f908-4e40-8f26-d61e95057c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361777936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1361777936
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4117601757
Short name T633
Test name
Test status
Simulation time 22637901799 ps
CPU time 14.05 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:05:54 PM PDT 24
Peak memory 201684 kb
Host smart-05fa82ba-9796-4c10-b654-feff6261a7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117601757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4117601757
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3152788256
Short name T505
Test name
Test status
Simulation time 3676733282 ps
CPU time 4.9 seconds
Started Jul 03 07:05:41 PM PDT 24
Finished Jul 03 07:05:47 PM PDT 24
Peak memory 201736 kb
Host smart-ed24fa46-761d-4e8a-854f-6b59df712343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152788256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3152788256
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2459610439
Short name T461
Test name
Test status
Simulation time 5747007902 ps
CPU time 13.98 seconds
Started Jul 03 07:05:35 PM PDT 24
Finished Jul 03 07:05:50 PM PDT 24
Peak memory 201724 kb
Host smart-03262e93-2a75-4341-82dd-c9eb0d99c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459610439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2459610439
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4187678520
Short name T39
Test name
Test status
Simulation time 1298597880 ps
CPU time 1.44 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:05:41 PM PDT 24
Peak memory 201656 kb
Host smart-d4663ea2-5d97-4809-96f9-4a5840bf4e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187678520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4187678520
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2170724520
Short name T433
Test name
Test status
Simulation time 380150969 ps
CPU time 1.41 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:05:46 PM PDT 24
Peak memory 201652 kb
Host smart-f22f59ca-1c3a-42e5-b0a9-f35672c4a41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170724520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2170724520
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.621230737
Short name T62
Test name
Test status
Simulation time 330449410274 ps
CPU time 176.17 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:08:37 PM PDT 24
Peak memory 201892 kb
Host smart-9b4cafe2-c6ce-4bf6-83a1-62d24f7cc233
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621230737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.621230737
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1940442683
Short name T724
Test name
Test status
Simulation time 351673921868 ps
CPU time 371.48 seconds
Started Jul 03 07:05:40 PM PDT 24
Finished Jul 03 07:11:53 PM PDT 24
Peak memory 201976 kb
Host smart-06e3280c-2951-442b-bb9e-af7e541e8ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940442683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1940442683
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.106639939
Short name T765
Test name
Test status
Simulation time 326415479126 ps
CPU time 202.42 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:09:06 PM PDT 24
Peak memory 201920 kb
Host smart-0b1d0659-2943-4a6b-bb38-aaa296b724e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106639939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.106639939
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3298109490
Short name T727
Test name
Test status
Simulation time 166310243882 ps
CPU time 368.7 seconds
Started Jul 03 07:05:40 PM PDT 24
Finished Jul 03 07:11:50 PM PDT 24
Peak memory 201916 kb
Host smart-f56c7fc1-ee23-411f-b221-6cfa4072a7da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298109490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3298109490
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1996047785
Short name T714
Test name
Test status
Simulation time 329929781829 ps
CPU time 798.45 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 201924 kb
Host smart-81050bab-5e62-4010-ba0c-8fc2bcd6878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996047785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1996047785
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2149379490
Short name T582
Test name
Test status
Simulation time 490244381814 ps
CPU time 1097.12 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:23:58 PM PDT 24
Peak memory 201920 kb
Host smart-d2a6c630-fec8-4556-b5a1-d88313e2996d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149379490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2149379490
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.844095336
Short name T153
Test name
Test status
Simulation time 164102474274 ps
CPU time 66.85 seconds
Started Jul 03 07:05:41 PM PDT 24
Finished Jul 03 07:06:49 PM PDT 24
Peak memory 201988 kb
Host smart-e9b89c78-0509-4197-bc09-f1d823f37c99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844095336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.844095336
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3776905352
Short name T428
Test name
Test status
Simulation time 618457384886 ps
CPU time 681.71 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 201884 kb
Host smart-d49acea4-dc58-4b31-97aa-927b3a384e3f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776905352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3776905352
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2811457279
Short name T456
Test name
Test status
Simulation time 65401739757 ps
CPU time 411.38 seconds
Started Jul 03 07:05:38 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 202188 kb
Host smart-7a49a3e3-adda-42fa-a2d4-4bdf470fa45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811457279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2811457279
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3979151142
Short name T412
Test name
Test status
Simulation time 34043711314 ps
CPU time 80.26 seconds
Started Jul 03 07:05:38 PM PDT 24
Finished Jul 03 07:06:59 PM PDT 24
Peak memory 201676 kb
Host smart-27fc945b-a918-4563-a5ef-f8224eaaad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979151142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3979151142
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3011471495
Short name T769
Test name
Test status
Simulation time 4598270453 ps
CPU time 6.32 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:05:49 PM PDT 24
Peak memory 201724 kb
Host smart-2d14904b-c6fb-439d-be51-0f2dd64bdc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011471495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3011471495
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2357454422
Short name T757
Test name
Test status
Simulation time 5921849821 ps
CPU time 15.15 seconds
Started Jul 03 07:05:39 PM PDT 24
Finished Jul 03 07:05:55 PM PDT 24
Peak memory 201724 kb
Host smart-ece0b28d-76f9-4248-b35f-83c0f69291fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357454422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2357454422
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1456555547
Short name T481
Test name
Test status
Simulation time 165642228247 ps
CPU time 205.36 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:09:10 PM PDT 24
Peak memory 201908 kb
Host smart-8c31a144-9a80-4600-866f-42ae28a9a7fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456555547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1456555547
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.262419099
Short name T40
Test name
Test status
Simulation time 55341016647 ps
CPU time 128.99 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:07:54 PM PDT 24
Peak memory 210264 kb
Host smart-b67e1591-6bfb-41a0-a286-f02fa37268b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262419099 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.262419099
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2235097024
Short name T446
Test name
Test status
Simulation time 445488301 ps
CPU time 1.12 seconds
Started Jul 03 06:52:19 PM PDT 24
Finished Jul 03 06:52:20 PM PDT 24
Peak memory 201648 kb
Host smart-3ef2c59b-6759-4b2b-a34d-84f07d0e3671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235097024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2235097024
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1603436363
Short name T489
Test name
Test status
Simulation time 332206155125 ps
CPU time 296.04 seconds
Started Jul 03 06:51:59 PM PDT 24
Finished Jul 03 06:56:56 PM PDT 24
Peak memory 201892 kb
Host smart-959fc500-c6a0-403a-8b75-cb7e3b93e185
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603436363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1603436363
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3002796798
Short name T5
Test name
Test status
Simulation time 494314922895 ps
CPU time 527.76 seconds
Started Jul 03 06:51:49 PM PDT 24
Finished Jul 03 07:00:37 PM PDT 24
Peak memory 201976 kb
Host smart-75310201-2720-43e1-a2ec-f419e11277e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002796798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3002796798
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4063441196
Short name T403
Test name
Test status
Simulation time 490632954777 ps
CPU time 1040.16 seconds
Started Jul 03 06:51:52 PM PDT 24
Finished Jul 03 07:09:13 PM PDT 24
Peak memory 201880 kb
Host smart-ba703036-7247-42d9-a251-de9d3be0afa0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063441196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4063441196
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1899854767
Short name T247
Test name
Test status
Simulation time 340366809052 ps
CPU time 775.72 seconds
Started Jul 03 06:52:00 PM PDT 24
Finished Jul 03 07:04:56 PM PDT 24
Peak memory 201932 kb
Host smart-d929ff8d-065a-4ce6-90a4-b96d23ea1243
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899854767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1899854767
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4036642571
Short name T390
Test name
Test status
Simulation time 208562251479 ps
CPU time 61.7 seconds
Started Jul 03 06:52:03 PM PDT 24
Finished Jul 03 06:53:06 PM PDT 24
Peak memory 201908 kb
Host smart-8bea309b-9a84-48c7-8f95-9556e7f35831
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036642571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4036642571
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2695355816
Short name T665
Test name
Test status
Simulation time 87844700275 ps
CPU time 301.57 seconds
Started Jul 03 06:52:15 PM PDT 24
Finished Jul 03 06:57:17 PM PDT 24
Peak memory 202236 kb
Host smart-39216360-a8e5-474a-9d9f-b6ac85fd8d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695355816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2695355816
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2812745109
Short name T777
Test name
Test status
Simulation time 42009337780 ps
CPU time 24.46 seconds
Started Jul 03 06:52:09 PM PDT 24
Finished Jul 03 06:52:34 PM PDT 24
Peak memory 201700 kb
Host smart-23520419-5cc3-4321-a2b2-a448c1e4f4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812745109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2812745109
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.227715733
Short name T660
Test name
Test status
Simulation time 4782101675 ps
CPU time 12.61 seconds
Started Jul 03 06:52:09 PM PDT 24
Finished Jul 03 06:52:22 PM PDT 24
Peak memory 201724 kb
Host smart-4a102a74-0e29-411c-b77b-c678e6d6e4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227715733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.227715733
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2960313208
Short name T68
Test name
Test status
Simulation time 4224397309 ps
CPU time 3.07 seconds
Started Jul 03 06:52:20 PM PDT 24
Finished Jul 03 06:52:23 PM PDT 24
Peak memory 217128 kb
Host smart-07849ff7-f580-49f7-bd52-e1e07ffc2026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960313208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2960313208
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3777076632
Short name T460
Test name
Test status
Simulation time 5763818196 ps
CPU time 2.59 seconds
Started Jul 03 06:51:45 PM PDT 24
Finished Jul 03 06:51:48 PM PDT 24
Peak memory 201696 kb
Host smart-51064dce-f2b8-4c2d-9286-2975415c2f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777076632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3777076632
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3713718190
Short name T242
Test name
Test status
Simulation time 395956190421 ps
CPU time 74.59 seconds
Started Jul 03 06:52:13 PM PDT 24
Finished Jul 03 06:53:28 PM PDT 24
Peak memory 210524 kb
Host smart-2a966ae1-03f4-4b9e-98be-68ad2d3980d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713718190 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3713718190
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2268969532
Short name T585
Test name
Test status
Simulation time 473812326 ps
CPU time 1.61 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:05:46 PM PDT 24
Peak memory 201596 kb
Host smart-24b05ada-23ab-4a32-859a-f6b7ded99ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268969532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2268969532
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2099700351
Short name T236
Test name
Test status
Simulation time 348668399527 ps
CPU time 774.64 seconds
Started Jul 03 07:05:44 PM PDT 24
Finished Jul 03 07:18:40 PM PDT 24
Peak memory 201984 kb
Host smart-fa0b1dd5-5dd7-42bd-bbe3-bd612d635a2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099700351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2099700351
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1082835957
Short name T508
Test name
Test status
Simulation time 425602937922 ps
CPU time 493.15 seconds
Started Jul 03 07:05:46 PM PDT 24
Finished Jul 03 07:14:00 PM PDT 24
Peak memory 201912 kb
Host smart-4a8c73c7-49a4-4f81-9ce5-36e7e99b8b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082835957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1082835957
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2667974130
Short name T102
Test name
Test status
Simulation time 166783665914 ps
CPU time 405.08 seconds
Started Jul 03 07:05:44 PM PDT 24
Finished Jul 03 07:12:30 PM PDT 24
Peak memory 201916 kb
Host smart-7ea8fb97-319e-45bd-9992-3a94806f35c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667974130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2667974130
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2164728396
Short name T691
Test name
Test status
Simulation time 488849027130 ps
CPU time 1117.01 seconds
Started Jul 03 07:05:45 PM PDT 24
Finished Jul 03 07:24:23 PM PDT 24
Peak memory 201864 kb
Host smart-0c151a3f-4cae-47b7-83dd-bef4e3f23d2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164728396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2164728396
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2309342724
Short name T219
Test name
Test status
Simulation time 492092382810 ps
CPU time 212.06 seconds
Started Jul 03 07:05:46 PM PDT 24
Finished Jul 03 07:09:19 PM PDT 24
Peak memory 201932 kb
Host smart-e2de00f6-5261-487d-9ba4-b3249d66f860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309342724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2309342724
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.280589094
Short name T599
Test name
Test status
Simulation time 489862862751 ps
CPU time 256.38 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:09:59 PM PDT 24
Peak memory 201908 kb
Host smart-ddaa489c-8761-406b-8bbb-8d5af7bbf58d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=280589094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.280589094
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3103428942
Short name T788
Test name
Test status
Simulation time 347657137553 ps
CPU time 389.52 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:12:13 PM PDT 24
Peak memory 201924 kb
Host smart-7324cab7-bfe5-417b-b478-ec205025aacc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103428942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3103428942
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.288602844
Short name T744
Test name
Test status
Simulation time 398362950062 ps
CPU time 857.48 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:20:02 PM PDT 24
Peak memory 201912 kb
Host smart-e0c7932b-fcea-4a3a-b915-fa9ef477c33b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288602844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.288602844
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1527213571
Short name T473
Test name
Test status
Simulation time 67107424040 ps
CPU time 235.41 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:09:40 PM PDT 24
Peak memory 202252 kb
Host smart-b9651a09-89a5-4e9a-b983-4d23d2638975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527213571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1527213571
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1477008773
Short name T614
Test name
Test status
Simulation time 40581068059 ps
CPU time 45.17 seconds
Started Jul 03 07:05:45 PM PDT 24
Finished Jul 03 07:06:31 PM PDT 24
Peak memory 201708 kb
Host smart-0e10260c-02c2-4393-b118-edfb5f71194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477008773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1477008773
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2864981760
Short name T685
Test name
Test status
Simulation time 4231819070 ps
CPU time 10.28 seconds
Started Jul 03 07:05:46 PM PDT 24
Finished Jul 03 07:05:58 PM PDT 24
Peak memory 201680 kb
Host smart-86671ed7-dd42-447d-a4b2-4f60dfa9128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864981760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2864981760
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.586414783
Short name T507
Test name
Test status
Simulation time 5859967560 ps
CPU time 4.35 seconds
Started Jul 03 07:05:42 PM PDT 24
Finished Jul 03 07:05:48 PM PDT 24
Peak memory 201740 kb
Host smart-f5c28fbd-f479-4826-a026-210fe640d58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586414783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.586414783
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1247641392
Short name T230
Test name
Test status
Simulation time 361125084182 ps
CPU time 411.84 seconds
Started Jul 03 07:05:44 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 201808 kb
Host smart-921d5060-4f62-4c73-8a41-254a36aaf16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247641392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1247641392
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.728157818
Short name T111
Test name
Test status
Simulation time 26901775298 ps
CPU time 69.34 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:06:53 PM PDT 24
Peak memory 218228 kb
Host smart-54957e6f-2e97-46d0-a914-dc5cecbd1875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728157818 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.728157818
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1252300370
Short name T719
Test name
Test status
Simulation time 563799174 ps
CPU time 0.72 seconds
Started Jul 03 07:05:49 PM PDT 24
Finished Jul 03 07:05:51 PM PDT 24
Peak memory 201652 kb
Host smart-d54a61d5-050e-443f-8e4c-9cd094b347c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252300370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1252300370
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.391291698
Short name T741
Test name
Test status
Simulation time 159686435218 ps
CPU time 190.07 seconds
Started Jul 03 07:05:50 PM PDT 24
Finished Jul 03 07:09:02 PM PDT 24
Peak memory 201908 kb
Host smart-cdb07116-1584-4d52-afd5-84e0d3b78638
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391291698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.391291698
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2092339857
Short name T183
Test name
Test status
Simulation time 526235947000 ps
CPU time 217.25 seconds
Started Jul 03 07:05:50 PM PDT 24
Finished Jul 03 07:09:29 PM PDT 24
Peak memory 201812 kb
Host smart-209bc937-2699-4ab3-bb60-33c320839e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092339857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2092339857
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2969952814
Short name T181
Test name
Test status
Simulation time 324772902831 ps
CPU time 196.08 seconds
Started Jul 03 07:05:49 PM PDT 24
Finished Jul 03 07:09:06 PM PDT 24
Peak memory 201960 kb
Host smart-d968af02-98b5-4128-8e01-06b69f5594f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969952814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2969952814
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3744725305
Short name T167
Test name
Test status
Simulation time 330507550972 ps
CPU time 81.01 seconds
Started Jul 03 07:05:49 PM PDT 24
Finished Jul 03 07:07:12 PM PDT 24
Peak memory 201868 kb
Host smart-ea617700-2443-480d-9838-7fe2a4eb3ae6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744725305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3744725305
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1489682973
Short name T189
Test name
Test status
Simulation time 493401005590 ps
CPU time 270.54 seconds
Started Jul 03 07:05:43 PM PDT 24
Finished Jul 03 07:10:14 PM PDT 24
Peak memory 201848 kb
Host smart-b070b55b-9ea4-4599-bfa6-d15e9bb5d75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489682973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1489682973
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1042569920
Short name T436
Test name
Test status
Simulation time 165678251264 ps
CPU time 387.1 seconds
Started Jul 03 07:05:50 PM PDT 24
Finished Jul 03 07:12:19 PM PDT 24
Peak memory 201888 kb
Host smart-697cdcad-08a2-45b1-8c22-b117ce9df879
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042569920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1042569920
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1017930213
Short name T362
Test name
Test status
Simulation time 608043464309 ps
CPU time 680.13 seconds
Started Jul 03 07:05:50 PM PDT 24
Finished Jul 03 07:17:12 PM PDT 24
Peak memory 201904 kb
Host smart-09f1009e-ab1f-43c4-8a39-b84356f2e568
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017930213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1017930213
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2961064036
Short name T593
Test name
Test status
Simulation time 92552045853 ps
CPU time 479.4 seconds
Started Jul 03 07:05:49 PM PDT 24
Finished Jul 03 07:13:51 PM PDT 24
Peak memory 202204 kb
Host smart-9ddb812c-344d-464a-a78d-9555de9952f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961064036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2961064036
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2064738230
Short name T546
Test name
Test status
Simulation time 38840741800 ps
CPU time 91.36 seconds
Started Jul 03 07:05:48 PM PDT 24
Finished Jul 03 07:07:20 PM PDT 24
Peak memory 201712 kb
Host smart-46d415fd-d0e2-4349-bde6-fe9cbe140f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064738230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2064738230
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2836144677
Short name T140
Test name
Test status
Simulation time 3012505868 ps
CPU time 3.94 seconds
Started Jul 03 07:05:51 PM PDT 24
Finished Jul 03 07:05:57 PM PDT 24
Peak memory 201720 kb
Host smart-bfd89d77-8d92-48c9-8bfd-c946ba585f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836144677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2836144677
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3334312702
Short name T515
Test name
Test status
Simulation time 5836416488 ps
CPU time 3.17 seconds
Started Jul 03 07:05:46 PM PDT 24
Finished Jul 03 07:05:51 PM PDT 24
Peak memory 201704 kb
Host smart-d1c7e274-eeb2-4ac9-8f3f-6b497b20bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334312702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3334312702
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.274541710
Short name T677
Test name
Test status
Simulation time 373157514843 ps
CPU time 853.68 seconds
Started Jul 03 07:05:48 PM PDT 24
Finished Jul 03 07:20:03 PM PDT 24
Peak memory 201904 kb
Host smart-2c52017c-d270-4853-adee-689e6d3de71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274541710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
274541710
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2010214974
Short name T663
Test name
Test status
Simulation time 20922651565 ps
CPU time 24.8 seconds
Started Jul 03 07:05:49 PM PDT 24
Finished Jul 03 07:06:15 PM PDT 24
Peak memory 210212 kb
Host smart-c54e40af-6592-419c-8cf6-0c216734c743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010214974 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2010214974
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2417682426
Short name T437
Test name
Test status
Simulation time 412927739 ps
CPU time 1.06 seconds
Started Jul 03 07:05:52 PM PDT 24
Finished Jul 03 07:05:57 PM PDT 24
Peak memory 201664 kb
Host smart-2ae43bef-7c40-4d93-8ff4-86ba32de20c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417682426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2417682426
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3854487556
Short name T317
Test name
Test status
Simulation time 168645197255 ps
CPU time 91.92 seconds
Started Jul 03 07:05:55 PM PDT 24
Finished Jul 03 07:07:29 PM PDT 24
Peak memory 201920 kb
Host smart-b8736cce-0567-48e1-816e-7f305e80fb93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854487556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3854487556
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.4126465566
Short name T256
Test name
Test status
Simulation time 347390918147 ps
CPU time 740.27 seconds
Started Jul 03 07:05:52 PM PDT 24
Finished Jul 03 07:18:16 PM PDT 24
Peak memory 201924 kb
Host smart-286f01b7-6344-47c8-b07f-d36df91a2e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126465566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.4126465566
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4277645883
Short name T308
Test name
Test status
Simulation time 164166137379 ps
CPU time 376.07 seconds
Started Jul 03 07:05:53 PM PDT 24
Finished Jul 03 07:12:12 PM PDT 24
Peak memory 201944 kb
Host smart-70ac6159-fb0c-438b-81b4-18f8d1b7d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277645883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4277645883
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.289539772
Short name T498
Test name
Test status
Simulation time 330486505666 ps
CPU time 758.71 seconds
Started Jul 03 07:05:53 PM PDT 24
Finished Jul 03 07:18:35 PM PDT 24
Peak memory 201792 kb
Host smart-0a9c223c-537b-4395-b3f9-4c56d3c39224
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=289539772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.289539772
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1244012061
Short name T114
Test name
Test status
Simulation time 489473959217 ps
CPU time 1026.39 seconds
Started Jul 03 07:05:50 PM PDT 24
Finished Jul 03 07:22:58 PM PDT 24
Peak memory 201880 kb
Host smart-88b85a78-667c-4618-8abb-f7de69efa38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244012061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1244012061
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.397760908
Short name T86
Test name
Test status
Simulation time 335074814974 ps
CPU time 72.26 seconds
Started Jul 03 07:05:51 PM PDT 24
Finished Jul 03 07:07:06 PM PDT 24
Peak memory 201912 kb
Host smart-2798162d-0fbe-457c-a028-e32c259f5dd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=397760908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.397760908
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.382394200
Short name T327
Test name
Test status
Simulation time 211086137873 ps
CPU time 37.44 seconds
Started Jul 03 07:05:52 PM PDT 24
Finished Jul 03 07:06:32 PM PDT 24
Peak memory 201868 kb
Host smart-98daffa7-b283-4867-b3d6-39b8baf7db55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382394200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.382394200
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.411462074
Short name T463
Test name
Test status
Simulation time 391696098736 ps
CPU time 408.67 seconds
Started Jul 03 07:05:53 PM PDT 24
Finished Jul 03 07:12:45 PM PDT 24
Peak memory 201900 kb
Host smart-673ca0e6-e6fb-45ed-9bdb-a24a59ca48d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411462074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.411462074
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1694635714
Short name T59
Test name
Test status
Simulation time 104081161163 ps
CPU time 573.87 seconds
Started Jul 03 07:05:53 PM PDT 24
Finished Jul 03 07:15:30 PM PDT 24
Peak memory 202208 kb
Host smart-6ced2144-b6fd-4afa-9880-ccb8c82ce2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694635714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1694635714
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3327054853
Short name T496
Test name
Test status
Simulation time 28414157735 ps
CPU time 66.43 seconds
Started Jul 03 07:05:55 PM PDT 24
Finished Jul 03 07:07:04 PM PDT 24
Peak memory 201732 kb
Host smart-326d1ee6-1c3c-4dfd-86d2-782c02505eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327054853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3327054853
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2192908145
Short name T1
Test name
Test status
Simulation time 5364552897 ps
CPU time 4.02 seconds
Started Jul 03 07:05:52 PM PDT 24
Finished Jul 03 07:05:59 PM PDT 24
Peak memory 201720 kb
Host smart-a494f503-1964-41c9-929a-a2c391612760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192908145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2192908145
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1304798291
Short name T664
Test name
Test status
Simulation time 5717181978 ps
CPU time 12.6 seconds
Started Jul 03 07:05:51 PM PDT 24
Finished Jul 03 07:06:06 PM PDT 24
Peak memory 201696 kb
Host smart-ac51674a-36f4-48d5-a1e9-20c42e312544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304798291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1304798291
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2492667481
Short name T756
Test name
Test status
Simulation time 12441958367 ps
CPU time 8.75 seconds
Started Jul 03 07:05:52 PM PDT 24
Finished Jul 03 07:06:04 PM PDT 24
Peak memory 201956 kb
Host smart-db4c63ef-bcc6-495e-a48c-a34d875a5539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492667481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2492667481
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1952746733
Short name T91
Test name
Test status
Simulation time 89443826582 ps
CPU time 124.86 seconds
Started Jul 03 07:05:54 PM PDT 24
Finished Jul 03 07:08:02 PM PDT 24
Peak memory 211540 kb
Host smart-3cc188cf-152b-4ecd-aecd-de1e5b412ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952746733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1952746733
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2677291311
Short name T76
Test name
Test status
Simulation time 524313943 ps
CPU time 1.34 seconds
Started Jul 03 07:06:03 PM PDT 24
Finished Jul 03 07:06:05 PM PDT 24
Peak memory 201632 kb
Host smart-d7ec6506-d451-47f1-a563-32b7816f196a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677291311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2677291311
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4238383092
Short name T595
Test name
Test status
Simulation time 487290523827 ps
CPU time 1192.27 seconds
Started Jul 03 07:06:00 PM PDT 24
Finished Jul 03 07:25:53 PM PDT 24
Peak memory 201896 kb
Host smart-a292330c-c282-4f1e-b3c0-4b7858ffe8ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238383092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4238383092
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.185519053
Short name T411
Test name
Test status
Simulation time 160861372397 ps
CPU time 26.1 seconds
Started Jul 03 07:05:53 PM PDT 24
Finished Jul 03 07:06:22 PM PDT 24
Peak memory 201928 kb
Host smart-cad996f9-2121-4278-8ce7-f81bef57046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185519053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.185519053
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1080700899
Short name T434
Test name
Test status
Simulation time 499094272927 ps
CPU time 1160.29 seconds
Started Jul 03 07:05:55 PM PDT 24
Finished Jul 03 07:25:18 PM PDT 24
Peak memory 201908 kb
Host smart-a1285d93-4bf5-4308-8acc-57fbfca565a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080700899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1080700899
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1268153389
Short name T240
Test name
Test status
Simulation time 538853697135 ps
CPU time 1274.55 seconds
Started Jul 03 07:05:59 PM PDT 24
Finished Jul 03 07:27:14 PM PDT 24
Peak memory 201864 kb
Host smart-38e8369f-d3af-419d-b079-faf379eabfdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268153389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1268153389
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.230193750
Short name T352
Test name
Test status
Simulation time 196762397530 ps
CPU time 114.13 seconds
Started Jul 03 07:05:58 PM PDT 24
Finished Jul 03 07:07:53 PM PDT 24
Peak memory 201900 kb
Host smart-749455f3-83c7-461d-b19e-c33b734b37db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230193750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.230193750
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1469035420
Short name T208
Test name
Test status
Simulation time 81218321599 ps
CPU time 343.05 seconds
Started Jul 03 07:06:04 PM PDT 24
Finished Jul 03 07:11:48 PM PDT 24
Peak memory 202260 kb
Host smart-0b8152ee-7594-4d01-ae98-206e8fce039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469035420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1469035420
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.857405586
Short name T476
Test name
Test status
Simulation time 29718785892 ps
CPU time 69.86 seconds
Started Jul 03 07:06:03 PM PDT 24
Finished Jul 03 07:07:15 PM PDT 24
Peak memory 201688 kb
Host smart-0a59e2f3-e8cc-4e2a-8414-89a54d0aa040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857405586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.857405586
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.811017864
Short name T355
Test name
Test status
Simulation time 4031877658 ps
CPU time 1.41 seconds
Started Jul 03 07:05:58 PM PDT 24
Finished Jul 03 07:06:00 PM PDT 24
Peak memory 201696 kb
Host smart-ebcc2812-2a0c-4466-a33f-71597b22f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811017864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.811017864
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1179016134
Short name T105
Test name
Test status
Simulation time 5883884393 ps
CPU time 14.2 seconds
Started Jul 03 07:05:53 PM PDT 24
Finished Jul 03 07:06:10 PM PDT 24
Peak memory 201752 kb
Host smart-8d326006-a9b7-47bc-af61-d30dfcb07750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179016134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1179016134
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1480678440
Short name T518
Test name
Test status
Simulation time 27220955139 ps
CPU time 48.97 seconds
Started Jul 03 07:06:03 PM PDT 24
Finished Jul 03 07:06:53 PM PDT 24
Peak memory 201728 kb
Host smart-e5f0d470-e6a5-4110-87a1-a5c19597010c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480678440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1480678440
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2595921097
Short name T780
Test name
Test status
Simulation time 374903788 ps
CPU time 1.39 seconds
Started Jul 03 07:06:06 PM PDT 24
Finished Jul 03 07:06:09 PM PDT 24
Peak memory 201628 kb
Host smart-2f991b56-11ce-4302-8e93-92684abb17ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595921097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2595921097
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1168514171
Short name T271
Test name
Test status
Simulation time 381011812662 ps
CPU time 216.49 seconds
Started Jul 03 07:06:09 PM PDT 24
Finished Jul 03 07:09:47 PM PDT 24
Peak memory 201884 kb
Host smart-4d887b3e-2c94-4126-829c-e106626dd35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168514171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1168514171
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4279777513
Short name T626
Test name
Test status
Simulation time 331929562271 ps
CPU time 744.58 seconds
Started Jul 03 07:06:03 PM PDT 24
Finished Jul 03 07:18:29 PM PDT 24
Peak memory 201948 kb
Host smart-8c78b305-b1bb-4505-8daf-730e34b1d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279777513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4279777513
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.543275886
Short name T720
Test name
Test status
Simulation time 169420864486 ps
CPU time 150.4 seconds
Started Jul 03 07:06:07 PM PDT 24
Finished Jul 03 07:08:38 PM PDT 24
Peak memory 201868 kb
Host smart-9806c7c9-446b-44c6-aaf0-ab93c4fb6130
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=543275886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.543275886
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1981616350
Short name T188
Test name
Test status
Simulation time 336082490111 ps
CPU time 184.52 seconds
Started Jul 03 07:06:04 PM PDT 24
Finished Jul 03 07:09:10 PM PDT 24
Peak memory 201876 kb
Host smart-68fdf62e-3fa4-4706-be36-f4f3762ec6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981616350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1981616350
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4146449844
Short name T354
Test name
Test status
Simulation time 504236635326 ps
CPU time 565.33 seconds
Started Jul 03 07:06:02 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 201920 kb
Host smart-83d2977f-f5a9-44ce-8c6f-ec25d825f8fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146449844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4146449844
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1708571701
Short name T659
Test name
Test status
Simulation time 178440936304 ps
CPU time 224.03 seconds
Started Jul 03 07:06:06 PM PDT 24
Finished Jul 03 07:09:51 PM PDT 24
Peak memory 201936 kb
Host smart-62bb0b4e-639d-4264-836b-b9a3b0de6a18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708571701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1708571701
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2483478704
Short name T586
Test name
Test status
Simulation time 603810046322 ps
CPU time 310.76 seconds
Started Jul 03 07:06:08 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 201908 kb
Host smart-9bc89555-1439-49ff-b0cf-fd9cb0acf7f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483478704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2483478704
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2213439071
Short name T578
Test name
Test status
Simulation time 77620086975 ps
CPU time 245.69 seconds
Started Jul 03 07:06:07 PM PDT 24
Finished Jul 03 07:10:14 PM PDT 24
Peak memory 202184 kb
Host smart-f30ea35c-f36e-4031-99d7-afe42556b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213439071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2213439071
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.764076420
Short name T753
Test name
Test status
Simulation time 23144487760 ps
CPU time 37.77 seconds
Started Jul 03 07:06:07 PM PDT 24
Finished Jul 03 07:06:46 PM PDT 24
Peak memory 201652 kb
Host smart-69c24d99-ee29-4b09-89c6-9fd64e6a8994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764076420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.764076420
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3738548484
Short name T706
Test name
Test status
Simulation time 5128186100 ps
CPU time 13.31 seconds
Started Jul 03 07:06:06 PM PDT 24
Finished Jul 03 07:06:20 PM PDT 24
Peak memory 201728 kb
Host smart-cadf5054-e3a9-415a-b2ea-b751f846eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738548484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3738548484
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1440806172
Short name T101
Test name
Test status
Simulation time 5739026508 ps
CPU time 3.82 seconds
Started Jul 03 07:06:03 PM PDT 24
Finished Jul 03 07:06:07 PM PDT 24
Peak memory 201712 kb
Host smart-6a4ae1f9-526d-4118-994a-087347913062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440806172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1440806172
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2132612290
Short name T250
Test name
Test status
Simulation time 225403194021 ps
CPU time 312.08 seconds
Started Jul 03 07:06:07 PM PDT 24
Finished Jul 03 07:11:20 PM PDT 24
Peak memory 201900 kb
Host smart-292a5294-d54e-493c-a2e7-0f1ccfad33ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132612290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2132612290
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.349804666
Short name T212
Test name
Test status
Simulation time 81167887589 ps
CPU time 364.41 seconds
Started Jul 03 07:06:07 PM PDT 24
Finished Jul 03 07:12:12 PM PDT 24
Peak memory 211620 kb
Host smart-84a6145a-3912-42df-852c-4da7cc261697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349804666 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.349804666
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1534971507
Short name T628
Test name
Test status
Simulation time 508313047 ps
CPU time 1.8 seconds
Started Jul 03 07:06:19 PM PDT 24
Finished Jul 03 07:06:22 PM PDT 24
Peak memory 201620 kb
Host smart-4cb08989-a2ab-41d5-a36e-bd16ceae8412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534971507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1534971507
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.231135391
Short name T305
Test name
Test status
Simulation time 349137137126 ps
CPU time 382.18 seconds
Started Jul 03 07:06:14 PM PDT 24
Finished Jul 03 07:12:37 PM PDT 24
Peak memory 201888 kb
Host smart-30539dd3-99cc-46cd-aa02-64b9ee72a1a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231135391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.231135391
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1133170019
Short name T512
Test name
Test status
Simulation time 328204727568 ps
CPU time 739.99 seconds
Started Jul 03 07:06:12 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 201936 kb
Host smart-e722d575-bba5-49ab-acde-2084fd10ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133170019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1133170019
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2803307606
Short name T484
Test name
Test status
Simulation time 328887573184 ps
CPU time 783.83 seconds
Started Jul 03 07:06:12 PM PDT 24
Finished Jul 03 07:19:16 PM PDT 24
Peak memory 201904 kb
Host smart-0955ed66-fbcc-463b-98f1-f78b3a325bd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803307606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2803307606
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1568939974
Short name T693
Test name
Test status
Simulation time 496176923371 ps
CPU time 317.76 seconds
Started Jul 03 07:06:13 PM PDT 24
Finished Jul 03 07:11:32 PM PDT 24
Peak memory 201952 kb
Host smart-fcb5391d-e218-4ef5-a8ca-0e9d5f36531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568939974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1568939974
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3854437947
Short name T25
Test name
Test status
Simulation time 487942153400 ps
CPU time 620.51 seconds
Started Jul 03 07:06:18 PM PDT 24
Finished Jul 03 07:16:40 PM PDT 24
Peak memory 200672 kb
Host smart-02e3cdff-487a-4e42-aef0-740471fb6bac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854437947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3854437947
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3117962230
Short name T694
Test name
Test status
Simulation time 172389327656 ps
CPU time 359.54 seconds
Started Jul 03 07:06:12 PM PDT 24
Finished Jul 03 07:12:12 PM PDT 24
Peak memory 201920 kb
Host smart-756a3fd8-1b7f-4a6e-9683-974d6ebca378
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117962230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3117962230
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3505618182
Short name T413
Test name
Test status
Simulation time 589842806095 ps
CPU time 1435.99 seconds
Started Jul 03 07:06:12 PM PDT 24
Finished Jul 03 07:30:09 PM PDT 24
Peak memory 201868 kb
Host smart-72b7f59e-7125-4863-93ce-cf6d1eb58438
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505618182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3505618182
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.506953808
Short name T214
Test name
Test status
Simulation time 101653085733 ps
CPU time 423.82 seconds
Started Jul 03 07:06:17 PM PDT 24
Finished Jul 03 07:13:23 PM PDT 24
Peak memory 202236 kb
Host smart-b539df04-f91c-4f61-a5f7-8f3091290897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506953808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.506953808
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1306222756
Short name T602
Test name
Test status
Simulation time 48415885069 ps
CPU time 10.85 seconds
Started Jul 03 07:06:15 PM PDT 24
Finished Jul 03 07:06:26 PM PDT 24
Peak memory 201708 kb
Host smart-9396c280-b087-45da-bd7e-1d8b7e79d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306222756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1306222756
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2333851730
Short name T622
Test name
Test status
Simulation time 5580278344 ps
CPU time 13.15 seconds
Started Jul 03 07:06:13 PM PDT 24
Finished Jul 03 07:06:26 PM PDT 24
Peak memory 201696 kb
Host smart-f6f04f31-9aee-4cc3-a881-cfb241c03669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333851730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2333851730
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3263512507
Short name T610
Test name
Test status
Simulation time 5634725661 ps
CPU time 13.13 seconds
Started Jul 03 07:06:18 PM PDT 24
Finished Jul 03 07:06:33 PM PDT 24
Peak memory 201248 kb
Host smart-d5ee1f0e-820b-413f-b4b4-7c4181857d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263512507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3263512507
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2839326523
Short name T38
Test name
Test status
Simulation time 1728162999302 ps
CPU time 1222.21 seconds
Started Jul 03 07:06:18 PM PDT 24
Finished Jul 03 07:26:42 PM PDT 24
Peak memory 209136 kb
Host smart-94a9f746-15e3-41c1-a762-ae80373ba06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839326523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2839326523
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.44751078
Short name T532
Test name
Test status
Simulation time 3701140857 ps
CPU time 3.11 seconds
Started Jul 03 07:06:17 PM PDT 24
Finished Jul 03 07:06:22 PM PDT 24
Peak memory 201832 kb
Host smart-ed78528a-ffe9-4fb6-b834-1d37e69a1247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44751078 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.44751078
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2162193652
Short name T440
Test name
Test status
Simulation time 384540029 ps
CPU time 1.49 seconds
Started Jul 03 07:06:20 PM PDT 24
Finished Jul 03 07:06:22 PM PDT 24
Peak memory 201692 kb
Host smart-1bb26055-a3ae-49b2-8cdb-6e18acccf109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162193652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2162193652
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2124179715
Short name T510
Test name
Test status
Simulation time 326933917680 ps
CPU time 102.5 seconds
Started Jul 03 07:06:21 PM PDT 24
Finished Jul 03 07:08:05 PM PDT 24
Peak memory 201932 kb
Host smart-11c59540-52e3-4d28-a3bc-6d1054c85b7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124179715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2124179715
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2506452131
Short name T179
Test name
Test status
Simulation time 492753282261 ps
CPU time 280.54 seconds
Started Jul 03 07:06:18 PM PDT 24
Finished Jul 03 07:11:00 PM PDT 24
Peak memory 201988 kb
Host smart-8a3cf84e-ffed-4e52-a403-c537500b5b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506452131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2506452131
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.78244973
Short name T531
Test name
Test status
Simulation time 164762162313 ps
CPU time 99.18 seconds
Started Jul 03 07:06:17 PM PDT 24
Finished Jul 03 07:07:58 PM PDT 24
Peak memory 201852 kb
Host smart-432ebdbe-a508-41c0-b5b3-dd710efab938
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=78244973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt
_fixed.78244973
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.687551617
Short name T566
Test name
Test status
Simulation time 167462819251 ps
CPU time 375.36 seconds
Started Jul 03 07:06:16 PM PDT 24
Finished Jul 03 07:12:32 PM PDT 24
Peak memory 201924 kb
Host smart-59c9f4d5-745b-4a8e-bc3f-14fc612c790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687551617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.687551617
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3896742763
Short name T648
Test name
Test status
Simulation time 158512362542 ps
CPU time 381.23 seconds
Started Jul 03 07:06:17 PM PDT 24
Finished Jul 03 07:12:39 PM PDT 24
Peak memory 201996 kb
Host smart-64c7b53a-2e87-4178-b8cb-f86eb767a191
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896742763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3896742763
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.654064830
Short name T675
Test name
Test status
Simulation time 204577862245 ps
CPU time 451.15 seconds
Started Jul 03 07:06:18 PM PDT 24
Finished Jul 03 07:13:51 PM PDT 24
Peak memory 201892 kb
Host smart-21fb9da0-ee10-49d6-a65a-6e9da4ac502d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654064830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.654064830
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1081082312
Short name T540
Test name
Test status
Simulation time 203458434354 ps
CPU time 473.26 seconds
Started Jul 03 07:06:15 PM PDT 24
Finished Jul 03 07:14:09 PM PDT 24
Peak memory 201920 kb
Host smart-11aab1cd-9c23-4e23-8605-66392a1544b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081082312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1081082312
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3049217789
Short name T209
Test name
Test status
Simulation time 126847270691 ps
CPU time 522.51 seconds
Started Jul 03 07:06:23 PM PDT 24
Finished Jul 03 07:15:07 PM PDT 24
Peak memory 202264 kb
Host smart-5b5c8efe-b17d-40f4-b3b9-db8ac04d2233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049217789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3049217789
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3746711834
Short name T192
Test name
Test status
Simulation time 42258433468 ps
CPU time 96.14 seconds
Started Jul 03 07:06:22 PM PDT 24
Finished Jul 03 07:08:00 PM PDT 24
Peak memory 201684 kb
Host smart-60836e6c-50a5-4822-afcc-504b5880118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746711834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3746711834
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.440244024
Short name T527
Test name
Test status
Simulation time 4537199714 ps
CPU time 3.52 seconds
Started Jul 03 07:06:20 PM PDT 24
Finished Jul 03 07:06:25 PM PDT 24
Peak memory 201724 kb
Host smart-dfbb6933-17ae-4d69-9a4b-227bb42b4ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440244024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.440244024
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2530321753
Short name T596
Test name
Test status
Simulation time 5917237739 ps
CPU time 14.23 seconds
Started Jul 03 07:06:16 PM PDT 24
Finished Jul 03 07:06:31 PM PDT 24
Peak memory 201696 kb
Host smart-fe751bd0-191c-407a-b7cf-20db357e94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530321753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2530321753
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3121843954
Short name T336
Test name
Test status
Simulation time 524964978782 ps
CPU time 1274.76 seconds
Started Jul 03 07:06:23 PM PDT 24
Finished Jul 03 07:27:40 PM PDT 24
Peak memory 201968 kb
Host smart-6820433e-0857-4701-b581-74052564f1a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121843954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3121843954
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1270971278
Short name T42
Test name
Test status
Simulation time 179218125369 ps
CPU time 107.23 seconds
Started Jul 03 07:06:22 PM PDT 24
Finished Jul 03 07:08:11 PM PDT 24
Peak memory 210260 kb
Host smart-bb9198b1-83a3-4771-a44d-87f28c8ebe1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270971278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1270971278
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.348912388
Short name T377
Test name
Test status
Simulation time 415144112 ps
CPU time 1.05 seconds
Started Jul 03 07:06:31 PM PDT 24
Finished Jul 03 07:06:33 PM PDT 24
Peak memory 201616 kb
Host smart-c914959b-0927-4cb9-bb94-81a86312dca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348912388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.348912388
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.4030434481
Short name T174
Test name
Test status
Simulation time 491183683288 ps
CPU time 239.96 seconds
Started Jul 03 07:06:26 PM PDT 24
Finished Jul 03 07:10:27 PM PDT 24
Peak memory 201936 kb
Host smart-c77c871d-b0ee-4c77-8e5a-d48b8871e70a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030434481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.4030434481
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.425424250
Short name T776
Test name
Test status
Simulation time 169476981055 ps
CPU time 98.31 seconds
Started Jul 03 07:06:25 PM PDT 24
Finished Jul 03 07:08:05 PM PDT 24
Peak memory 201844 kb
Host smart-687de135-3c2d-421b-9bf2-58d094af0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425424250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.425424250
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2601179507
Short name T537
Test name
Test status
Simulation time 326007098518 ps
CPU time 691.19 seconds
Started Jul 03 07:06:24 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 201900 kb
Host smart-8e929464-11d3-42d1-9ac8-032c7c1dd8be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601179507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2601179507
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1075974697
Short name T289
Test name
Test status
Simulation time 488903330368 ps
CPU time 1076.83 seconds
Started Jul 03 07:06:21 PM PDT 24
Finished Jul 03 07:24:19 PM PDT 24
Peak memory 201920 kb
Host smart-0f0d6314-3035-484f-8b20-6467a797674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075974697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1075974697
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3588722239
Short name T613
Test name
Test status
Simulation time 164741112024 ps
CPU time 60.63 seconds
Started Jul 03 07:06:21 PM PDT 24
Finished Jul 03 07:07:23 PM PDT 24
Peak memory 201916 kb
Host smart-ff1b9e58-c1e0-410c-ba39-a2062129d7dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588722239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3588722239
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.4173579675
Short name T266
Test name
Test status
Simulation time 592103278679 ps
CPU time 622.21 seconds
Started Jul 03 07:06:26 PM PDT 24
Finished Jul 03 07:16:50 PM PDT 24
Peak memory 201932 kb
Host smart-e557572d-7eca-4394-b590-e72c110ac726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173579675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.4173579675
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3880809820
Short name T374
Test name
Test status
Simulation time 398293533872 ps
CPU time 919.97 seconds
Started Jul 03 07:06:26 PM PDT 24
Finished Jul 03 07:21:47 PM PDT 24
Peak memory 201964 kb
Host smart-fb570e5f-362d-49b2-8205-89985b60804d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880809820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3880809820
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.606625512
Short name T372
Test name
Test status
Simulation time 88500429626 ps
CPU time 470.14 seconds
Started Jul 03 07:06:25 PM PDT 24
Finished Jul 03 07:14:17 PM PDT 24
Peak memory 202184 kb
Host smart-89f94ea1-219c-49de-94b9-7fa5f4256b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606625512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.606625512
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3453903450
Short name T426
Test name
Test status
Simulation time 43532904069 ps
CPU time 27.12 seconds
Started Jul 03 07:06:25 PM PDT 24
Finished Jul 03 07:06:54 PM PDT 24
Peak memory 201712 kb
Host smart-88f728eb-2dda-4b9a-ae87-9cd93a962867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453903450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3453903450
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.4117137181
Short name T746
Test name
Test status
Simulation time 4486751936 ps
CPU time 9.19 seconds
Started Jul 03 07:06:26 PM PDT 24
Finished Jul 03 07:06:36 PM PDT 24
Peak memory 201732 kb
Host smart-b3b21f0f-b1f9-4cf8-a679-bb36c316e782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117137181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.4117137181
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2047280523
Short name T634
Test name
Test status
Simulation time 5797019866 ps
CPU time 14.52 seconds
Started Jul 03 07:06:22 PM PDT 24
Finished Jul 03 07:06:38 PM PDT 24
Peak memory 201708 kb
Host smart-a7cae61f-62ad-4cb9-8f35-66fafda52a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047280523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2047280523
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2873849921
Short name T669
Test name
Test status
Simulation time 399879963175 ps
CPU time 362.49 seconds
Started Jul 03 07:06:29 PM PDT 24
Finished Jul 03 07:12:33 PM PDT 24
Peak memory 201868 kb
Host smart-8d8a9994-1bc9-4faa-8e3c-444b52a1ac18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873849921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2873849921
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3565415897
Short name T522
Test name
Test status
Simulation time 286146410 ps
CPU time 1.3 seconds
Started Jul 03 07:06:41 PM PDT 24
Finished Jul 03 07:06:44 PM PDT 24
Peak memory 201640 kb
Host smart-90adf2c7-900f-4067-926a-14d02b3f8ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565415897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3565415897
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1689537452
Short name T245
Test name
Test status
Simulation time 171971281028 ps
CPU time 106.95 seconds
Started Jul 03 07:06:37 PM PDT 24
Finished Jul 03 07:08:26 PM PDT 24
Peak memory 201944 kb
Host smart-fa57aabc-06d1-46ed-a0a1-e32567962c0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689537452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1689537452
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.517729783
Short name T158
Test name
Test status
Simulation time 167035358213 ps
CPU time 100.66 seconds
Started Jul 03 07:06:35 PM PDT 24
Finished Jul 03 07:08:17 PM PDT 24
Peak memory 201960 kb
Host smart-9ce02539-106a-4cd1-bc66-e31738a120bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517729783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.517729783
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3261008008
Short name T451
Test name
Test status
Simulation time 333704098791 ps
CPU time 183.61 seconds
Started Jul 03 07:06:38 PM PDT 24
Finished Jul 03 07:09:43 PM PDT 24
Peak memory 201900 kb
Host smart-d7f1ff25-3efc-4f57-9e18-c29f9cbac517
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261008008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3261008008
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.75854309
Short name T564
Test name
Test status
Simulation time 169749469029 ps
CPU time 98.19 seconds
Started Jul 03 07:06:29 PM PDT 24
Finished Jul 03 07:08:09 PM PDT 24
Peak memory 201996 kb
Host smart-b5041186-9e69-49f1-9c2e-b10ac43e6911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75854309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.75854309
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4238808439
Short name T435
Test name
Test status
Simulation time 165924523466 ps
CPU time 388.37 seconds
Started Jul 03 07:06:32 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 201904 kb
Host smart-021c0717-cc47-4558-addf-ff5c8caed0ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238808439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4238808439
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1310567398
Short name T159
Test name
Test status
Simulation time 509824758944 ps
CPU time 129.69 seconds
Started Jul 03 07:06:36 PM PDT 24
Finished Jul 03 07:08:47 PM PDT 24
Peak memory 202000 kb
Host smart-8412fe56-f135-4c4d-996c-6aaf4520cba7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310567398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1310567398
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3280262840
Short name T589
Test name
Test status
Simulation time 211158262708 ps
CPU time 428.76 seconds
Started Jul 03 07:06:34 PM PDT 24
Finished Jul 03 07:13:44 PM PDT 24
Peak memory 201904 kb
Host smart-0bc03c6e-4047-4648-8245-039f140bfa51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280262840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3280262840
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3096053594
Short name T482
Test name
Test status
Simulation time 94517627997 ps
CPU time 316.52 seconds
Started Jul 03 07:06:40 PM PDT 24
Finished Jul 03 07:11:58 PM PDT 24
Peak memory 202196 kb
Host smart-18457998-48c1-4d74-b1ee-02f63a07474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096053594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3096053594
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.841805457
Short name T565
Test name
Test status
Simulation time 40744918826 ps
CPU time 77.42 seconds
Started Jul 03 07:06:42 PM PDT 24
Finished Jul 03 07:08:01 PM PDT 24
Peak memory 201696 kb
Host smart-cb15a7c1-046e-400d-89b1-9a8e8f35668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841805457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.841805457
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2512056391
Short name T455
Test name
Test status
Simulation time 5449877520 ps
CPU time 1.64 seconds
Started Jul 03 07:06:36 PM PDT 24
Finished Jul 03 07:06:39 PM PDT 24
Peak memory 201692 kb
Host smart-da1586fa-455d-40ce-a490-ab23446899a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512056391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2512056391
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4008447056
Short name T407
Test name
Test status
Simulation time 5694510602 ps
CPU time 4.43 seconds
Started Jul 03 07:06:30 PM PDT 24
Finished Jul 03 07:06:35 PM PDT 24
Peak memory 201572 kb
Host smart-785fa728-0295-412b-8979-0bd34b14b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008447056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4008447056
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2804711151
Short name T322
Test name
Test status
Simulation time 209897488848 ps
CPU time 128.84 seconds
Started Jul 03 07:06:40 PM PDT 24
Finished Jul 03 07:08:51 PM PDT 24
Peak memory 201952 kb
Host smart-1742cce2-81cf-4c38-aed2-a7c9f9e641b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804711151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2804711151
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3007509723
Short name T492
Test name
Test status
Simulation time 500391368984 ps
CPU time 158.54 seconds
Started Jul 03 07:06:41 PM PDT 24
Finished Jul 03 07:09:21 PM PDT 24
Peak memory 202036 kb
Host smart-0c32798b-c800-4c20-88dd-0413883e01c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007509723 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3007509723
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.333936066
Short name T501
Test name
Test status
Simulation time 398560768 ps
CPU time 1.58 seconds
Started Jul 03 07:06:54 PM PDT 24
Finished Jul 03 07:06:57 PM PDT 24
Peak memory 201648 kb
Host smart-360f760f-136c-4037-94c1-6e9bc66c6466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333936066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.333936066
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.133284984
Short name T235
Test name
Test status
Simulation time 183459642468 ps
CPU time 96.56 seconds
Started Jul 03 07:06:45 PM PDT 24
Finished Jul 03 07:08:23 PM PDT 24
Peak memory 201964 kb
Host smart-6009f147-7d58-46aa-aa97-dbe666d002da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133284984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.133284984
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4086480765
Short name T542
Test name
Test status
Simulation time 324263331485 ps
CPU time 456.01 seconds
Started Jul 03 07:06:46 PM PDT 24
Finished Jul 03 07:14:23 PM PDT 24
Peak memory 201876 kb
Host smart-967600cb-cbaa-445d-b011-8852191263fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086480765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4086480765
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3303555638
Short name T778
Test name
Test status
Simulation time 333163272100 ps
CPU time 785.04 seconds
Started Jul 03 07:06:44 PM PDT 24
Finished Jul 03 07:19:50 PM PDT 24
Peak memory 201876 kb
Host smart-2a1567b2-055e-4c6a-989d-dddc6f898c5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303555638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3303555638
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3103869785
Short name T680
Test name
Test status
Simulation time 324610651917 ps
CPU time 679.38 seconds
Started Jul 03 07:06:40 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 201952 kb
Host smart-b5c37406-87ec-4903-a07e-28798c0036cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103869785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3103869785
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.754455398
Short name T376
Test name
Test status
Simulation time 333397743714 ps
CPU time 378.63 seconds
Started Jul 03 07:06:41 PM PDT 24
Finished Jul 03 07:13:02 PM PDT 24
Peak memory 201872 kb
Host smart-dcf3296e-4a4e-4478-b17f-6c2ffa226837
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=754455398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.754455398
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2805326649
Short name T287
Test name
Test status
Simulation time 360626660918 ps
CPU time 197.84 seconds
Started Jul 03 07:06:47 PM PDT 24
Finished Jul 03 07:10:05 PM PDT 24
Peak memory 201956 kb
Host smart-e341e7d8-94b2-431e-9d38-cc63257d91f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805326649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2805326649
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2649562136
Short name T513
Test name
Test status
Simulation time 204377853961 ps
CPU time 459.55 seconds
Started Jul 03 07:06:46 PM PDT 24
Finished Jul 03 07:14:27 PM PDT 24
Peak memory 201976 kb
Host smart-cde812a9-ccf7-43ef-a796-6c0a8c36ebf4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649562136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2649562136
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.770794864
Short name T616
Test name
Test status
Simulation time 97318198633 ps
CPU time 505.49 seconds
Started Jul 03 07:06:55 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 202236 kb
Host smart-ad686b6b-a7af-4158-a4de-7b5bed4a6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770794864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.770794864
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1500506882
Short name T380
Test name
Test status
Simulation time 33073114126 ps
CPU time 40.72 seconds
Started Jul 03 07:06:48 PM PDT 24
Finished Jul 03 07:07:30 PM PDT 24
Peak memory 201680 kb
Host smart-6a619595-e038-4cc5-bbbb-82d098428ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500506882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1500506882
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1436882336
Short name T631
Test name
Test status
Simulation time 4952002812 ps
CPU time 3.57 seconds
Started Jul 03 07:06:48 PM PDT 24
Finished Jul 03 07:06:52 PM PDT 24
Peak memory 201732 kb
Host smart-f8303235-b36d-4619-8d33-9629c4044936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436882336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1436882336
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.690951094
Short name T107
Test name
Test status
Simulation time 5843591986 ps
CPU time 7.59 seconds
Started Jul 03 07:06:41 PM PDT 24
Finished Jul 03 07:06:51 PM PDT 24
Peak memory 201736 kb
Host smart-623b366a-b576-472a-bb26-cea73b1c757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690951094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.690951094
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.299053188
Short name T306
Test name
Test status
Simulation time 226798901550 ps
CPU time 126.07 seconds
Started Jul 03 07:06:54 PM PDT 24
Finished Jul 03 07:09:02 PM PDT 24
Peak memory 201968 kb
Host smart-bcb376bd-82a6-4eda-92d1-984e595fe814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299053188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
299053188
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1013530798
Short name T497
Test name
Test status
Simulation time 432321082 ps
CPU time 0.9 seconds
Started Jul 03 06:52:38 PM PDT 24
Finished Jul 03 06:52:39 PM PDT 24
Peak memory 201680 kb
Host smart-bf91c841-9e5b-4f74-a999-96c8d5c58627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013530798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1013530798
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1235442876
Short name T698
Test name
Test status
Simulation time 534316771746 ps
CPU time 244.38 seconds
Started Jul 03 06:52:29 PM PDT 24
Finished Jul 03 06:56:33 PM PDT 24
Peak memory 201892 kb
Host smart-014e17e6-4d64-47d8-83be-f54405d1ffb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235442876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1235442876
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2101916740
Short name T329
Test name
Test status
Simulation time 376357426184 ps
CPU time 846.88 seconds
Started Jul 03 06:52:29 PM PDT 24
Finished Jul 03 07:06:37 PM PDT 24
Peak memory 201876 kb
Host smart-f4c0642b-ba35-4136-95da-277a5ea010dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101916740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2101916740
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2960800670
Short name T487
Test name
Test status
Simulation time 485217341181 ps
CPU time 994.67 seconds
Started Jul 03 06:52:28 PM PDT 24
Finished Jul 03 07:09:03 PM PDT 24
Peak memory 201928 kb
Host smart-2be20cf3-738e-4834-9e84-4f4da27e81d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960800670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2960800670
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.548339388
Short name T217
Test name
Test status
Simulation time 166122475738 ps
CPU time 176.65 seconds
Started Jul 03 06:52:25 PM PDT 24
Finished Jul 03 06:55:22 PM PDT 24
Peak memory 201992 kb
Host smart-38566a89-f047-4c26-b1cf-35ff52010288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548339388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.548339388
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.120738893
Short name T385
Test name
Test status
Simulation time 164664662584 ps
CPU time 192.79 seconds
Started Jul 03 06:52:27 PM PDT 24
Finished Jul 03 06:55:40 PM PDT 24
Peak memory 201912 kb
Host smart-d5175af2-8617-431f-9a6d-2a61aebf161f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=120738893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.120738893
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1484847184
Short name T171
Test name
Test status
Simulation time 613546108389 ps
CPU time 121.67 seconds
Started Jul 03 06:52:29 PM PDT 24
Finished Jul 03 06:54:31 PM PDT 24
Peak memory 201952 kb
Host smart-0090f616-f694-46f8-9eb1-80b50e9ad4fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484847184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1484847184
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3591329259
Short name T405
Test name
Test status
Simulation time 208187121457 ps
CPU time 33.57 seconds
Started Jul 03 06:52:28 PM PDT 24
Finished Jul 03 06:53:02 PM PDT 24
Peak memory 201960 kb
Host smart-d184dabe-3e9b-46ef-b0a8-9e6ab0814453
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591329259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3591329259
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1948545512
Short name T684
Test name
Test status
Simulation time 122442545496 ps
CPU time 682.6 seconds
Started Jul 03 06:52:34 PM PDT 24
Finished Jul 03 07:03:57 PM PDT 24
Peak memory 202272 kb
Host smart-92656333-43b8-4631-9ff8-e066a3c3982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948545512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1948545512
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1627787403
Short name T728
Test name
Test status
Simulation time 27592097228 ps
CPU time 64.43 seconds
Started Jul 03 06:52:33 PM PDT 24
Finished Jul 03 06:53:38 PM PDT 24
Peak memory 201712 kb
Host smart-e5fda289-0307-4036-b599-82f1d2ff5a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627787403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1627787403
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1368676332
Short name T624
Test name
Test status
Simulation time 4139043122 ps
CPU time 9.51 seconds
Started Jul 03 06:52:36 PM PDT 24
Finished Jul 03 06:52:46 PM PDT 24
Peak memory 201720 kb
Host smart-98302682-f576-4332-9dc9-20550e922c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368676332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1368676332
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.248951729
Short name T793
Test name
Test status
Simulation time 6088693101 ps
CPU time 2.27 seconds
Started Jul 03 06:52:19 PM PDT 24
Finished Jul 03 06:52:22 PM PDT 24
Peak memory 201744 kb
Host smart-4095bb01-65d9-472d-b872-fd3eea1f42d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248951729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.248951729
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2937366235
Short name T320
Test name
Test status
Simulation time 210177592875 ps
CPU time 134.45 seconds
Started Jul 03 06:52:37 PM PDT 24
Finished Jul 03 06:54:52 PM PDT 24
Peak memory 201836 kb
Host smart-e1fd507a-9abb-4b0a-9d39-5f302979ccf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937366235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2937366235
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1062387061
Short name T479
Test name
Test status
Simulation time 124850981071 ps
CPU time 142.82 seconds
Started Jul 03 06:52:34 PM PDT 24
Finished Jul 03 06:54:57 PM PDT 24
Peak memory 210544 kb
Host smart-65f04c4c-e6a6-4806-9d8a-db22c3cd985f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062387061 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1062387061
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1810658846
Short name T353
Test name
Test status
Simulation time 506898883 ps
CPU time 1.74 seconds
Started Jul 03 06:53:10 PM PDT 24
Finished Jul 03 06:53:12 PM PDT 24
Peak memory 201680 kb
Host smart-7fd726d7-82e4-44d6-8f6d-5c614e305477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810658846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1810658846
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.932093572
Short name T509
Test name
Test status
Simulation time 265059878650 ps
CPU time 11.71 seconds
Started Jul 03 06:53:01 PM PDT 24
Finished Jul 03 06:53:13 PM PDT 24
Peak memory 201904 kb
Host smart-efd600fd-1f38-4509-89d5-063ccf6b21a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932093572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.932093572
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.864359222
Short name T545
Test name
Test status
Simulation time 182798235034 ps
CPU time 110.14 seconds
Started Jul 03 06:52:54 PM PDT 24
Finished Jul 03 06:54:45 PM PDT 24
Peak memory 201928 kb
Host smart-97f6af2d-f978-4e2f-8a5b-12c28a673f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864359222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.864359222
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1076617953
Short name T681
Test name
Test status
Simulation time 489046142592 ps
CPU time 554.84 seconds
Started Jul 03 06:52:42 PM PDT 24
Finished Jul 03 07:01:58 PM PDT 24
Peak memory 201908 kb
Host smart-58101c5b-218a-497a-a9ae-cc80038a9efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076617953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1076617953
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4186063075
Short name T438
Test name
Test status
Simulation time 162382679756 ps
CPU time 40.68 seconds
Started Jul 03 06:52:41 PM PDT 24
Finished Jul 03 06:53:23 PM PDT 24
Peak memory 201904 kb
Host smart-b28f85fe-5b3b-40e5-aa46-3a9446dfd8c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186063075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4186063075
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2517710781
Short name T467
Test name
Test status
Simulation time 168648715905 ps
CPU time 196.69 seconds
Started Jul 03 06:52:42 PM PDT 24
Finished Jul 03 06:55:59 PM PDT 24
Peak memory 201996 kb
Host smart-4d9f5242-87d9-4d15-9a0f-d42bf155e5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517710781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2517710781
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2724249932
Short name T402
Test name
Test status
Simulation time 168544232046 ps
CPU time 372.78 seconds
Started Jul 03 06:52:43 PM PDT 24
Finished Jul 03 06:58:56 PM PDT 24
Peak memory 201912 kb
Host smart-bde01c50-5899-426d-94b9-1d9f327925c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724249932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2724249932
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3785950327
Short name T252
Test name
Test status
Simulation time 182619641733 ps
CPU time 226.78 seconds
Started Jul 03 06:52:50 PM PDT 24
Finished Jul 03 06:56:37 PM PDT 24
Peak memory 201932 kb
Host smart-adb85953-e075-4c86-b1a8-3cf2dae6b1d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785950327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3785950327
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1640968874
Short name T94
Test name
Test status
Simulation time 391835344436 ps
CPU time 809.44 seconds
Started Jul 03 06:52:56 PM PDT 24
Finished Jul 03 07:06:26 PM PDT 24
Peak memory 201872 kb
Host smart-061c398d-d40b-40ee-8060-8ed52ad91a3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640968874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1640968874
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2500284974
Short name T200
Test name
Test status
Simulation time 144098124160 ps
CPU time 392.23 seconds
Started Jul 03 06:53:02 PM PDT 24
Finished Jul 03 06:59:35 PM PDT 24
Peak memory 202180 kb
Host smart-39890047-77a6-4ab4-b0a4-1a5302a49de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500284974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2500284974
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2619756868
Short name T427
Test name
Test status
Simulation time 31196063435 ps
CPU time 13.92 seconds
Started Jul 03 06:53:01 PM PDT 24
Finished Jul 03 06:53:16 PM PDT 24
Peak memory 201684 kb
Host smart-98c739d7-6d55-4151-b797-b6f412c68166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619756868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2619756868
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3050364808
Short name T761
Test name
Test status
Simulation time 3023505866 ps
CPU time 2.24 seconds
Started Jul 03 06:53:01 PM PDT 24
Finished Jul 03 06:53:03 PM PDT 24
Peak memory 201732 kb
Host smart-8c86c92e-6c64-4c55-8751-65121fa36049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050364808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3050364808
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.747429850
Short name T699
Test name
Test status
Simulation time 5716213894 ps
CPU time 13.23 seconds
Started Jul 03 06:52:41 PM PDT 24
Finished Jul 03 06:52:55 PM PDT 24
Peak memory 201736 kb
Host smart-c8a2c315-a1c7-4e36-8d78-c12329777251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747429850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.747429850
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3530629158
Short name T35
Test name
Test status
Simulation time 199517257863 ps
CPU time 61.24 seconds
Started Jul 03 06:53:09 PM PDT 24
Finished Jul 03 06:54:11 PM PDT 24
Peak memory 201984 kb
Host smart-84559edb-102b-45e8-8410-4cf18770ea63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530629158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3530629158
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4053565390
Short name T601
Test name
Test status
Simulation time 103317051240 ps
CPU time 124.21 seconds
Started Jul 03 06:53:05 PM PDT 24
Finished Jul 03 06:55:10 PM PDT 24
Peak memory 210256 kb
Host smart-639216a3-664d-41dd-877c-648b98cc2c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053565390 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4053565390
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3559338879
Short name T369
Test name
Test status
Simulation time 330252203 ps
CPU time 1.02 seconds
Started Jul 03 06:53:40 PM PDT 24
Finished Jul 03 06:53:41 PM PDT 24
Peak memory 201672 kb
Host smart-9f8da1fa-10f0-4feb-a657-d54530dc8789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559338879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3559338879
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4142726091
Short name T333
Test name
Test status
Simulation time 167361411877 ps
CPU time 372.4 seconds
Started Jul 03 06:53:30 PM PDT 24
Finished Jul 03 06:59:42 PM PDT 24
Peak memory 201996 kb
Host smart-fafadd69-6e52-4e05-bb6d-78d4a2ba4676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142726091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4142726091
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.958007328
Short name T313
Test name
Test status
Simulation time 160818576262 ps
CPU time 56.81 seconds
Started Jul 03 06:53:21 PM PDT 24
Finished Jul 03 06:54:18 PM PDT 24
Peak memory 201844 kb
Host smart-c7cda4ac-d3f4-4e84-931d-f87c932f6355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958007328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.958007328
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.25929291
Short name T700
Test name
Test status
Simulation time 332281839926 ps
CPU time 714.9 seconds
Started Jul 03 06:53:24 PM PDT 24
Finished Jul 03 07:05:19 PM PDT 24
Peak memory 201916 kb
Host smart-1fce2057-2993-4284-8b50-cf058a8f0b57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=25929291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_
fixed.25929291
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2232559367
Short name T441
Test name
Test status
Simulation time 499041338853 ps
CPU time 1075.15 seconds
Started Jul 03 06:53:17 PM PDT 24
Finished Jul 03 07:11:12 PM PDT 24
Peak memory 201956 kb
Host smart-ce9f03e3-760e-441b-8186-793f3ffb94ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232559367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2232559367
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2003467084
Short name T366
Test name
Test status
Simulation time 481197901316 ps
CPU time 567.61 seconds
Started Jul 03 06:53:23 PM PDT 24
Finished Jul 03 07:02:52 PM PDT 24
Peak memory 201980 kb
Host smart-7a8aee51-ce93-419f-bd18-c7cf7153a9e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003467084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2003467084
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.882107014
Short name T248
Test name
Test status
Simulation time 175593281382 ps
CPU time 108.96 seconds
Started Jul 03 06:53:23 PM PDT 24
Finished Jul 03 06:55:13 PM PDT 24
Peak memory 201916 kb
Host smart-accd5547-4f76-4ac4-8d14-d690ac042106
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882107014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.882107014
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2892885845
Short name T151
Test name
Test status
Simulation time 196307600845 ps
CPU time 92.32 seconds
Started Jul 03 06:53:26 PM PDT 24
Finished Jul 03 06:54:59 PM PDT 24
Peak memory 201892 kb
Host smart-92b49187-cc0f-45f5-94cf-9e32793de160
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892885845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2892885845
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3251602029
Short name T204
Test name
Test status
Simulation time 91423825417 ps
CPU time 516.04 seconds
Started Jul 03 06:53:36 PM PDT 24
Finished Jul 03 07:02:12 PM PDT 24
Peak memory 202280 kb
Host smart-6b345c7a-d840-4a8e-9315-d5521eb2be86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251602029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3251602029
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1633861038
Short name T781
Test name
Test status
Simulation time 37810731665 ps
CPU time 21.24 seconds
Started Jul 03 06:53:32 PM PDT 24
Finished Jul 03 06:53:54 PM PDT 24
Peak memory 201692 kb
Host smart-ca3e1f23-c885-4c21-825a-96ce93290e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633861038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1633861038
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4189979282
Short name T118
Test name
Test status
Simulation time 3581693918 ps
CPU time 1.65 seconds
Started Jul 03 06:53:31 PM PDT 24
Finished Jul 03 06:53:33 PM PDT 24
Peak memory 201696 kb
Host smart-90ee8b58-ebe6-4f04-8f5d-145b36168210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189979282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4189979282
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.930754670
Short name T523
Test name
Test status
Simulation time 5696996877 ps
CPU time 12.74 seconds
Started Jul 03 06:53:15 PM PDT 24
Finished Jul 03 06:53:28 PM PDT 24
Peak memory 201724 kb
Host smart-39fa9709-c2ec-4b58-8aaf-fd6c0ee6e409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930754670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.930754670
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.698918324
Short name T759
Test name
Test status
Simulation time 13245307160 ps
CPU time 8.94 seconds
Started Jul 03 06:53:41 PM PDT 24
Finished Jul 03 06:53:50 PM PDT 24
Peak memory 201720 kb
Host smart-bc40c56e-b3c7-45fa-bcd5-ee8367c97fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698918324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.698918324
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2248929884
Short name T293
Test name
Test status
Simulation time 39558664217 ps
CPU time 81.51 seconds
Started Jul 03 06:53:39 PM PDT 24
Finished Jul 03 06:55:01 PM PDT 24
Peak memory 210272 kb
Host smart-ef75e5c8-eac2-4801-9c7f-55b8a9134e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248929884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2248929884
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3262179967
Short name T400
Test name
Test status
Simulation time 367096120 ps
CPU time 0.85 seconds
Started Jul 03 06:54:03 PM PDT 24
Finished Jul 03 06:54:04 PM PDT 24
Peak memory 201652 kb
Host smart-0bf656cc-ab0c-475c-a7de-add22306ab72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262179967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3262179967
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1204712766
Short name T533
Test name
Test status
Simulation time 355958761156 ps
CPU time 808.56 seconds
Started Jul 03 06:53:48 PM PDT 24
Finished Jul 03 07:07:17 PM PDT 24
Peak memory 201892 kb
Host smart-211ebb69-34c6-4e20-90ba-f25748d3ec74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204712766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1204712766
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2365526325
Short name T772
Test name
Test status
Simulation time 165981200036 ps
CPU time 349.23 seconds
Started Jul 03 06:53:45 PM PDT 24
Finished Jul 03 06:59:35 PM PDT 24
Peak memory 201920 kb
Host smart-64b0b71b-a1cc-46d2-a8ea-bdd87df4941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365526325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2365526325
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.314596820
Short name T360
Test name
Test status
Simulation time 326303300718 ps
CPU time 771.94 seconds
Started Jul 03 06:53:45 PM PDT 24
Finished Jul 03 07:06:38 PM PDT 24
Peak memory 201908 kb
Host smart-a682caf4-08bf-456a-bb69-ca858334b61a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=314596820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.314596820
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1375212387
Short name T251
Test name
Test status
Simulation time 324540454915 ps
CPU time 695.3 seconds
Started Jul 03 06:53:39 PM PDT 24
Finished Jul 03 07:05:15 PM PDT 24
Peak memory 201936 kb
Host smart-cd1f6f42-907a-45bd-8304-365bf9006d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375212387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1375212387
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1757383545
Short name T574
Test name
Test status
Simulation time 484356851936 ps
CPU time 573.56 seconds
Started Jul 03 06:53:45 PM PDT 24
Finished Jul 03 07:03:19 PM PDT 24
Peak memory 201948 kb
Host smart-89f3d59d-4735-4a64-a4d3-e1117cc4a56d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757383545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1757383545
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3390747170
Short name T221
Test name
Test status
Simulation time 334490561481 ps
CPU time 672.22 seconds
Started Jul 03 06:53:49 PM PDT 24
Finished Jul 03 07:05:02 PM PDT 24
Peak memory 201944 kb
Host smart-26e767cc-7cfd-42fa-85b8-55ab23ef5118
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390747170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3390747170
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1453446181
Short name T468
Test name
Test status
Simulation time 401492680857 ps
CPU time 453.1 seconds
Started Jul 03 06:53:48 PM PDT 24
Finished Jul 03 07:01:22 PM PDT 24
Peak memory 201904 kb
Host smart-46b17ce8-f903-465a-87b5-44425e7e8d4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453446181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1453446181
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.52284477
Short name T201
Test name
Test status
Simulation time 83674083972 ps
CPU time 371.21 seconds
Started Jul 03 06:53:58 PM PDT 24
Finished Jul 03 07:00:09 PM PDT 24
Peak memory 202236 kb
Host smart-e9506568-ee24-441e-9e87-46a0989d58e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52284477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.52284477
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.956969046
Short name T393
Test name
Test status
Simulation time 32467539998 ps
CPU time 39.26 seconds
Started Jul 03 06:54:00 PM PDT 24
Finished Jul 03 06:54:39 PM PDT 24
Peak memory 201700 kb
Host smart-942e5e98-5f01-4209-bc3b-36cd9fad97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956969046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.956969046
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.812662250
Short name T623
Test name
Test status
Simulation time 3637507526 ps
CPU time 5.5 seconds
Started Jul 03 06:53:52 PM PDT 24
Finished Jul 03 06:53:58 PM PDT 24
Peak memory 201732 kb
Host smart-95cf61b5-5617-40b3-922d-db07040487e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812662250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.812662250
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1146873414
Short name T731
Test name
Test status
Simulation time 5518154041 ps
CPU time 15.18 seconds
Started Jul 03 06:53:40 PM PDT 24
Finished Jul 03 06:53:56 PM PDT 24
Peak memory 201728 kb
Host smart-1a892348-d2bc-405f-9945-bf59edee9dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146873414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1146873414
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2643541304
Short name T575
Test name
Test status
Simulation time 514378416107 ps
CPU time 969.03 seconds
Started Jul 03 06:54:02 PM PDT 24
Finished Jul 03 07:10:12 PM PDT 24
Peak memory 212928 kb
Host smart-e35b9a7f-e76d-4156-b927-4bd5e6e71dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643541304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2643541304
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3894163062
Short name T580
Test name
Test status
Simulation time 269000743460 ps
CPU time 212.69 seconds
Started Jul 03 06:53:57 PM PDT 24
Finished Jul 03 06:57:30 PM PDT 24
Peak memory 218716 kb
Host smart-07f1c27f-13bd-44ed-8412-1b79cce9c21c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894163062 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3894163062
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1466370107
Short name T784
Test name
Test status
Simulation time 494651345 ps
CPU time 0.83 seconds
Started Jul 03 06:54:31 PM PDT 24
Finished Jul 03 06:54:32 PM PDT 24
Peak memory 201672 kb
Host smart-c4dcfdd5-d1c8-4fba-b205-8165ada2346c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466370107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1466370107
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2961529894
Short name T318
Test name
Test status
Simulation time 329613135089 ps
CPU time 702.92 seconds
Started Jul 03 06:54:17 PM PDT 24
Finished Jul 03 07:06:01 PM PDT 24
Peak memory 201896 kb
Host smart-557fb5a3-b841-4a1c-b9ca-0d0f34279c24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961529894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2961529894
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2628671809
Short name T556
Test name
Test status
Simulation time 165260387540 ps
CPU time 41.55 seconds
Started Jul 03 06:54:18 PM PDT 24
Finished Jul 03 06:55:00 PM PDT 24
Peak memory 201888 kb
Host smart-efb817b8-45a0-4627-ae4e-b47164eb6e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628671809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2628671809
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.622732045
Short name T702
Test name
Test status
Simulation time 163036781187 ps
CPU time 366.14 seconds
Started Jul 03 06:54:03 PM PDT 24
Finished Jul 03 07:00:10 PM PDT 24
Peak memory 201852 kb
Host smart-0ffcafef-1372-4326-8f30-81195afc7344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622732045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.622732045
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.367725420
Short name T97
Test name
Test status
Simulation time 161178350703 ps
CPU time 353.65 seconds
Started Jul 03 06:54:08 PM PDT 24
Finished Jul 03 07:00:02 PM PDT 24
Peak memory 201904 kb
Host smart-4e2417cd-f678-4a5b-bd70-c7b7210a040f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=367725420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.367725420
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2366167430
Short name T324
Test name
Test status
Simulation time 488289042882 ps
CPU time 574.78 seconds
Started Jul 03 06:54:03 PM PDT 24
Finished Jul 03 07:03:38 PM PDT 24
Peak memory 201928 kb
Host smart-70b565a7-040d-4a21-afc6-41a30bccbe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366167430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2366167430
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1265639428
Short name T763
Test name
Test status
Simulation time 321165062099 ps
CPU time 693.97 seconds
Started Jul 03 06:54:03 PM PDT 24
Finished Jul 03 07:05:38 PM PDT 24
Peak memory 201968 kb
Host smart-fbbdd226-443a-4f9d-a602-67b5bc250d16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265639428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1265639428
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2231625784
Short name T730
Test name
Test status
Simulation time 341995051256 ps
CPU time 200.31 seconds
Started Jul 03 06:54:12 PM PDT 24
Finished Jul 03 06:57:33 PM PDT 24
Peak memory 201920 kb
Host smart-c40e15fd-99dc-42b2-94ba-a541f18f8a85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231625784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2231625784
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2225652747
Short name T760
Test name
Test status
Simulation time 205280129127 ps
CPU time 478.08 seconds
Started Jul 03 06:54:12 PM PDT 24
Finished Jul 03 07:02:11 PM PDT 24
Peak memory 201796 kb
Host smart-fb8dd753-0d81-4778-aabd-2d7935ae32c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225652747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2225652747
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2383317315
Short name T764
Test name
Test status
Simulation time 39820512985 ps
CPU time 21.57 seconds
Started Jul 03 06:54:17 PM PDT 24
Finished Jul 03 06:54:39 PM PDT 24
Peak memory 201676 kb
Host smart-b75228bf-6d46-4c7a-99df-e0dbb7023e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383317315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2383317315
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1820388541
Short name T787
Test name
Test status
Simulation time 4082438994 ps
CPU time 3.04 seconds
Started Jul 03 06:54:16 PM PDT 24
Finished Jul 03 06:54:19 PM PDT 24
Peak memory 201700 kb
Host smart-310d7212-707a-4979-aa6f-260526336ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820388541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1820388541
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3949306989
Short name T725
Test name
Test status
Simulation time 5934415928 ps
CPU time 14.85 seconds
Started Jul 03 06:54:02 PM PDT 24
Finished Jul 03 06:54:18 PM PDT 24
Peak memory 201736 kb
Host smart-45448047-5923-493f-94f4-525d51d49ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949306989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3949306989
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2463795708
Short name T273
Test name
Test status
Simulation time 335565095860 ps
CPU time 392.5 seconds
Started Jul 03 06:54:30 PM PDT 24
Finished Jul 03 07:01:03 PM PDT 24
Peak memory 201896 kb
Host smart-ce530915-8bab-42eb-894a-653d8cf5e284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463795708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2463795708
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2595379132
Short name T112
Test name
Test status
Simulation time 60166380245 ps
CPU time 98.62 seconds
Started Jul 03 06:54:26 PM PDT 24
Finished Jul 03 06:56:05 PM PDT 24
Peak memory 210236 kb
Host smart-367e3af7-973f-4650-ac8e-0a984b25e5a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595379132 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2595379132
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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