Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6692	1			T1	4		T7	4		T10	20
testmodes[AdcCtrlTestmodeNormal]	5481	1			T1	8		T2	3		T3	2
testmodes[AdcCtrlTestmodeLowpower]	5893	1			T8	1		T9	19		T13	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3583	1			T7	2		T10	19		T109	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1700	1			T1	4		T7	2		T54	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1308	1			T54	15		T35	19		T45	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1747	1			T1	3		T7	2		T54	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1994	1			T1	4		T2	2		T3	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1398	1			T54	13		T34	1		T35	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1253	1			T54	15		T35	17		T45	8
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1450	1			T54	13		T51	1		T35	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2935	1			T9	18		T13	1		T56	18