Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22727

1

T1

12

T2

3

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

4040

1

T3

27

T6

15

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20167

1

T1

12

T7

10

T9

19

auto[1]

6600

1

T2

3

T3

36

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9	1			T229	5		T230	1		T231	2
values[1]	596	1			T3	27		T51	29		T25	27
values[2]	2965	1			T2	3		T5	15		T11	19
values[3]	1049	1			T4	11		T136	1		T158	30
values[4]	886	1			T3	9		T50	39		T51	2
values[5]	738	1			T25	32		T140	11		T138	61
values[6]	629	1			T4	3		T12	1		T137	7
values[7]	705	1			T6	22		T12	1		T137	19
values[8]	873	1			T158	24		T32	11		T33	3
values[9]	1185	1			T8	19		T12	1		T42	7
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	691	1			T3	27		T51	29		T25	27
values[1]	3257	1			T2	3		T5	15		T11	19
values[2]	899	1			T4	11		T51	2		T136	1
values[3]	889	1			T3	9		T50	39		T25	32
values[4]	653	1			T137	7		T140	11		T138	34
values[5]	608	1			T4	3		T12	2		T137	19
values[6]	789	1			T6	22		T32	13		T138	27
values[7]	854	1			T158	24		T33	3		T157	13
values[8]	856	1			T42	7		T136	1		T45	8
values[9]	139	1			T8	19		T12	1		T57	5
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T51	13		T140	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	14		T25	12		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1757	1			T2	3		T5	1		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T144	2		T149	3		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	1		T51	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T158	17		T15	10		T130	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	5		T142	14		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T50	20		T25	17		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	1		T138	17		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	5		T46	2		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T12	2		T137	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T142	5		T233	7		T150	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T32	1		T138	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T135	17		T234	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T158	13		T33	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	1		T232	12		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T32	1		T139	1		T131	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T42	7		T136	1		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T57	1		T235	1		T173	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T8	19		T12	1		T236	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T51	16		T140	4		T142	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	13		T25	15		T147	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T5	14		T11	17		T14	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T144	23		T149	11		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	10		T51	1		T131	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T158	13		T15	9		T130	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	4		T142	15		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T50	19		T25	15		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T140	10		T138	17		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T137	2		T46	1		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	2		T137	9		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T142	4		T233	5		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	6		T32	12		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	14		T135	11		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	11		T157	12		T49	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T232	18		T160	11		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T32	10		T131	9		T170	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	2		T130	11		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T57	4		T238	1		T197	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T239	1		T240	1		T106	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T229	4		T230	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T51	13		T140	1		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	14		T25	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1726	1			T2	3		T5	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T144	1		T172	12		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	1		T136	1		T199	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T158	17		T243	10		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	5		T51	1		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T50	20		T15	10		T46	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	1		T138	17		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T25	17		T138	14		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	1		T12	1		T33	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T137	5		T233	7		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T12	1		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	1		T142	5		T135	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T158	13		T32	1		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	1		T160	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T139	1		T57	1		T131	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T8	19		T12	1		T42	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T51	16		T140	4		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	13		T25	15		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T5	14		T11	17		T14	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T144	13		T245	10		T211	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	10		T199	7		T164	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T158	13		T243	12		T130	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	4		T51	1		T142	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T50	19		T15	9		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	10		T138	17		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T25	15		T138	13		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	2		T140	2		T145	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T137	2		T233	5		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	6		T137	9		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	14		T142	4		T135	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	11		T32	10		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T160	11		T244	15		T152	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T57	4		T131	9		T170	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T45	2		T130	11		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T51	17		T140	5		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	14		T25	16		T147	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T2	3		T5	15		T11	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T144	25		T149	12		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	11		T51	2		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T158	14		T15	12		T130	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	5		T142	16		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T50	21		T25	16		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T140	11		T138	18		T143	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T137	3		T46	2		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	3		T12	2		T137	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T142	5		T233	6		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	7		T32	13		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	15		T135	12		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T158	12		T33	1		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T148	1		T232	19		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	11		T139	1		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T42	1		T136	1		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T57	5		T235	1		T173	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T8	1		T12	1		T236	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T51	12		T142	11		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	13		T25	11		T47	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T13	23		T52	10		T40	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T149	2		T232	14		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T131	12		T48	1		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T158	16		T15	7		T130	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	4		T142	13		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	18		T25	16		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	16		T247	7		T248	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T137	4		T46	1		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T137	9		T33	12		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T142	4		T233	6		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	15		T150	15		T234	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	16		T234	12		T92	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T158	12		T33	2		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T232	11		T152	10		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T131	14		T250	15		T200	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T42	6		T45	2		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T210	7		T197	9		T251	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T8	18		T236	14		T106	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T231	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T229	4		T230	1		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T51	17		T140	5		T142	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	14		T25	16		T147	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T2	3		T5	15		T11	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T144	14		T172	1		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	11		T136	1		T199	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T158	14		T243	13		T130	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	5		T51	2		T142	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T50	21		T15	12		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T140	11		T138	18		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T25	16		T138	14		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	3		T12	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	3		T233	6		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	7		T12	1		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	15		T142	5		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T158	12		T32	11		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T148	1		T160	12		T244	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T139	1		T57	5		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T8	1		T12	1		T42	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T231	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T51	12		T142	11		T130	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	13		T25	11		T47	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T13	23		T52	10		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T172	11		T252	12		T210	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T199	6		T253	11		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T158	16		T243	9		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	4		T142	13		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	18		T15	7		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T138	16		T248	1		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	16		T138	13		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	12		T17	3		T91	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	4		T233	6		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T137	9		T138	15		T234	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T142	4		T135	16		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T158	12		T33	2		T150	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T152	10		T249	8		T255	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T131	14		T250	15		T200	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T8	18		T42	6		T45	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23232

1

T1

12

T2

3

T3

36

auto[ADC_CTRL_FILTER_COND_OUT]

3535

1

T12

2

T50

18

T51

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20233

1

T1

12

T4

3

T7

10

auto[1]

6534

1

T2

3

T3

36

T4

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	298	1			T158	24		T150	3		T256	25
values[1]	568	1			T12	2		T25	32		T149	11
values[2]	515	1			T3	9		T46	4		T47	6
values[3]	694	1			T4	11		T50	21		T136	1
values[4]	690	1			T33	3		T140	5		T142	27
values[5]	3156	1			T2	3		T3	27		T4	3
values[6]	640	1			T50	18		T51	2		T42	7
values[7]	925	1			T6	22		T33	13		T138	61
values[8]	794	1			T137	19		T142	29		T139	1
values[9]	1355	1			T8	19		T12	1		T51	29
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	500	1			T12	1		T25	32		T149	11
values[1]	562	1			T3	9		T4	11		T46	4
values[2]	653	1			T50	21		T136	1		T137	7
values[3]	3106	1			T2	3		T5	15		T11	19
values[4]	784	1			T3	27		T4	3		T42	7
values[5]	670	1			T6	7		T50	18		T51	2
values[6]	835	1			T6	15		T33	13		T138	61
values[7]	878	1			T8	19		T12	1		T137	19
values[8]	1258	1			T45	8		T158	24		T32	13
values[9]	194	1			T51	29		T151	1		T152	27
minimum	17327	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T170	1		T49	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	17		T149	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	5		T4	1		T47	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T46	3		T145	1		T135	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T50	11		T138	16		T142	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	1		T137	5		T158	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T2	3		T5	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T142	5		T233	7		T157	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	14		T4	1		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	7		T25	12		T131	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	1		T243	10		T130	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T50	9		T51	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	1		T33	13		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T138	31		T199	3		T257	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	19		T149	3		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T137	10		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	411	1			T45	6		T32	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T158	13		T157	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T51	13		T151	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T152	17		T258	1		T259	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17034	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T12	1		T145	1		T234	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T170	1		T49	8		T18	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T25	15		T149	10		T229	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	4		T4	10		T47	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	1		T145	14		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T50	10		T138	11		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T137	2		T158	13		T15	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T5	14		T11	17		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T142	4		T233	5		T157	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	13		T4	2		T130	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T25	15		T131	7		T199	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	6		T243	12		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T50	9		T51	1		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	14		T16	1		T171	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T138	30		T199	3		T257	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T149	11		T48	1		T160	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T137	9		T142	15		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T45	2		T32	12		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T158	11		T157	9		T46	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T51	16		T163	11		T67	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T152	10		T212	15		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T145	13		T234	12		T200	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T150	3		T256	15		T261	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T158	13		T262	1		T259	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	1		T170	1		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T25	17		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	5		T47	4		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T46	3		T145	1		T135	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	1		T50	11		T138	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T136	1		T137	5		T158	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T33	3		T140	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T142	5		T48	1		T232	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1730	1			T2	3		T3	14		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T25	12		T233	7		T157	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T243	10		T130	11		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T50	9		T51	1		T42	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	2		T33	13		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T138	31		T139	1		T131	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T139	1		T263	1		T48	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T137	10		T142	14		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T8	19		T51	13		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T12	1		T157	1		T46	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T256	10		T163	11		T264	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T158	11		T262	9		T212	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T170	1		T49	8		T18	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T25	15		T149	10		T145	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	4		T47	2		T249	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T46	1		T145	14		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	10		T50	10		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T137	2		T158	13		T15	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T140	4		T142	6		T57	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T142	4		T232	11		T92	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T3	13		T4	2		T5	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	15		T233	5		T157	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T243	12		T130	11		T144	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T50	9		T51	1		T199	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	20		T16	1		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T138	30		T131	9		T170	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	1		T160	2		T154	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T137	9		T142	15		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T51	16		T45	2		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T157	9		T46	5		T91	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2