Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20782

1

T1

12

T3

36

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

5985

1

T2

3

T5

15

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19925

1

T1

12

T3

27

T4

14

auto[1]

6842

1

T2

3

T3

9

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T325	6		-	-		-	-
values[0]	148	1			T158	30		T263	1		T162	12
values[1]	857	1			T4	11		T137	19		T158	24
values[2]	774	1			T4	3		T6	7		T25	27
values[3]	820	1			T15	19		T144	14		T46	1
values[4]	757	1			T51	2		T42	7		T138	27
values[5]	638	1			T6	15		T138	27		T130	22
values[6]	631	1			T12	1		T50	21		T33	13
values[7]	836	1			T12	1		T51	29		T136	1
values[8]	650	1			T3	36		T136	1		T45	8
values[9]	3518	1			T2	3		T5	15		T8	19
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1290	1			T4	11		T137	19		T158	54
values[1]	2977	1			T2	3		T4	3		T5	15
values[2]	725	1			T15	19		T46	1		T131	24
values[3]	788	1			T6	15		T51	2		T42	7
values[4]	625	1			T12	1		T138	27		T130	22
values[5]	731	1			T50	21		T136	1		T33	13
values[6]	833	1			T3	9		T12	1		T51	29
values[7]	542	1			T3	27		T136	1		T45	8
values[8]	915	1			T8	19		T12	1		T50	18
values[9]	153	1			T233	12		T229	2		T153	1
minimum	17188	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T4	1		T158	13		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T137	10		T158	17		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	1		T6	1		T25	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1725	1			T2	3		T5	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	10		T131	15		T17	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T46	1		T199	5		T270	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T138	14		T139	1		T49	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T51	1		T42	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T138	16		T130	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	4		T148	1		T234	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	11		T33	13		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T136	1		T142	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	5		T12	1		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	13		T137	5		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	14		T45	6		T130	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T136	1		T140	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T25	17		T33	3		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T8	19		T12	1		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T153	1		T185	11		T326	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T233	7		T229	1		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17022	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T274	12		T327	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T4	10		T158	11		T140	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T137	9		T158	13		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T4	2		T6	6		T25	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1034	1			T5	14		T11	17		T14	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	9		T131	9		T17	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T199	4		T270	12		T256	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T138	13		T49	8		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	14		T51	1		T142	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T138	11		T130	11		T46	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	2		T234	12		T91	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T50	10		T143	13		T234	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T142	6		T130	6		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	4		T32	10		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T51	16		T137	2		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	13		T45	2		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T140	2		T18	4		T288	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	15		T157	12		T171	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T50	9		T135	11		T232	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T185	8		T326	8		T328	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T233	5		T229	1		T301	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T274	3		T327	4		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T325	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T263	1		T317	14		T329	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T158	17		T162	10		T330	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T4	1		T158	13		T138	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	10		T140	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	1		T6	1		T25	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T243	10		T46	2		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	10		T131	15		T17	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	1		T46	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T138	14		T139	1		T232	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	1		T42	7		T142	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	16		T130	11		T46	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	1		T57	1		T234	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T50	11		T33	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T139	1		T130	13		T47	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	1		T32	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	13		T136	1		T137	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	19		T45	6		T130	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	1		T141	1		T234	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T25	17		T33	3		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1874	1			T2	3		T5	1		T8	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T329	10		T207	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T158	13		T162	2		T330	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T4	10		T158	11		T138	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T137	9		T140	4		T160	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	2		T6	6		T25	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T243	12		T46	1		T93	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	9		T131	9		T17	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T144	13		T131	9		T270	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T138	13		T232	11		T91	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T51	1		T142	4		T145	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	11		T130	11		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	14		T57	4		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T50	10		T234	14		T244	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	6		T47	2		T149	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T32	10		T147	9		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	16		T137	2		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	17		T45	2		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T234	11		T18	4		T288	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T25	15		T157	12		T171	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1090	1			T5	14		T11	17		T14	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	405	1			T4	11		T158	12		T140	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T137	10		T158	14		T140	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T4	3		T6	7		T25	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1376	1			T2	3		T5	15		T11	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T15	12		T131	10		T17	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T46	1		T199	5		T270	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T138	14		T139	1		T49	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	15		T51	2		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T138	12		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	5		T148	1		T234	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T50	11		T33	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	1		T142	7		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	5		T12	1		T32	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T51	17		T137	3		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	14		T45	6		T130	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T136	1		T140	3		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T25	16		T33	1		T157	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	1		T12	1		T50	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T153	1		T185	9		T326	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T233	6		T229	2		T301	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17146	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T274	4		T327	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T158	12		T138	16		T142	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T137	9		T158	16		T93	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T25	11		T162	4		T172	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1383	1			T13	23		T52	10		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	7		T131	14		T17	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T199	4		T270	10		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T138	13		T49	5		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T42	6		T142	4		T150	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T138	15		T130	10		T265	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T47	1		T234	15		T91	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T50	10		T33	12		T234	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T142	11		T130	12		T271	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	4		T199	2		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	12		T137	4		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	13		T45	2		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T18	1		T159	2		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	16		T33	2		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	18		T50	8		T135	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T185	10		T326	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T233	6		T331	11		T279	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T332	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T274	11		T327	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T325	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T263	1		T317	1		T329	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T158	14		T162	3		T330	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T4	11		T158	12		T138	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T137	10		T140	5		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	3		T6	7		T25	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T243	13		T46	2		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	12		T131	10		T17	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T144	14		T46	1		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T138	14		T139	1		T232	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T51	2		T42	1		T142	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	12		T130	12		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	15		T57	5		T234	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T50	11		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T139	1		T130	7		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T12	1		T32	11		T147	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T51	17		T136	1		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	19		T45	6		T130	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T136	1		T141	1		T234	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T25	16		T33	1		T157	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1457	1			T2	3		T5	15		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T325	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T317	13		T329	7		T318	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T158	16		T162	9		T330	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T158	12		T138	16		T135	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	9		T253	14		T19	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	11		T142	13		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T243	9		T46	1		T93	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	7		T131	14		T17	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T270	10		T286	13		T333	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T138	13		T232	11		T91	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T42	6		T142	4		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T138	15		T130	10		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T234	15		T91	14		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T50	10		T33	12		T234	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T130	12		T47	1		T271	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	2		T199	2		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T51	12		T137	4		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	17		T45	2		T130	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T234	12		T18	1		T246	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T25	16		T33	2		T171	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1507	1			T8	18		T13	23		T50	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23