Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23061

1

T1

12

T2

3

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3706

1

T3

27

T4

3

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20298

1

T1

12

T3

9

T7

10

auto[1]

6469

1

T2

3

T3

27

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	326	1			T42	7		T158	24		T138	27
values[0]	35	1			T135	35		-	-		-	-
values[1]	704	1			T12	1		T50	18		T136	1
values[2]	811	1			T32	13		T138	27		T141	1
values[3]	744	1			T6	15		T12	1		T140	19
values[4]	786	1			T3	27		T45	8		T33	3
values[5]	814	1			T8	19		T51	2		T25	32
values[6]	816	1			T4	14		T6	7		T137	19
values[7]	605	1			T51	29		T137	7		T15	19
values[8]	768	1			T32	11		T33	13		T263	1
values[9]	3226	1			T2	3		T3	9		T5	15
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	809	1			T12	1		T50	18		T136	1
values[1]	681	1			T32	13		T138	27		T141	1
values[2]	766	1			T6	15		T12	1		T140	19
values[3]	932	1			T3	27		T45	8		T33	3
values[4]	787	1			T4	11		T6	7		T8	19
values[5]	749	1			T4	3		T137	19		T243	22
values[6]	2970	1			T2	3		T5	15		T11	19
values[7]	640	1			T32	11		T33	13		T263	1
values[8]	903	1			T12	1		T42	7		T136	1
values[9]	228	1			T3	9		T50	21		T144	11
minimum	17302	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T50	9		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T142	14		T143	1		T135	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T32	1		T138	14		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T141	1		T142	12		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	1		T140	2		T130	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T140	1		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T147	1		T257	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	14		T45	6		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	1		T8	19		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	1		T51	1		T25	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T137	10		T243	10		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T149	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1667	1			T2	3		T5	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	13		T15	10		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T263	1		T144	1		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T32	1		T33	13		T135	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T136	1		T158	30		T25	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T42	7		T138	33
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T3	5		T50	11		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T144	1		T157	1		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17063	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T249	6		T301	1		T331	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T50	9		T131	18		T234	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T142	15		T143	13		T135	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	12		T138	13		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T142	6		T157	9		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T140	12		T130	6		T57	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	14		T140	4		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T147	9		T257	10		T249	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	13		T45	2		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	10		T285	13		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	6		T51	1		T25	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T137	9		T243	12		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	2		T149	10		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T5	14		T11	17		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T51	16		T15	9		T244	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T144	13		T256	10		T160	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	10		T135	11		T17	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T158	24		T25	15		T145	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T138	28		T47	2		T170	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T3	4		T50	10		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T144	10		T157	12		T254	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T249	8		T301	7		T331	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T158	13		T235	1		T232	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T42	7		T138	16		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T135	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T50	9		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T143	1		T160	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T32	1		T138	14		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T141	1		T142	26		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T140	2		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T140	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T130	2		T147	1		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	14		T45	6		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	19		T161	1		T285	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T51	1		T25	17		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T4	1		T137	10		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T6	1		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T137	5		T130	24		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T51	13		T15	10		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T263	1		T144	1		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T32	1		T33	13		T135	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1753	1			T2	3		T3	5		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T138	17		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T158	11		T232	11		T237	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T138	11		T144	10		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T135	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	9		T131	18		T232	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	13		T160	2		T249	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T32	12		T138	13		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T142	21		T157	9		T234	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T140	12		T57	4		T131	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	14		T140	4		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T130	6		T147	9		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	13		T45	2		T142	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T285	13		T154	10		T19	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T51	1		T25	15		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	10		T137	9		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	2		T6	6		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T137	2		T130	17		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	16		T15	9		T149	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	13		T48	2		T256	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	10		T135	11		T17	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T3	4		T5	14		T11	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	17		T47	2		T170	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T12	1		T50	10		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T142	16		T143	14		T135	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	13		T138	14		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T141	1		T142	7		T157	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T140	14		T130	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	15		T140	5		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T147	10		T257	11		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T3	14		T45	6		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	11		T8	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	7		T51	2		T25	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T137	10		T243	13		T130	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	3		T149	11		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T2	3		T5	15		T11	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T51	17		T15	12		T244	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T263	1		T144	14		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T32	11		T33	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T136	1		T158	26		T25	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T12	1		T42	1		T138	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T3	5		T50	11		T157	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T144	11		T157	13		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T249	9		T301	8		T331	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	8		T131	14		T234	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T142	13		T135	16		T152	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T138	13		T16	1		T93	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T142	11		T234	12		T91	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T130	1		T131	12		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T142	4		T46	1		T150	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T253	11		T249	8		T19	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	13		T45	2		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	18		T159	13		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T25	16		T233	6		T150	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T137	9		T243	9		T130	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T261	5		T210	6		T334	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T13	23		T52	10		T40	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T51	12		T15	7		T19	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T150	12		T256	9		T335	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T33	12		T135	16		T17	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	28		T25	11		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T42	6		T138	31		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T3	4		T50	10		T289	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T290	14		T254	14		T283	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T265	7		T336	9		T186	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T249	5		T331	11		T281	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T158	12		T235	1		T232	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T42	1		T138	12		T144	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T135	19		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	1		T50	10		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T143	14		T160	3		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T32	13		T138	14		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T141	1		T142	23		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T140	14		T57	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	15		T140	5		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T130	7		T147	10		T18	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	14		T45	6		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	1		T161	1		T285	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T51	2		T25	16		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	11		T137	10		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	3		T6	7		T96	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	3		T130	19		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	17		T15	12		T149	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T263	1		T144	14		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T32	11		T33	1		T135	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T2	3		T3	5		T5	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	1		T138	18		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T158	12		T232	11		T237	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T42	6		T138	15		T232	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T135	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T50	8		T131	14		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T249	5		T19	3		T210	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	13		T16	1		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T142	24		T234	12		T91	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T131	12		T171	9		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T229	1		T92	2		T291	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T130	1		T18	1		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	13		T45	2		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	18		T154	12		T19	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T25	16		T233	6		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T137	9		T243	9		T159	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T172	15		T210	6		T334	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	4		T130	22		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T51	12		T15	7		T261	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T150	12		T256	9		T335	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T33	12		T135	16		T17	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T3	4		T13	23		T50	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T138	16		T47	1		T49	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23