Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20778

1

T1

12

T3

36

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

5989

1

T2

3

T5

15

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19954

1

T1

12

T3

27

T4

14

auto[1]

6813

1

T2

3

T3

9

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	253	1			T148	1		T135	28		T171	18
values[0]	16	1			T141	1		T263	1		T92	13
values[1]	1019	1			T4	11		T137	19		T158	54
values[2]	755	1			T4	3		T6	7		T25	27
values[3]	766	1			T46	1		T131	24		T17	27
values[4]	739	1			T51	2		T15	19		T138	27
values[5]	744	1			T6	15		T42	7		T138	27
values[6]	622	1			T12	2		T50	21		T33	13
values[7]	790	1			T51	29		T136	1		T137	7
values[8]	658	1			T3	36		T136	1		T45	8
values[9]	3273	1			T2	3		T5	15		T8	19
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1004	1			T4	11		T137	19		T158	24
values[1]	2978	1			T2	3		T4	3		T5	15
values[2]	731	1			T15	19		T46	1		T131	24
values[3]	783	1			T6	15		T51	2		T42	7
values[4]	647	1			T12	1		T138	27		T130	22
values[5]	717	1			T50	21		T136	1		T33	13
values[6]	864	1			T3	9		T12	1		T51	29
values[7]	564	1			T3	27		T136	1		T45	8
values[8]	883	1			T8	19		T12	1		T50	18
values[9]	149	1			T233	12		T153	1		T259	15
minimum	17447	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T4	1		T158	13		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T137	10		T140	1		T93	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T6	1		T25	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1717	1			T2	3		T5	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	10		T131	15		T17	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	1		T199	5		T270	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T138	14		T139	1		T49	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T51	1		T42	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T138	16		T130	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	4		T148	1		T234	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T50	11		T33	13		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T136	1		T142	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T3	5		T12	1		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T51	13		T137	5		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	14		T45	6		T149	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	1		T140	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T25	17		T33	3		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	19		T12	1		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T153	1		T259	15		T185	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T233	7		T331	12		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17101	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T158	17		T19	3		T107	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T4	10		T158	11		T140	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	9		T140	4		T93	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T4	2		T6	6		T25	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1020	1			T5	14		T11	17		T14	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	9		T131	9		T17	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T199	4		T270	12		T256	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T138	13		T49	8		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	14		T51	1		T142	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	11		T130	11		T46	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T47	2		T234	12		T154	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T50	10		T143	13		T234	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T142	6		T130	6		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	4		T32	10		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T51	16		T137	2		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	13		T45	2		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T140	2		T130	6		T18	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	15		T157	12		T171	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T50	9		T135	11		T229	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T185	8		T326	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T233	5		T331	14		T294	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T45	3		T57	1		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T158	13		T19	1		T107	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T148	1		T171	10		T153	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T135	17		T280	10		T172	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T141	1		T263	1		T92	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T4	1		T158	13		T138	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T137	10		T158	17		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T6	1		T25	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T243	10		T46	2		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T131	15		T17	14		T275	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T46	1		T270	11		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	10		T138	14		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T51	1		T142	5		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	16		T130	11		T46	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	1		T42	7		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	2		T50	11		T33	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T142	12		T139	1		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T32	1		T147	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T51	13		T136	1		T137	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	19		T45	6		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T136	1		T140	1		T130	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T25	17		T33	3		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1800	1			T2	3		T5	1		T8	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T171	8		T185	8		T337	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T135	11		T176	13		T331	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T92	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T4	10		T158	11		T138	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T137	9		T158	13		T140	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	2		T6	6		T25	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T243	12		T46	1		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T131	9		T17	13		T275	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T270	12		T256	7		T19	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	9		T138	13		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	1		T142	4		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	11		T130	11		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	14		T57	4		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T50	10		T234	14		T17	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T142	6		T130	6		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T32	10		T147	9		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T51	16		T137	2		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	17		T45	2		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T140	2		T130	6		T234	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T25	15		T157	12		T91	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1049	1			T5	14		T11	17		T14	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T4	11		T158	12		T140	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T137	10		T140	5		T93	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	3		T6	7		T25	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1362	1			T2	3		T5	15		T11	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	12		T131	10		T17	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T46	1		T199	5		T270	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T138	14		T139	1		T49	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	15		T51	2		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T138	12		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	5		T148	1		T234	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	11		T33	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T136	1		T142	7		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T3	5		T12	1		T32	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T51	17		T137	3		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	14		T45	6		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	1		T140	3		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T25	16		T33	1		T157	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	1		T12	1		T50	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T153	1		T259	1		T185	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T233	6		T331	15		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17251	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T158	14		T19	3		T107	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T158	12		T138	16		T142	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T137	9		T93	11		T162	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	11		T162	4		T172	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1375	1			T13	23		T52	10		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	7		T131	14		T17	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T199	4		T270	10		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	13		T49	5		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T42	6		T142	4		T150	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T138	15		T130	10		T265	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	1		T234	15		T154	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T50	10		T33	12		T234	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T142	11		T130	12		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	4		T199	2		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	12		T137	4		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T3	13		T45	2		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T130	1		T18	1		T159	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T25	16		T33	2		T171	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	18		T50	8		T135	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T259	14		T185	10		T326	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T233	6		T331	11		T279	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T92	2		T265	9		T254	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T158	16		T19	1		T107	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T148	1		T171	9		T153	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T135	12		T280	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T141	1		T263	1		T92	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T4	11		T158	12		T138	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T137	10		T158	14		T140	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	3		T6	7		T25	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T243	13		T46	2		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T131	10		T17	16		T275	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	1		T270	13		T256	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T15	12		T138	14		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T51	2		T142	5		T144	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T138	12		T130	12		T46	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	15		T42	1		T57	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	2		T50	11		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T142	7		T139	1		T130	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T32	11		T147	10		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T51	17		T136	1		T137	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	19		T45	6		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T136	1		T140	3		T130	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T25	16		T33	1		T157	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1410	1			T2	3		T5	15		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T171	9		T316	18		T259	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T135	16		T280	9		T172	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T92	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T158	12		T138	16		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	9		T158	16		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T25	11		T131	12		T152	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T243	9		T46	1		T93	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T131	14		T17	11		T275	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T270	10		T286	13		T333	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	7		T138	13		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T142	4		T150	14		T199	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	15		T130	10		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	6		T234	15		T91	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	10		T33	12		T234	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	11		T130	12		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T199	2		T152	16		T200	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	12		T137	4		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	17		T45	2		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T130	1		T234	12		T159	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T25	16		T33	2		T159	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1439	1			T8	18		T13	23		T50	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23