Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22759

1

T1

12

T2

3

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

4008

1

T3

27

T6

15

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20212

1

T1

12

T7

10

T9

19

auto[1]

6555

1

T2

3

T3

36

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T8	19		T12	1		T42	7
values[0]	17	1			T230	1		T231	2		T241	1
values[1]	580	1			T3	27		T51	29		T25	27
values[2]	3028	1			T2	3		T5	15		T11	19
values[3]	980	1			T4	11		T136	1		T158	30
values[4]	916	1			T3	9		T50	39		T51	2
values[5]	715	1			T138	61		T143	14		T149	11
values[6]	663	1			T4	3		T12	1		T137	7
values[7]	727	1			T6	22		T12	1		T137	19
values[8]	841	1			T158	24		T32	11		T33	3
values[9]	878	1			T136	1		T45	8		T139	1
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	477	1			T3	27		T25	27		T140	5
values[1]	3321	1			T2	3		T5	15		T11	19
values[2]	899	1			T4	11		T51	2		T136	1
values[3]	817	1			T3	9		T50	39		T25	32
values[4]	646	1			T140	11		T138	34		T143	14
values[5]	675	1			T4	3		T12	2		T137	7
values[6]	755	1			T6	22		T137	19		T32	13
values[7]	819	1			T158	24		T32	11		T33	3
values[8]	909	1			T42	7		T136	1		T45	8
values[9]	105	1			T8	19		T12	1		T57	5
minimum	17344	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T140	1		T141	1		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	14		T25	12		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1760	1			T2	3		T5	1		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T144	2		T149	3		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	1		T51	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T158	17		T15	10		T243	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	5		T142	14		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T50	20		T25	17		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T140	1		T138	17		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	2		T150	13		T159	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	1		T12	2		T33	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T137	5		T142	5		T233	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	1		T137	10		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T135	17		T234	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T158	13		T32	1		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T148	1		T232	12		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T139	1		T131	15		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T42	7		T136	1		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T57	1		T48	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T8	19		T12	1		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17066	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T229	4		T91	3		T292	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	4		T130	6		T47	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	13		T25	15		T147	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T5	14		T11	17		T14	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T144	23		T149	11		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	10		T51	1		T157	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T158	13		T15	9		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	4		T142	15		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	19		T25	15		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T140	10		T138	17		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T46	1		T93	13		T244	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	2		T140	2		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T137	2		T142	4		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	6		T137	9		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	14		T135	11		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	11		T32	10		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T232	18		T160	11		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T131	9		T170	1		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	2		T130	11		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T57	4		T338	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T160	9		T106	17		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T51	16		T45	3		T142	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T229	1		T91	11		T292	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	1		T160	1		T200	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T8	19		T12	1		T42	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T230	1		T241	1		T339	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T51	13		T140	1		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	14		T25	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1730	1			T2	3		T5	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T144	1		T149	3		T232	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	1		T136	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T158	17		T243	10		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	5		T51	1		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T50	20		T15	10		T25	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	17		T143	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T138	14		T150	13		T159	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	1		T12	1		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	5		T233	7		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T12	1		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T142	5		T135	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T158	13		T32	1		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	1		T160	1		T152	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T139	1		T57	1		T131	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T136	1		T45	6		T130	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T160	2		T200	7		T336	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T256	10		T160	9		T340	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T51	16		T140	4		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	13		T25	15		T147	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T5	14		T11	17		T14	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	13		T149	11		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	10		T199	7		T248	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T158	13		T243	12		T130	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	4		T51	1		T142	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T50	19		T15	9		T25	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	17		T143	13		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	13		T93	13		T244	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	2		T140	12		T145	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T137	2		T233	5		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	6		T137	9		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	14		T142	4		T135	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T158	11		T32	10		T157	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T160	11		T152	7		T285	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T57	4		T131	9		T170	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	2		T130	11		T48	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T140	5		T141	1		T263	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	14		T25	16		T147	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T2	3		T5	15		T11	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T144	25		T149	12		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	11		T51	2		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T158	14		T15	12		T243	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	5		T142	16		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T50	21		T25	16		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T140	11		T138	18		T143	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	2		T150	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	3		T12	2		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T137	3		T142	5		T233	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	7		T137	10		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	15		T135	12		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T158	12		T32	11		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T148	1		T232	19		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T139	1		T131	10		T170	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T42	1		T136	1		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T57	5		T48	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T8	1		T12	1		T160	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17197	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T229	4		T91	12		T292	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T130	1		T47	1		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	13		T25	11		T270	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T13	23		T52	10		T40	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T149	2		T232	14		T172	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	1		T199	2		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T158	16		T15	7		T243	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	4		T142	13		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	18		T25	16		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T138	16		T248	1		T254	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	1		T150	12		T159	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	12		T17	3		T91	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	4		T142	4		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T137	9		T138	15		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T135	16		T234	12		T92	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	12		T33	2		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T232	11		T152	10		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T131	14		T250	15		T200	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T42	6		T45	2		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T210	7		T251	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T8	18		T106	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T51	12		T142	11		T17	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T229	1		T91	2		T300	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	1		T160	3		T200	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T8	1		T12	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T231	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T230	1		T241	1		T339	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T51	17		T140	5		T142	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	14		T25	16		T147	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T2	3		T5	15		T11	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T144	14		T149	12		T232	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	11		T136	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T158	14		T243	13		T130	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	5		T51	2		T142	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T50	21		T15	12		T25	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	18		T143	14		T149	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T138	14		T150	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	3		T12	1		T140	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	3		T233	6		T46	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	7		T12	1		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	15		T142	5		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T158	12		T32	11		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T148	1		T160	12		T152	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T139	1		T57	5		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T136	1		T45	6		T130	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T200	9		T336	16		T332	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T8	18		T42	6		T256	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T231	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T339	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T51	12		T142	11		T130	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	13		T25	11		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T13	23		T52	10		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	2		T232	14		T172	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T199	6		T253	11		T248	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T158	16		T243	9		T130	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	4		T142	13		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	18		T15	7		T25	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T138	16		T248	1		T254	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	13		T150	12		T159	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	3		T91	13		T261	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T137	4		T233	6		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T137	9		T33	12		T138	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T142	4		T135	16		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T158	12		T33	2		T49	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T152	10		T249	8		T255	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	14		T250	15		T172	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	2		T130	10		T171	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23