Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23158

1

T1

12

T2

3

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3609

1

T3

9

T4

3

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19814

1

T1

12

T3

9

T4

3

auto[1]

6953

1

T2

3

T3

27

T4

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	665	1			T3	9		T54	3		T34	4
values[0]	58	1			T300	19		T106	33		T279	6
values[1]	872	1			T140	5		T143	14		T157	13
values[2]	2930	1			T2	3		T5	15		T11	19
values[3]	629	1			T6	15		T8	19		T136	1
values[4]	763	1			T4	14		T138	27		T139	1
values[5]	1033	1			T12	1		T50	21		T51	2
values[6]	653	1			T51	29		T45	8		T137	7
values[7]	1050	1			T6	7		T25	59		T140	14
values[8]	471	1			T15	19		T147	10		T46	11
values[9]	950	1			T3	27		T12	2		T42	7
minimum	16693	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	902	1			T140	5		T143	14		T157	13
values[1]	2947	1			T2	3		T5	15		T8	19
values[2]	666	1			T6	15		T136	1		T158	24
values[3]	794	1			T4	14		T12	1		T51	2
values[4]	933	1			T50	21		T136	1		T45	8
values[5]	761	1			T6	7		T51	29		T142	9
values[6]	977	1			T25	59		T140	14		T138	34
values[7]	394	1			T3	27		T12	1		T137	19
values[8]	952	1			T3	9		T12	1		T42	7
values[9]	102	1			T131	10		T150	3		T234	28
minimum	17339	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T140	1		T143	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	4		T149	3		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1732	1			T2	3		T5	1		T8	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T50	9		T141	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	1		T32	1		T142	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T158	13		T138	30
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	1		T12	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	1		T51	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T50	11		T136	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T45	6		T137	5		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T51	13		T142	5		T130	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T16	3		T232	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T25	17		T141	1		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T25	12		T140	2		T138	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	14		T12	1		T15	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	10		T46	2		T229	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T33	3		T145	1		T199	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	5		T12	1		T42	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T150	3		T234	16		T172	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T131	1		T176	1		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17073	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T153	1		T19	3		T300	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T140	4		T143	13		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T47	2		T149	11		T170	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T5	14		T11	17		T14	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T50	9		T233	5		T49	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	12		T142	6		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	14		T158	11		T138	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	10		T130	6		T144	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	2		T51	1		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T50	10		T170	1		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T45	2		T137	2		T32	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T51	16		T142	4		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	6		T16	1		T232	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	15		T144	13		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T25	15		T140	12		T138	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	13		T15	9		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T137	9		T46	5		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T145	13		T199	4		T91	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	4		T158	13		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T234	12		T276	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T131	9		T176	3		T297	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T19	2		T300	8		T341	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	491	1			T54	3		T34	4		T35	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T3	5		T131	1		T154	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T106	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T300	11		T279	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T140	1		T143	1		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	4		T149	3		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T2	3		T5	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T50	9		T141	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	19		T136	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T158	13		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	1		T139	1		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	1		T138	16		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T50	11		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T51	1		T32	1		T33	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T51	13		T142	5		T130	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	6		T137	5		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T25	17		T141	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T6	1		T25	12		T140	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	10		T147	1		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T46	2		T229	4		T159	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	14		T12	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T12	1		T42	7		T137	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16569	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T145	13		T152	7		T249	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T3	4		T131	9		T154	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T106	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T300	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T140	4		T143	13		T157	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	2		T149	11		T170	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T5	14		T11	17		T14	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T50	9		T233	5		T49	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T32	12		T142	6		T145	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	14		T158	11		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	10		T130	6		T144	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	2		T138	11		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T50	10		T170	1		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T51	1		T32	10		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T51	16		T142	4		T130	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T45	2		T137	2		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T25	15		T144	13		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	6		T25	15		T140	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T15	9		T147	9		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T46	5		T229	1		T288	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	13		T199	4		T234	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T137	9		T158	13		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T140	5		T143	14		T157	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	5		T149	12		T170	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T2	3		T5	15		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T50	10		T141	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	1		T32	13		T142	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	15		T158	12		T138	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	11		T12	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	3		T51	2		T149	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T50	11		T136	1		T170	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T45	6		T137	3		T32	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T51	17		T142	5		T130	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	7		T16	3		T232	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	16		T141	1		T144	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T25	16		T140	14		T138	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	14		T12	1		T15	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T137	10		T46	7		T229	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T33	1		T145	14		T199	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	5		T12	1		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T150	1		T234	13		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T131	10		T176	4		T297	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17206	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T153	1		T19	3		T300	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T135	16		T17	11		T232	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T47	1		T149	2		T261	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T8	18		T13	23		T52	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T50	8		T233	6		T49	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T142	11		T135	16		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T158	12		T138	28		T159	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T130	12		T171	9		T93	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T232	11		T200	12		T280	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	10		T162	9		T267	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T45	2		T137	4		T33	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T51	12		T142	4		T130	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	1		T232	14		T342	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	16		T150	12		T92	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T25	11		T138	16		T131	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T3	13		T15	7		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T137	9		T229	1		T287	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T33	2		T199	4		T91	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	4		T42	6		T158	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T150	2		T234	15		T172	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T234	12		T245	9		T343	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T19	2		T300	10		T341	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	517	1			T54	3		T34	4		T35	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T3	5		T131	10		T154	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T106	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T300	9		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T140	5		T143	14		T157	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	5		T149	12		T170	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	3		T5	15		T11	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T50	10		T141	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	1		T136	1		T32	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	15		T158	12		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	11		T139	1		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	3		T138	12		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	1		T50	11		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T51	2		T32	11		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T51	17		T142	5		T130	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T45	6		T137	3		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T25	16		T141	1		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T6	7		T25	16		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	12		T147	10		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	7		T229	4		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	14		T12	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	1		T42	1		T137	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16693	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T150	2		T152	10		T249	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T3	4		T154	12		T281	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T106	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T300	10		T279	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T135	16		T234	12		T17	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T47	1		T149	2		T261	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T13	23		T52	10		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T50	8		T233	6		T49	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	18		T142	11		T135	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T158	12		T138	13		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T130	12		T199	2		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T138	15		T232	11		T159	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	10		T93	11		T162	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T33	12		T243	9		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T51	12		T142	4		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	2		T137	4		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T25	16		T150	12		T234	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T25	11		T138	16		T131	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T15	7		T46	1		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T229	1		T159	2		T250	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	13		T33	2		T199	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T42	6		T137	9		T158	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23