Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23074

1

T1

12

T2

3

T3

36

auto[ADC_CTRL_FILTER_COND_OUT]

3693

1

T4

11

T6

15

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20414

1

T1

12

T3

27

T7

10

auto[1]

6353

1

T2

3

T3

9

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	288	1			T140	5		T60	11		T152	36
values[0]	39	1			T131	24		T160	12		T310	1
values[1]	798	1			T3	27		T6	15		T51	29
values[2]	861	1			T4	3		T6	7		T15	19
values[3]	737	1			T3	9		T4	11		T12	1
values[4]	659	1			T243	22		T157	13		T46	8
values[5]	3014	1			T2	3		T5	15		T11	19
values[6]	575	1			T12	1		T158	24		T131	10
values[7]	903	1			T50	21		T51	2		T42	7
values[8]	660	1			T8	19		T12	1		T158	30
values[9]	1101	1			T136	1		T45	8		T25	27
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	782	1			T6	22		T51	29		T137	26
values[1]	879	1			T3	9		T4	3		T12	1
values[2]	802	1			T4	11		T50	18		T32	11
values[3]	2897	1			T2	3		T5	15		T11	19
values[4]	652	1			T158	24		T25	32		T33	3
values[5]	731	1			T12	1		T50	21		T51	2
values[6]	870	1			T42	7		T158	30		T263	1
values[7]	693	1			T8	19		T12	1		T136	1
values[8]	931	1			T45	8		T140	16		T138	88
values[9]	152	1			T130	8		T244	9		T201	1
minimum	17378	1			T1	12		T3	27		T7	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	1		T137	15		T15	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T51	13		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	5		T4	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T147	1		T46	2		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T50	9		T140	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	1		T32	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T2	3		T5	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T243	10		T152	17		T253	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T25	17		T157	1		T234	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T158	13		T33	3		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T136	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	11		T51	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T42	7		T144	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T158	17		T263	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T136	1		T170	1		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	19		T12	1		T25	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T45	6		T140	2		T138	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T138	30		T141	1		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T130	2		T319	14		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T244	1		T201	1		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17114	1			T1	12		T3	14		T7	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T162	5		T197	10		T344	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	6		T137	11		T15	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	14		T51	16		T232	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	4		T4	2		T145	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T147	9		T46	1		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T50	9		T140	2		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	10		T32	10		T130	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T5	14		T11	17		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T243	12		T152	10		T287	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T25	15		T157	9		T234	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	11		T93	13		T19	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T142	15		T131	9		T92	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T50	10		T51	1		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T144	13		T171	8		T275	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T158	13		T48	1		T145	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T170	1		T49	8		T199	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T25	15		T233	5		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T45	2		T140	14		T138	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T138	24		T142	6		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T130	6		T345	11		T97	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T244	8		T19	1		T320	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	13		T45	3		T143	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T162	2		T197	9		T344	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T140	1		T319	14		T345	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T60	1		T152	20		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T131	15		T310	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T160	1		T346	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	14		T137	15		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	1		T51	13		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	1		T6	1		T15	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T147	1		T46	2		T232	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	5		T12	1		T50	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	1		T32	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T157	1		T170	1		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T243	10		T46	3		T172	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T2	3		T5	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	3		T235	1		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T131	1		T159	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	13		T16	3		T234	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T42	7		T136	1		T142	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T50	11		T51	1		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T170	1		T49	10		T199	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	19		T12	1		T158	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T136	1		T45	6		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T25	12		T33	13		T138	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T140	4		T345	11		T97	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T60	10		T152	16		T19	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T131	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T160	11		T346	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	13		T137	11		T32	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	14		T51	16		T232	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	2		T6	6		T15	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T147	9		T46	1		T232	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	4		T50	9		T140	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	10		T32	10		T130	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T157	12		T170	4		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T243	12		T46	5		T287	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T5	14		T11	17		T14	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T93	13		T152	10		T19	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T131	9		T173	1		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T158	11		T16	1		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T142	15		T144	13		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T50	10		T51	1		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T170	1		T49	8		T199	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T158	13		T47	2		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T45	2		T140	10		T138	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T25	15		T138	24		T142	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	7		T137	13		T15	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	15		T51	17		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	5		T4	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T147	10		T46	2		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T50	10		T140	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T4	11		T32	11		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T2	3		T5	15		T11	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T243	13		T152	11		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T25	16		T157	10		T234	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T158	12		T33	1		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T136	1		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T50	11		T51	2		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T42	1		T144	14		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T158	14		T263	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T136	1		T170	2		T49	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	1		T12	1		T25	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T45	6		T140	16		T138	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T138	26		T141	1		T142	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T130	7		T319	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T244	9		T201	1		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17203	1			T1	12		T3	14		T7	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T162	3		T197	10		T344	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T137	13		T15	7		T131	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	12		T232	11		T92	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	4		T91	13		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	1		T232	14		T261	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T50	8		T142	4		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T130	12		T131	12		T172	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T13	23		T52	10		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T243	9		T152	16		T253	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T25	16		T234	15		T291	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T158	12		T33	2		T19	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T142	13		T159	11		T92	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	10		T16	1		T199	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T42	6		T150	12		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T158	16		T48	1		T234	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T49	5		T199	2		T270	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	18		T25	11		T33	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T45	2		T138	16		T135	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T138	28		T142	11		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T130	1		T319	13		T345	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T19	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	13		T150	15		T246	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T162	4		T197	9		T344	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T140	5		T319	1		T345	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T60	11		T152	17		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T131	10		T310	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T160	12		T346	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	14		T137	13		T32	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	15		T51	17		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T4	3		T6	7		T15	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T147	10		T46	2		T232	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	5		T12	1		T50	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	11		T32	11		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T157	13		T170	5		T18	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T243	13		T46	8		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T2	3		T5	15		T11	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T33	1		T235	1		T93	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T131	10		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T158	12		T16	3		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T42	1		T136	1		T142	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T50	11		T51	2		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T170	2		T49	13		T199	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T12	1		T158	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T136	1		T45	6		T140	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T25	16		T33	1		T138	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T319	13		T345	11		T97	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T152	19		T172	11		T19	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T131	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	13		T137	13		T150	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T51	12		T232	11		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	7		T135	16		T91	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	1		T232	14		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	4		T50	8		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T130	12		T131	12		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	1		T93	11		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T243	9		T172	15		T333	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T13	23		T52	10		T40	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T33	2		T152	16		T253	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T159	11		T173	1		T291	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T158	12		T16	1		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T42	6		T142	13		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T50	10		T48	1		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	5		T199	2		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	18		T158	16		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	2		T138	16		T130	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T25	11		T33	12		T138	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23