Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23223

1

T1

12

T2

3

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3544

1

T3

9

T4

11

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20386

1

T1

12

T3

36

T4

14

auto[1]

6381

1

T2

3

T5

15

T6

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	270	1			T32	13		T140	3		T142	47
values[0]	44	1			T131	20		T229	5		T347	8
values[1]	672	1			T3	27		T4	3		T50	21
values[2]	814	1			T50	18		T45	8		T25	32
values[3]	818	1			T12	1		T51	2		T42	7
values[4]	582	1			T158	30		T32	11		T33	3
values[5]	672	1			T6	15		T8	19		T12	1
values[6]	744	1			T3	9		T4	11		T51	29
values[7]	733	1			T137	7		T46	3		T170	5
values[8]	3145	1			T2	3		T5	15		T6	7
values[9]	1141	1			T12	1		T136	1		T137	19
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	599	1			T3	27		T4	3		T50	21
values[1]	927	1			T50	18		T51	2		T45	8
values[2]	690	1			T12	1		T42	7		T15	19
values[3]	754	1			T8	19		T158	30		T32	11
values[4]	572	1			T6	15		T12	1		T136	1
values[5]	634	1			T3	9		T4	11		T51	29
values[6]	3264	1			T2	3		T5	15		T11	19
values[7]	722	1			T6	7		T138	27		T147	10
values[8]	1037	1			T12	1		T136	1		T137	19
values[9]	183	1			T140	3		T263	1		T135	35
minimum	17385	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	14		T4	1		T130	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T50	11		T139	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T51	1		T45	6		T57	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T50	9		T25	17		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T15	10		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T42	7		T141	1		T233	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T158	17		T32	1		T130	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	19		T138	17		T130	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T12	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T25	12		T243	10		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T158	13		T139	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	5		T4	1		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1748	1			T2	3		T5	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	2		T256	1		T162	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T138	16		T147	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T157	1		T131	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	1		T137	10		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T136	1		T138	14		T142	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T140	1		T135	17		T237	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T263	1		T264	1		T295	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17044	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T131	13		T145	1		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	13		T4	2		T130	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T50	10		T229	1		T244	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T51	1		T45	2		T57	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T50	9		T25	15		T140	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	9		T140	10		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T233	5		T48	2		T93	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T158	13		T32	10		T130	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T138	17		T130	11		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	14		T144	13		T49	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T25	15		T243	12		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T158	11		T91	12		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	4		T4	10		T51	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T5	14		T11	17		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T46	1		T256	7		T162	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T138	11		T147	9		T232	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	6		T157	9		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T137	9		T32	12		T142	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T138	13		T142	15		T170	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T140	2		T135	18		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T307	7		T348	11		T349	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T131	7		T145	13		T257	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T32	1		T140	1		T142	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T142	14		T263	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T229	4		T347	1		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T131	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	14		T4	1		T130	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T50	11		T145	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	6		T46	2		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T50	9		T25	17		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T51	1		T15	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T42	7		T141	1		T233	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T158	17		T32	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	17		T48	2		T17	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T12	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	19		T25	12		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T158	13		T33	13		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	5		T4	1		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T137	5		T170	1		T234	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T46	2		T256	1		T162	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1706	1			T2	3		T5	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T157	1		T131	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T12	1		T137	10		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T136	1		T138	14		T170	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T32	12		T140	2		T142	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T142	15		T350	16		T348	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T229	1		T347	7		T306	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T131	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	13		T4	2		T130	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	10		T145	13		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T45	2		T46	5		T131	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T50	9		T25	15		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T51	1		T15	9		T57	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T233	5		T234	12		T275	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T158	13		T32	10		T140	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T138	17		T48	2		T17	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	14		T171	8		T285	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T25	15		T243	12		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T158	11		T144	13		T49	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	4		T4	10		T51	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T137	2		T170	4		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T46	1		T256	7		T162	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T5	14		T11	17		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	6		T157	9		T131	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T137	9		T157	12		T135	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T138	13		T170	1		T234	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	14		T4	3		T130	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T50	11		T139	1		T229	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T51	2		T45	6		T57	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T50	10		T25	16		T140	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	1		T15	12		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	1		T141	1		T233	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T158	14		T32	11		T130	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T138	18		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	15		T12	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T25	16		T243	13		T157	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T158	12		T139	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	5		T4	11		T51	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T2	3		T5	15		T11	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T46	2		T256	8		T162	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T138	12		T147	10		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	7		T157	10		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	1		T137	10		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T136	1		T138	14		T142	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T140	3		T135	19		T237	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T263	1		T264	1		T295	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17184	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T131	8		T145	14		T257	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	13		T130	12		T199	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	10		T290	14		T254	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T45	2		T48	1		T150	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	8		T25	16		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	7		T33	2		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T42	6		T233	6		T200	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T158	16		T130	1		T150	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	18		T138	16		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	12		T49	5		T173	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T25	11		T243	9		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T158	12		T91	14		T152	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	4		T51	12		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T13	23		T52	10		T40	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	1		T162	11		T154	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T138	15		T232	14		T91	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T131	14		T93	11		T255	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T137	9		T142	11		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T138	13		T142	13		T234	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T135	16		T237	2		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T295	8		T307	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T229	1		T305	7		T351	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T131	12		T291	13		T248	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T32	13		T140	3		T142	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T142	16		T263	1		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T229	4		T347	8		T306	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T131	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	14		T4	3		T130	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T50	11		T145	14		T229	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T45	6		T46	7		T131	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	10		T25	16		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	1		T51	2		T15	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T42	1		T141	1		T233	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T158	14		T32	11		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T138	18		T48	4		T17	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	15		T12	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	1		T25	16		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T158	12		T33	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	5		T4	11		T51	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T137	3		T170	5		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T46	2		T256	8		T162	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T2	3		T5	15		T11	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	7		T157	10		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T12	1		T137	10		T157	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T136	1		T138	14		T170	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T142	11		T16	1		T237	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T142	13		T269	6		T295	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T229	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T131	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	13		T130	12		T199	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T50	10		T290	14		T252	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	2		T232	11		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T50	8		T25	16		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	7		T149	2		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	6		T233	6		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	16		T33	2		T142	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T138	16		T17	11		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T171	9		T173	1		T336	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	18		T25	11		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T158	12		T33	12		T49	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	4		T51	12		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	4		T234	12		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T46	1		T162	7		T253	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T13	23		T52	10		T40	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T131	14		T162	4		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T137	9		T135	16		T92	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T138	13		T234	15		T93	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23