Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T170	2		T49	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T25	16		T149	11		T229	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	5		T4	11		T47	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T46	3		T145	15		T135	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	11		T138	12		T142	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	1		T137	3		T158	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	3		T5	15		T11	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T142	5		T233	6		T157	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	14		T4	3		T130	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	1		T25	16		T131	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T6	7		T243	13		T130	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	10		T51	2		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	15		T33	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T138	32		T199	4		T257	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	1		T149	12		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	1		T137	10		T142	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T45	6		T32	13		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T158	12		T157	10		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T51	17		T151	1		T163	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T152	11		T258	1		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17169	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T12	1		T145	14		T234	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T49	5		T18	1		T254	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T25	16		T92	2		T265	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	4		T47	1		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T46	1		T135	16		T154	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T50	10		T138	15		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T137	4		T158	16		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T13	23		T52	10		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T142	4		T233	6		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	13		T130	12		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T42	6		T25	11		T131	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T243	9		T130	10		T150	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T50	8		T131	14		T92	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	12		T16	1		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T138	29		T199	2		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	18		T149	2		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T137	9		T142	13		T135	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T45	2		T130	1		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T158	12		T91	13		T253	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T51	12		T67	4		T266	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T152	16		T259	14		T212	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T267	1		T268	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T234	15		T200	12		T253	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T150	1		T256	16		T261	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T158	12		T262	10		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T170	2		T49	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T25	16		T149	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	5		T47	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T46	3		T145	15		T135	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	11		T50	11		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T136	1		T137	3		T158	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	1		T140	5		T142	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T142	5		T48	1		T232	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T2	3		T3	14		T4	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T25	16		T233	6		T157	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T243	13		T130	12		T144	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T50	10		T51	2		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	22		T33	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T138	32		T139	1		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T139	1		T263	1		T48	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T137	10		T142	16		T147	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T8	1		T51	17		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	1		T157	10		T46	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T150	2		T256	9		T269	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T158	12		T259	14		T212	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T49	5		T18	1		T267	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T25	16		T234	15		T92	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	4		T47	1		T150	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T46	1		T135	16		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T50	10		T138	15		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T137	4		T158	16		T15	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	2		T142	11		T270	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	4		T232	11		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T3	13		T13	23		T52	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T25	11		T233	6		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T243	9		T130	10		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T50	8		T42	6		T199	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	12		T16	1		T171	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T138	29		T131	14		T271	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	1		T154	12		T272	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T137	9		T142	13		T135	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T8	18		T51	12		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T91	13		T152	16		T200	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23