Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23186

1

T1

12

T2

3

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3581

1

T3

9

T6

22

T50

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19931

1

T1

12

T3

36

T6

7

auto[1]

6836

1

T2

3

T4

14

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	468	1			T54	3		T34	4		T35	4
values[0]	64	1			T273	1		T240	2		T274	15
values[1]	839	1			T140	5		T143	14		T157	13
values[2]	2957	1			T2	3		T5	15		T11	19
values[3]	606	1			T6	15		T8	19		T158	24
values[4]	813	1			T4	3		T136	1		T32	13
values[5]	973	1			T4	11		T12	1		T50	21
values[6]	683	1			T51	29		T45	8		T137	7
values[7]	979	1			T6	7		T140	14		T138	34
values[8]	576	1			T15	19		T25	59		T141	1
values[9]	1116	1			T3	36		T12	2		T42	7
minimum	16693	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1131	1			T140	5		T141	1		T143	14
values[1]	2889	1			T2	3		T5	15		T8	19
values[2]	701	1			T6	15		T136	1		T158	24
values[3]	679	1			T4	14		T12	1		T51	2
values[4]	1048	1			T50	21		T136	1		T45	8
values[5]	756	1			T6	7		T51	29		T142	9
values[6]	973	1			T25	59		T140	14		T138	34
values[7]	396	1			T3	27		T12	1		T137	19
values[8]	962	1			T3	9		T12	1		T42	7
values[9]	100	1			T57	5		T131	10		T150	3
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T140	1		T141	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T143	1		T47	4		T149	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1691	1			T2	3		T5	1		T8	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T50	9		T233	7		T49	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T142	12		T263	1		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T136	1		T158	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	2		T12	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T51	1		T139	1		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T50	11		T136	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T45	6		T137	5		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T142	5		T130	2		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T51	13		T234	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T140	1		T138	17		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T25	29		T140	1		T159	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	14		T12	1		T15	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	10		T46	5		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	1		T42	7		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	5		T158	17		T130	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T150	3		T92	9		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T57	1		T131	1		T176	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T140	4		T157	12		T48	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T143	13		T47	2		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T5	14		T11	17		T14	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T50	9		T233	5		T49	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T142	6		T145	14		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	14		T158	11		T32	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	12		T144	10		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T51	1		T130	6		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T50	10		T170	1		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T45	2		T137	2		T32	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T142	4		T130	6		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	6		T51	16		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T140	2		T138	17		T144	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T25	30		T140	10		T60	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	13		T15	9		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T137	9		T46	6		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T145	13		T199	4		T275	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	4		T158	13		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T92	5		T276	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T57	4		T131	9		T176	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	439	1			T54	3		T34	4		T35	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T234	16		T277	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T240	1		T274	12		T106	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T273	1		T278	7		T279	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T140	1		T157	1		T135	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	1		T47	4		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T2	3		T5	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T50	9		T233	7		T270	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	19		T142	12		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T158	13		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	1		T263	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T136	1		T32	1		T138	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T4	1		T12	1		T50	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T51	1		T33	13		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T142	5		T130	2		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T51	13		T45	6		T137	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T140	1		T138	17		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	1		T140	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	10		T141	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T25	29		T46	5		T229	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T3	14		T12	2		T42	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	5		T137	10		T158	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16569	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T234	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T240	1		T274	3		T106	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T140	4		T157	12		T135	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T143	13		T47	2		T149	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	14		T11	17		T14	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	9		T233	5		T270	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T142	6		T145	14		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	14		T158	11		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	2		T144	10		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T32	12		T138	11		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	10		T50	10		T170	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T51	1		T243	12		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T142	4		T130	6		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	16		T45	2		T137	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T140	2		T138	17		T144	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	6		T140	10		T234	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	9		T147	9		T17	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T25	30		T46	6		T229	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T3	13		T145	13		T199	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	4		T137	9		T158	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T140	5		T141	1		T157	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T143	14		T47	5		T149	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	3		T5	15		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	10		T233	6		T49	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T142	7		T263	1		T145	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	15		T136	1		T158	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	14		T12	1		T144	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	2		T139	1		T130	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T50	11		T136	1		T170	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T45	6		T137	3		T32	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T142	5		T130	7		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	7		T51	17		T234	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T140	3		T138	18		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T25	32		T140	11		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	14		T12	1		T15	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T137	10		T46	10		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T12	1		T42	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	5		T158	14		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T150	1		T92	6		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T57	5		T131	10		T176	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T135	16		T234	12		T17	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	1		T149	2		T256	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T8	18		T13	23		T52	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T50	8		T233	6		T49	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T142	11		T135	16		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T158	12		T138	28		T150	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T171	9		T93	11		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T130	12		T232	11		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	10		T267	1		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T45	2		T137	4		T33	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T142	4		T130	1		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	12		T234	15		T232	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T138	16		T131	14		T150	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T25	27		T159	2		T200	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T3	13		T15	7		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T137	9		T46	1		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T42	6		T33	2		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	4		T158	16		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T150	2		T92	8		T172	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T281	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	439	1			T54	3		T34	4		T35	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T234	13		T277	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T240	2		T274	4		T106	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T273	1		T278	1		T279	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T140	5		T157	13		T135	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T143	14		T47	5		T149	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T2	3		T5	15		T11	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T50	10		T233	6		T270	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	1		T142	7		T145	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	15		T158	12		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	3		T263	1		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T136	1		T32	13		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T4	11		T12	1		T50	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T51	2		T33	1		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T142	5		T130	7		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T51	17		T45	6		T137	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T140	3		T138	18		T144	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	7		T140	11		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	12		T141	1		T147	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T25	32		T46	10		T229	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T3	14		T12	2		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	5		T137	10		T158	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16693	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T234	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T274	11		T106	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T278	6		T279	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T135	16		T234	12		T17	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T47	1		T149	2		T49	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T13	23		T52	10		T40	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T50	8		T233	6		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	18		T142	11		T135	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T158	12		T138	13		T150	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T199	2		T171	9		T253	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T138	15		T130	12		T131	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	10		T93	11		T280	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T33	12		T243	9		T152	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T142	4		T130	1		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	12		T45	2		T137	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T138	16		T131	14		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T234	15		T232	14		T246	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T15	7		T17	3		T92	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	27		T46	1		T229	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	13		T42	6		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	4		T137	9		T158	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23