Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23155

1

T1

12

T2

3

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3612

1

T3

27

T4

3

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20279

1

T1

12

T3

9

T6

15

auto[1]

6488

1

T2

3

T3

27

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T139	1		T282	1		T283	9
values[0]	119	1			T135	35		T232	30		T186	21
values[1]	710	1			T50	18		T136	1		T131	34
values[2]	700	1			T12	1		T32	13		T138	27
values[3]	726	1			T6	15		T12	1		T140	19
values[4]	824	1			T3	27		T45	8		T33	3
values[5]	809	1			T8	19		T51	2		T25	32
values[6]	828	1			T4	14		T6	7		T137	19
values[7]	570	1			T51	29		T137	7		T15	19
values[8]	810	1			T32	11		T33	13		T138	34
values[9]	3528	1			T2	3		T3	9		T5	15
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T12	1		T50	18		T136	1
values[1]	732	1			T32	13		T138	27		T141	1
values[2]	694	1			T6	15		T12	1		T140	19
values[3]	968	1			T3	27		T45	8		T33	3
values[4]	775	1			T4	11		T6	7		T8	19
values[5]	792	1			T4	3		T137	19		T243	22
values[6]	3033	1			T2	3		T5	15		T11	19
values[7]	507	1			T32	11		T33	13		T135	28
values[8]	897	1			T12	1		T42	7		T136	1
values[9]	304	1			T3	9		T50	21		T158	30
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	1		T50	9		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T142	14		T143	1		T135	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T32	1		T138	14		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T141	1		T142	12		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T140	2		T130	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T140	1		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T147	1		T131	13		T199	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	14		T45	6		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	1		T8	19		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T6	1		T51	1		T25	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T137	10		T243	10		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	1		T149	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1686	1			T2	3		T5	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	13		T148	1		T284	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T32	1		T150	13		T17	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	13		T135	17		T257	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	1		T136	1		T158	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T42	7		T138	17		T47	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T3	5		T50	11		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T158	17		T138	16		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T50	9		T131	9		T234	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T142	15		T143	13		T135	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T32	12		T138	13		T131	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	6		T157	9		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T140	12		T130	6		T57	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	14		T140	4		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T147	9		T131	7		T199	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	13		T45	2		T234	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T4	10		T285	13		T154	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	6		T51	1		T25	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T137	9		T243	12		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	2		T149	10		T244	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T5	14		T11	17		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	16		T286	15		T287	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T32	10		T17	13		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T135	11		T257	6		T152	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T158	11		T25	15		T145	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	17		T47	2		T170	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T3	4		T50	10		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T158	13		T138	11		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T139	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T282	1		T283	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T232	12		T186	21		T106	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T135	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	9		T136	1		T131	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T160	1		T153	1		T249	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T32	1		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T141	1		T142	26		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T140	2		T57	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T140	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T130	2		T147	1		T199	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	14		T45	6		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	19		T161	1		T285	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T51	1		T25	17		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	1		T137	10		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T6	1		T159	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	5		T15	10		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	13		T149	1		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T32	1		T263	1		T130	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T33	13		T138	17		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1803	1			T2	3		T3	5		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T42	7		T158	17		T138	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T232	18		T106	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T135	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T50	9		T131	18		T234	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T160	2		T249	8		T19	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	12		T138	13		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T142	21		T143	13		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	12		T57	4		T131	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	14		T140	4		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T130	6		T147	9		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	13		T45	2		T142	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T285	13		T19	2		T163	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T51	1		T25	15		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	10		T137	9		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	2		T6	6		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T137	2		T15	9		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	16		T149	10		T244	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	10		T130	11		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	17		T135	11		T257	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T3	4		T5	14		T11	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T158	13		T138	11		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T12	1		T50	10		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	16		T143	14		T135	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T32	13		T138	14		T131	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T141	1		T142	7		T157	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T140	14		T130	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	15		T140	5		T142	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T147	10		T131	8		T199	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	14		T45	6		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	11		T8	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	7		T51	2		T25	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T137	10		T243	13		T130	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	3		T149	11		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	3		T5	15		T11	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	17		T148	1		T284	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T32	11		T150	1		T17	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T33	1		T135	12		T257	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	1		T136	1		T158	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T42	1		T138	18		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T3	5		T50	11		T157	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T158	14		T138	12		T144	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T50	8		T131	14		T234	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T142	13		T135	16		T249	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T138	13		T16	1		T92	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T142	11		T234	12		T91	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T130	1		T18	1		T280	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T142	4		T46	1		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T131	12		T199	4		T171	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	13		T45	2		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	18		T159	11		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T25	16		T233	6		T150	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T137	9		T243	9		T130	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T261	5		T162	4		T210	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T13	23		T52	10		T40	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T51	12		T286	12		T287	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T150	12		T17	11		T256	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	12		T135	16		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T158	12		T25	11		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T42	6		T138	16		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T3	4		T50	10		T289	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T158	16		T138	15		T290	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T139	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T282	1		T283	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T232	19		T186	1		T106	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T135	19		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T50	10		T136	1		T131	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T160	3		T153	1		T249	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T32	13		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T141	1		T142	23		T143	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T140	14		T57	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	15		T140	5		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T130	7		T147	10		T199	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	14		T45	6		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	1		T161	1		T285	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T51	2		T25	16		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	11		T137	10		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	3		T6	7		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T137	3		T15	12		T130	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T51	17		T149	11		T244	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T32	11		T263	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T33	1		T138	18		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T2	3		T3	5		T5	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T42	1		T158	14		T138	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T283	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T232	11		T186	20		T106	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T135	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T50	8		T131	14		T234	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T249	5		T19	3		T210	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T138	13		T16	1		T92	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T142	24		T234	12		T91	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	12		T171	9		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T229	1		T92	2		T291	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T130	1		T199	4		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	13		T45	2		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	18		T253	11		T19	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T25	16		T233	6		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T137	9		T243	9		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	2		T162	4		T172	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T137	4		T15	7		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T51	12		T261	5		T287	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	10		T150	12		T17	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	12		T138	16		T135	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T3	4		T13	23		T50	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T42	6		T158	16		T138	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23