Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23063

1

T1

12

T2

3

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3704

1

T3

27

T4

11

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20407

1

T1

12

T3

36

T6

22

auto[1]

6360

1

T2

3

T4

14

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T251	7		-	-		-	-
values[0]	72	1			T140	5		T267	4		T291	11
values[1]	688	1			T50	18		T51	29		T141	1
values[2]	840	1			T136	1		T138	27		T144	14
values[3]	741	1			T4	11		T42	7		T45	8
values[4]	2950	1			T2	3		T3	27		T5	15
values[5]	916	1			T3	9		T136	1		T158	24
values[6]	874	1			T4	3		T50	21		T158	30
values[7]	769	1			T6	15		T12	1		T25	32
values[8]	653	1			T6	7		T51	2		T25	27
values[9]	1125	1			T12	2		T33	16		T140	3
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1030	1			T50	18		T136	1		T140	5
values[1]	712	1			T4	11		T51	29		T32	11
values[2]	700	1			T42	7		T45	8		T137	19
values[3]	3037	1			T2	3		T3	27		T5	15
values[4]	903	1			T4	3		T136	1		T32	13
values[5]	937	1			T3	9		T50	21		T158	30
values[6]	666	1			T6	15		T12	1		T51	2
values[7]	683	1			T6	7		T140	11		T141	1
values[8]	884	1			T12	2		T33	3		T140	3
values[9]	80	1			T33	13		T47	6		T229	2
minimum	17135	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T50	9		T136	1		T138	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T140	1		T141	1		T270	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T233	7		T157	1		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	1		T51	13		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T45	6		T137	10		T138	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T42	7		T138	16		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T2	3		T5	1		T8	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	14		T158	13		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T4	1		T136	1		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T32	1		T243	10		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T3	5		T50	11		T158	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T157	1		T93	12		T288	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T51	1		T142	5		T130	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	1		T12	1		T25	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T140	1		T139	1		T199	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	1		T141	1		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T33	3		T140	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	2		T130	24		T135	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T229	1		T201	1		T292	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T33	13		T47	4		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	9		T138	13		T144	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T140	4		T270	12		T60	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T233	5		T157	9		T92	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T4	10		T51	16		T32	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T45	2		T137	9		T138	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T138	11		T232	29		T287	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T5	14		T11	17		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	13		T158	11		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	2		T142	15		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T32	12		T243	12		T135	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T3	4		T50	10		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T157	12		T93	13		T288	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T51	1		T142	4		T130	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	14		T25	15		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T140	10		T199	4		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	6		T142	6		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T140	2		T147	9		T199	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T130	17		T135	11		T17	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T229	1		T292	1		T294	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T47	2		T244	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T251	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T267	3		T291	11		T185	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T140	1		T164	11		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T50	9		T144	1		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T51	13		T141	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T136	1		T138	14		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T144	1		T131	13		T171	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	6		T137	10		T138	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	1		T42	7		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T2	3		T5	1		T8	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	14		T138	16		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	5		T136	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T158	13		T32	1		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T4	1		T50	11		T158	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T157	1		T93	12		T288	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T25	17		T142	5		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T12	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T51	1		T140	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	1		T25	12		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T33	3		T140	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T12	2		T33	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T267	1		T185	9		T22	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T140	4		T164	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	9		T144	10		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	16		T93	13		T257	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	13		T157	9		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T144	13		T131	7		T171	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T45	2		T137	9		T138	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	10		T32	10		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T5	14		T11	17		T14	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	13		T138	11		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	4		T142	15		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T158	11		T32	12		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	2		T50	10		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T157	12		T93	13		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T25	15		T142	4		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	14		T145	14		T288	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T51	1		T140	10		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	6		T25	15		T142	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T140	2		T147	9		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	17		T47	2		T17	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T50	10		T136	1		T138	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T140	5		T141	1		T270	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T233	6		T157	10		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T4	11		T51	17		T32	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T45	6		T137	10		T138	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T42	1		T138	12		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	3		T5	15		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	14		T158	12		T143	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	3		T136	1		T142	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T32	13		T243	13		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T3	5		T50	11		T158	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T157	13		T93	14		T288	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T51	2		T142	5		T130	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	15		T12	1		T25	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T140	11		T139	1		T199	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	7		T141	1		T142	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T33	1		T140	3		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	2		T130	19		T135	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T229	2		T201	1		T292	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T33	1		T47	5		T244	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17133	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T293	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T50	8		T138	13		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T270	10		T154	12		T253	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T233	6		T92	2		T250	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T51	12		T131	12		T171	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T45	2		T137	9		T138	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T42	6		T138	15		T232	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T8	18		T13	23		T52	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	13		T158	12		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T142	13		T152	10		T162	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T243	9		T135	16		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	4		T50	10		T158	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T93	11		T162	9		T245	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T142	4		T130	1		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T25	11		T16	1		T150	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T199	4		T205	10		T295	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T142	11		T131	14		T234	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T33	2		T199	2		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T130	22		T135	16		T17	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T294	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T33	12		T47	1		T172	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T251	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T267	3		T291	1		T185	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T140	5		T164	8		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T50	10		T144	11		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	17		T141	1		T93	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T136	1		T138	14		T157	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T144	14		T131	8		T171	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	6		T137	10		T138	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T4	11		T42	1		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T2	3		T5	15		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	14		T138	12		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	5		T136	1		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T158	12		T32	13		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T4	3		T50	11		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T157	13		T93	14		T288	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T25	16		T142	5		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	15		T12	1		T145	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T51	2		T140	11		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T6	7		T25	16		T142	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T33	1		T140	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	2		T33	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T251	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T267	1		T291	10		T185	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T164	10		T296	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T50	8		T46	1		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T51	12		T249	5		T164	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T138	13		T17	3		T92	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T131	12		T171	9		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T45	2		T137	9		T138	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T42	6		T232	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T8	18		T13	23		T52	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	13		T138	15		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	4		T142	13		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T158	12		T243	9		T135	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T50	10		T158	16		T15	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T93	11		T152	16		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T25	16		T142	4		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T150	15		T200	12		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T130	1		T164	2		T295	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T25	11		T142	11		T131	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T33	2		T199	6		T234	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	12		T130	22		T47	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23