Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23440

1

T1

12

T2

3

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3327

1

T3

9

T12

2

T42

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20236

1

T1

12

T3

9

T4

3

auto[1]

6531

1

T2

3

T3

27

T4

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T297	13		-	-		-	-
values[0]	48	1			T234	28		T92	13		T292	4
values[1]	552	1			T12	2		T25	32		T149	11
values[2]	512	1			T3	9		T137	7		T138	27
values[3]	671	1			T4	11		T50	21		T158	30
values[4]	717	1			T3	27		T136	2		T33	3
values[5]	3198	1			T2	3		T4	3		T5	15
values[6]	590	1			T50	18		T51	2		T42	7
values[7]	867	1			T6	22		T33	13		T138	61
values[8]	811	1			T137	19		T142	29		T139	1
values[9]	1656	1			T8	19		T12	1		T51	29
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	710	1			T12	2		T25	32		T149	11
values[1]	506	1			T3	9		T4	11		T46	1
values[2]	579	1			T50	21		T136	1		T137	7
values[3]	3194	1			T2	3		T5	15		T11	19
values[4]	777	1			T3	27		T4	3		T42	7
values[5]	744	1			T6	7		T50	18		T51	2
values[6]	774	1			T6	15		T33	13		T138	61
values[7]	849	1			T8	19		T12	1		T137	19
values[8]	1171	1			T45	8		T158	24		T32	13
values[9]	298	1			T51	29		T157	10		T256	25
minimum	17165	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T149	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T25	17		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	1		T47	4		T135	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T3	5		T46	1		T298	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	11		T138	16		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T136	1		T137	5		T158	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1752	1			T2	3		T5	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T142	5		T233	7		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T3	14		T4	1		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	7		T25	12		T131	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	1		T50	9		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T139	1		T131	15		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T33	13		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T138	31		T141	1		T199	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	19		T140	1		T250	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T137	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T45	6		T32	1		T130	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T158	13		T142	14		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	13		T256	15		T152	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T157	1		T151	1		T261	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17011	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T288	1		T200	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T149	10		T145	13		T170	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T25	15		T145	14		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	10		T47	2		T135	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T3	4		T154	4		T19	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T50	10		T138	11		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T137	2		T158	13		T15	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T5	14		T11	17		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T142	4		T233	5		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	13		T4	2		T130	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	15		T131	7		T199	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	6		T50	9		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T131	9		T170	4		T271	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	14		T16	1		T171	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T138	30		T199	3		T257	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	2		T272	1		T287	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T137	9		T147	9		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T45	2		T32	12		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T158	11		T142	15		T46	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T51	16		T256	10		T152	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T157	9		T265	13		T212	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T288	2		T200	13		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T292	3		T191	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T234	16		T92	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T149	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	1		T25	17		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	16		T47	4		T135	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	5		T137	5		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	1		T50	11		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T158	17		T15	10		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	14		T136	1		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T136	1		T142	5		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1801	1			T2	3		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	12		T233	7		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	9		T51	1		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T42	7		T141	1		T131	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	2		T33	13		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T138	31		T139	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T139	1		T263	1		T299	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T137	10		T142	14		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	615	1			T8	19		T51	13		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T12	1		T158	13		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T297	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T292	1		T191	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T234	12		T92	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T149	10		T145	13		T170	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	15		T229	1		T288	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T138	11		T47	2		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T3	4		T137	2		T145	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	10		T50	10		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T158	13		T15	9		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	13		T140	4		T142	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T142	4		T232	11		T92	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T4	2		T5	14		T11	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T25	15		T233	5		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T50	9		T51	1		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T131	9		T199	3		T300	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	20		T16	1		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T138	30		T170	4		T271	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T287	11		T245	10		T301	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T137	9		T142	15		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	415	1			T51	16		T45	2		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T158	11		T157	9		T46	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	1		T149	11		T145	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T25	16		T145	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	11		T47	5		T135	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	5		T46	1		T298	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	11		T138	12		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T136	1		T137	3		T158	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T2	3		T5	15		T11	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T142	5		T233	6		T157	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	14		T4	3		T130	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	1		T25	16		T131	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T6	7		T50	10		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T139	1		T131	10		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	15		T33	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T138	32		T141	1		T199	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	1		T140	3		T250	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T137	10		T147	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T45	6		T32	13		T130	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T158	12		T142	16		T46	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T51	17		T256	16		T152	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T157	10		T151	1		T261	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17135	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T288	3		T200	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	5		T18	1		T247	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T25	16		T234	15		T92	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	1		T135	16		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T3	4		T154	4		T172	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T50	10		T138	15		T290	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T137	4		T158	16		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T13	23		T52	10		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T142	4		T233	6		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	13		T130	12		T234	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T42	6		T25	11		T131	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	8		T243	9		T130	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T131	14		T271	11		T302	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	12		T16	1		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T138	29		T199	2		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	18		T250	15		T272	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T137	9		T149	2		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T45	2		T130	1		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T158	12		T142	13		T91	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T51	12		T256	9		T152	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T265	9		T212	14		T303	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T267	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T200	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T297	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T292	4		T191	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T234	13		T92	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T149	11		T145	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	1		T25	16		T229	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	12		T47	5		T135	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	5		T137	3		T145	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	11		T50	11		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T158	14		T15	12		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	14		T136	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	1		T142	5		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T2	3		T4	3		T5	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T25	16		T233	6		T157	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	10		T51	2		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T42	1		T141	1		T131	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T6	22		T33	1		T16	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T138	32		T139	1		T170	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T139	1		T263	1		T299	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T137	10		T142	16		T147	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	519	1			T8	1		T51	17		T45	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T12	1		T158	12		T157	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T234	15		T92	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	5		T18	1		T267	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T25	16		T200	12		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	15		T47	1		T135	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	4		T137	4		T154	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	10		T17	3		T19	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T158	16		T15	7		T46	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	13		T33	2		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T142	4		T232	11		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T13	23		T52	10		T40	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	11		T233	6		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T50	8		T243	9		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T42	6		T131	14		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	12		T16	1		T171	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T138	29		T271	11		T237	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T287	14		T245	9		T304	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	9		T142	13		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	511	1			T8	18		T51	12		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T158	12		T149	2		T91	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23