Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23164

1

T1

12

T2

3

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3603

1

T3

9

T4

11

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20334

1

T1

12

T3

36

T4

14

auto[1]

6433

1

T2

3

T5

15

T6

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	67	1			T305	7		T238	13		T207	34
values[0]	46	1			T131	20		T290	15		T306	11
values[1]	663	1			T3	27		T4	3		T50	21
values[2]	811	1			T50	18		T25	32		T140	5
values[3]	881	1			T12	1		T51	2		T45	8
values[4]	563	1			T8	19		T42	7		T32	11
values[5]	705	1			T6	15		T12	1		T136	1
values[6]	712	1			T3	9		T4	11		T158	24
values[7]	694	1			T51	29		T137	7		T46	3
values[8]	3122	1			T2	3		T5	15		T6	7
values[9]	1371	1			T12	1		T136	1		T137	19
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T3	27		T4	3		T50	21
values[1]	853	1			T50	18		T51	2		T45	8
values[2]	739	1			T12	1		T42	7		T15	19
values[3]	746	1			T6	15		T8	19		T158	30
values[4]	541	1			T3	9		T12	1		T136	1
values[5]	694	1			T4	11		T51	29		T158	24
values[6]	3203	1			T2	3		T5	15		T11	19
values[7]	782	1			T6	7		T138	27		T147	10
values[8]	1005	1			T12	1		T136	1		T137	19
values[9]	185	1			T140	3		T263	1		T135	35
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	14		T4	1		T130	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T50	11		T140	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	1		T45	6		T57	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T50	9		T25	17		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T15	10		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T42	7		T138	17		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	1		T158	17		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	19		T243	10		T130	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T136	1		T33	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	5		T25	12		T47	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T158	13		T139	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	1		T51	13		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1732	1			T2	3		T5	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T46	2		T256	1		T162	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T138	16		T147	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	1		T157	1		T131	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	1		T137	10		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T136	1		T138	14		T142	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T140	1		T135	17		T237	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T263	1		T284	1		T264	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	13		T4	2		T130	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	10		T140	4		T131	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T51	1		T45	2		T57	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	9		T25	15		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	9		T140	10		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	17		T233	5		T48	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	14		T158	13		T32	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T243	12		T130	11		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T144	13		T257	10		T285	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T3	4		T25	15		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T158	11		T49	8		T17	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	10		T51	16		T60	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T5	14		T11	17		T14	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T46	1		T256	7		T162	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T138	11		T147	9		T232	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	6		T157	9		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T137	9		T32	12		T142	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T138	13		T142	15		T170	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T140	2		T135	18		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T307	7		T308	4		T309	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T238	11		T207	18		T310	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T305	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T131	13		T290	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	14		T4	1		T130	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T50	11		T145	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T46	2		T131	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T50	9		T25	17		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T51	1		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T141	1		T233	7		T234	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	1		T33	3		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	19		T42	7		T138	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	1		T12	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	12		T243	10		T130	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T158	13		T33	13		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	5		T4	1		T47	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T137	5		T170	1		T234	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T51	13		T46	2		T256	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T2	3		T5	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	1		T157	1		T131	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T12	1		T137	10		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T136	1		T138	14		T142	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T238	2		T207	16		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T305	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T306	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T131	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	13		T4	2		T130	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	10		T145	13		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T46	5		T131	9		T145	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	9		T25	15		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T51	1		T45	2		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T233	5		T234	12		T275	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T32	10		T140	10		T142	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T138	17		T48	2		T17	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	14		T173	1		T272	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	15		T243	12		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T158	11		T144	13		T49	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	4		T4	10		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	2		T170	4		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T51	16		T46	1		T256	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T5	14		T11	17		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	6		T157	9		T131	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T137	9		T32	12		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T138	13		T142	15		T170	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	14		T4	3		T130	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T50	11		T140	5		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T51	2		T45	6		T57	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	10		T25	16		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	1		T15	12		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	1		T138	18		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	15		T158	14		T32	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T243	13		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T136	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	5		T25	16		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T158	12		T139	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	11		T51	17		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T2	3		T5	15		T11	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T46	2		T256	8		T162	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T138	12		T147	10		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	7		T157	10		T131	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	1		T137	10		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T136	1		T138	14		T142	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T140	3		T135	19		T237	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T263	1		T284	1		T264	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	13		T130	12		T199	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T50	10		T131	12		T290	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T45	2		T48	1		T150	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T50	8		T25	16		T199	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T15	7		T33	2		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T42	6		T138	16		T233	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T158	16		T130	1		T150	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	18		T243	9		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T33	12		T173	1		T272	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T3	4		T25	11		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T158	12		T49	5		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T51	12		T159	11		T172	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T13	23		T52	10		T40	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	1		T162	11		T154	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T138	15		T232	14		T91	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T131	14		T93	11		T255	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T137	9		T142	11		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T138	13		T142	13		T234	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T135	16		T237	2		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T307	6		T308	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T238	3		T207	17		T310	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T305	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T306	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T131	8		T290	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	14		T4	3		T130	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	11		T145	14		T229	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T46	7		T131	10		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	10		T25	16		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T51	2		T45	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T141	1		T233	6		T234	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T32	11		T33	1		T140	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	1		T42	1		T138	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	15		T12	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T25	16		T243	13		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T158	12		T33	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	5		T4	11		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T137	3		T170	5		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T51	17		T46	2		T256	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T2	3		T5	15		T11	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	7		T157	10		T131	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T12	1		T137	10		T32	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T136	1		T138	14		T142	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T238	10		T207	17		T311	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T305	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T131	12		T290	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	13		T130	12		T229	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T50	10		T252	12		T291	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T199	4		T232	11		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T50	8		T25	16		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	2		T158	16		T15	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T233	6		T234	15		T275	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T33	2		T142	4		T130	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	18		T42	6		T138	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T173	1		T272	1		T287	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T25	11		T243	9		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T158	12		T33	12		T49	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	4		T47	1		T159	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	4		T234	12		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T51	12		T46	1		T162	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T13	23		T52	10		T40	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T131	14		T162	4		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T137	9		T142	11		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T138	13		T142	13		T234	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23