Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23058

1

T1

12

T2

3

T3

9

auto[ADC_CTRL_FILTER_COND_OUT]

3709

1

T3

27

T4

11

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20407

1

T1

12

T3

36

T6

22

auto[1]

6360

1

T2

3

T4

14

T5

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	280	1			T12	1		T130	22		T147	10
values[0]	7	1			T279	6		T312	1		-	-
values[1]	787	1			T50	18		T51	29		T140	5
values[2]	782	1			T136	1		T138	27		T144	14
values[3]	773	1			T4	11		T42	7		T45	8
values[4]	2991	1			T2	3		T3	27		T5	15
values[5]	885	1			T3	9		T136	1		T158	24
values[6]	854	1			T4	3		T50	21		T158	30
values[7]	720	1			T6	15		T12	1		T25	32
values[8]	671	1			T6	7		T51	2		T25	27
values[9]	885	1			T12	1		T33	16		T140	3
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	770	1			T50	18		T51	29		T136	1
values[1]	702	1			T32	11		T138	27		T233	12
values[2]	696	1			T4	11		T42	7		T45	8
values[3]	3114	1			T2	3		T3	27		T5	15
values[4]	874	1			T3	9		T4	3		T136	1
values[5]	900	1			T50	21		T158	30		T15	19
values[6]	656	1			T6	15		T12	1		T25	27
values[7]	659	1			T6	7		T51	2		T140	14
values[8]	928	1			T12	2		T33	16		T139	1
values[9]	82	1			T244	9		T172	16		T313	1
minimum	17386	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T50	9		T136	1		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T51	13		T140	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T138	14		T233	7		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	1		T144	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T45	6		T137	10		T138	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T42	7		T138	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1707	1			T2	3		T5	1		T8	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	14		T158	13		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	5		T4	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T32	1		T243	10		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T50	11		T158	17		T15	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T93	12		T288	2		T162	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T142	5		T130	2		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	1		T12	1		T25	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T51	1		T140	2		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T6	1		T141	1		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T33	3		T139	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	2		T33	13		T130	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T314	3		T294	13		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T244	1		T172	16		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17078	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T93	1		T257	1		T164	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	9		T144	10		T17	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	16		T140	4		T270	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T138	13		T233	5		T157	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T32	10		T144	13		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	2		T137	9		T138	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	10		T138	11		T232	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T5	14		T11	17		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	13		T158	11		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	4		T4	2		T142	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T32	12		T243	12		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T50	10		T158	13		T15	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T93	13		T288	18		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	4		T130	6		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	14		T25	15		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T51	1		T140	12		T199	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	6		T142	6		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T147	9		T199	3		T234	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T130	17		T47	2		T135	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T294	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T244	8		T315	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T45	3		T57	1		T46	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T93	13		T257	6		T164	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T147	1		T199	3		T152	20
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T12	1		T130	11		T47	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T279	6		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T50	9		T144	1		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T51	13		T140	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T136	1		T138	14		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T144	1		T131	13		T171	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T45	6		T137	10		T138	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	1		T42	7		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T2	3		T5	1		T8	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	14		T138	16		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	5		T136	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T158	13		T32	1		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T4	1		T50	11		T158	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T157	1		T93	12		T288	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T25	17		T142	5		T130	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T12	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T51	1		T140	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	1		T25	12		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T33	3		T140	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T33	13		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T147	9		T199	3		T152	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T130	11		T47	2		T17	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T50	9		T144	10		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	16		T140	4		T270	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	13		T157	9		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T144	13		T131	7		T171	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T45	2		T137	9		T138	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	10		T32	10		T157	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T5	14		T11	17		T14	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	13		T138	11		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	4		T142	15		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T158	11		T32	12		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	2		T50	10		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T157	12		T93	13		T288	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T25	15		T142	4		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	14		T145	14		T288	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T51	1		T140	10		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	6		T25	15		T142	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T140	2		T199	4		T234	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T130	6		T135	11		T19	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	10		T136	1		T144	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T51	17		T140	5		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	14		T233	6		T157	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T32	11		T144	14		T157	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T45	6		T137	10		T138	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	11		T42	1		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T2	3		T5	15		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	14		T158	12		T143	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	5		T4	3		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T32	13		T243	13		T157	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T50	11		T158	14		T15	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T93	14		T288	20		T162	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T142	5		T130	7		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	15		T12	1		T25	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T51	2		T140	14		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	7		T141	1		T142	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T33	1		T139	1		T147	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	2		T33	1		T130	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T314	3		T294	14		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T244	9		T172	1		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17165	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T93	14		T257	7		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	8		T17	3		T92	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	12		T270	10		T154	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T138	13		T233	6		T92	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	12		T171	9		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T45	2		T137	9		T138	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	6		T138	15		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T8	18		T13	23		T52	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	13		T158	12		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	4		T142	13		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T243	9		T135	16		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T50	10		T158	16		T15	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T93	11		T162	9		T316	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	4		T130	1		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T25	11		T16	1		T150	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T199	4		T295	15		T317	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T142	11		T131	14		T234	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T33	2		T199	2		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T33	12		T130	22		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T294	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T172	15		T315	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T46	1		T150	12		T267	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T164	10		T67	4		T306	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T147	10		T199	4		T152	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T12	1		T130	12		T47	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T279	1		T312	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T50	10		T144	11		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T51	17		T140	5		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	1		T138	14		T157	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T144	14		T131	8		T171	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T45	6		T137	10		T138	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T4	11		T42	1		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	3		T5	15		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	14		T138	12		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	5		T136	1		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T158	12		T32	13		T243	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T4	3		T50	11		T158	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T157	13		T93	14		T288	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T25	16		T142	5		T130	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	15		T12	1		T145	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T51	2		T140	11		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T6	7		T25	16		T142	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T33	1		T140	3		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	1		T33	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T199	2		T152	19		T318	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T130	10		T47	1		T17	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T279	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T50	8		T46	1		T150	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T51	12		T270	10		T249	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T138	13		T17	3		T92	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T131	12		T171	9		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T45	2		T137	9		T138	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	6		T232	11		T19	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T8	18		T13	23		T52	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	13		T138	15		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	4		T142	13		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T158	12		T243	9		T135	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T50	10		T158	16		T15	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T93	11		T152	16		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T25	16		T142	4		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T150	15		T200	12		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T164	2		T295	15		T202	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T25	11		T142	11		T131	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T33	2		T199	4		T234	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	12		T130	12		T135	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23