Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26767

1

T1

12

T2

3

T3

36

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23033

1

T1

12

T2

3

T3

36

auto[ADC_CTRL_FILTER_COND_OUT]

3734

1

T4

11

T6

15

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20411

1

T1

12

T3

27

T7

10

auto[1]

6356

1

T2

3

T3

9

T4

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22469

1

T1

12

T2

3

T3

19

auto[1]

4298

1

T3

17

T4

12

T5

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T319	14		-	-		-	-
values[0]	99	1			T51	29		T131	24		T160	12
values[1]	727	1			T3	27		T137	26		T15	19
values[2]	849	1			T4	3		T6	22		T12	1
values[3]	725	1			T3	9		T4	11		T50	18
values[4]	685	1			T32	11		T243	22		T157	13
values[5]	3013	1			T2	3		T5	15		T11	19
values[6]	628	1			T12	1		T158	24		T131	10
values[7]	927	1			T50	21		T51	2		T42	7
values[8]	605	1			T8	19		T12	1		T57	5
values[9]	1363	1			T136	1		T45	8		T25	27
minimum	17132	1			T1	12		T7	10		T9	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1069	1			T3	27		T4	3		T6	22
values[1]	785	1			T3	9		T12	1		T147	10
values[2]	766	1			T4	11		T50	18		T32	11
values[3]	2950	1			T2	3		T5	15		T11	19
values[4]	627	1			T158	24		T25	32		T33	3
values[5]	719	1			T12	1		T50	21		T51	2
values[6]	841	1			T42	7		T158	30		T263	1
values[7]	744	1			T8	19		T12	1		T136	1
values[8]	872	1			T140	11		T138	88		T141	1
values[9]	193	1			T140	5		T130	8		T244	9
minimum	17201	1			T1	12		T7	10		T9	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

4403

1

T3

17

T8

18

T13

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T3	14		T4	1		T6	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T182	1		T232	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	5		T12	1		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T147	1		T46	2		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T50	9		T140	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	1		T32	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T2	3		T5	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T243	10		T152	17		T253	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	17		T157	1		T234	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T158	13		T33	3		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T136	1		T142	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T50	11		T51	1		T199	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	7		T144	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T158	17		T263	1		T47	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T136	1		T45	6		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	19		T12	1		T25	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T140	1		T138	17		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T138	30		T141	1		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T140	1		T130	2		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T244	1		T201	1		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T51	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T3	13		T4	2		T6	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	14		T232	18		T92	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	4		T145	14		T229	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T147	9		T46	1		T131	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	9		T140	2		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	10		T32	10		T130	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T5	14		T11	17		T14	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T243	12		T152	10		T287	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	15		T157	9		T234	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T158	11		T93	13		T19	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T142	15		T131	9		T92	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T50	10		T51	1		T199	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T144	13		T171	8		T270	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T158	13		T47	2		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	2		T170	1		T49	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T25	15		T233	5		T149	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T140	10		T138	17		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T138	24		T142	6		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T140	4		T130	6		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T244	8		T19	1		T320	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	3		T57	1		T46	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T51	16		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T319	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T131	15		T212	8		T310	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T51	13		T160	1		T321	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	14		T137	15		T15	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T182	1		T232	12		T256	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T6	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	1		T147	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	5		T50	9		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	1		T139	1		T130	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T157	1		T170	1		T18	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T32	1		T243	10		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T2	3		T5	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	3		T93	1		T152	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T131	1		T159	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T158	13		T16	3		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T42	7		T136	1		T142	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T50	11		T51	1		T158	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T170	1		T49	10		T199	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	19		T12	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T136	1		T45	6		T140	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T25	12		T33	13		T138	30
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17008	1			T1	12		T7	10		T9	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T131	9		T212	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T51	16		T160	11		T321	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	13		T137	11		T15	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T232	18		T256	7		T152	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	2		T6	6		T140	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T6	14		T147	9		T46	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	4		T50	9		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	10		T130	6		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T157	12		T170	4		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T32	10		T243	12		T46	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	14		T11	17		T14	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T93	13		T152	10		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T131	9		T173	1		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T158	11		T16	1		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T142	15		T144	13		T171	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T50	10		T51	1		T158	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T170	1		T49	8		T199	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T57	4		T47	2		T48	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T45	2		T140	14		T138	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T25	15		T138	24		T142	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T57	1		T46	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T3	14		T4	3		T6	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	15		T182	1		T232	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	5		T12	1		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T147	10		T46	2		T131	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T50	10		T140	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T4	11		T32	11		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T2	3		T5	15		T11	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T243	13		T152	11		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T25	16		T157	10		T234	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T158	12		T33	1		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T136	1		T142	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T50	11		T51	2		T199	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T42	1		T144	14		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T158	14		T263	1		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T136	1		T45	6		T170	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T12	1		T25	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T140	11		T138	18		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T138	26		T141	1		T142	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T140	5		T130	7		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T244	9		T201	1		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17147	1			T1	12		T7	10		T9	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T51	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T3	13		T137	13		T15	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T232	11		T92	4		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	4		T162	9		T286	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	1		T131	12		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T50	8		T142	4		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T130	12		T172	20		T210	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T13	23		T52	10		T40	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T243	9		T152	16		T253	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T25	16		T234	15		T249	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T158	12		T33	2		T19	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T142	13		T159	11		T92	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T50	10		T199	4		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	6		T150	12		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T158	16		T47	1		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T45	2		T49	5		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	18		T25	11		T33	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T138	16		T135	16		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T138	28		T142	11		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T130	1		T247	12		T231	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T19	1		T68	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T322	3		T323	9		T324	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T51	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T319	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T131	10		T212	11		T310	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T51	17		T160	12		T321	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	14		T137	13		T15	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T182	1		T232	19		T256	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T4	3		T6	7		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	15		T147	10		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	5		T50	10		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	11		T139	1		T130	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T157	13		T170	5		T18	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T32	11		T243	13		T46	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T2	3		T5	15		T11	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	1		T93	14		T152	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T131	10		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T158	12		T16	3		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T42	1		T136	1		T142	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T50	11		T51	2		T158	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T170	2		T49	13		T199	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T12	1		T57	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T136	1		T45	6		T140	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T25	16		T33	1		T138	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17132	1			T1	12		T7	10		T9	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T319	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T131	14		T212	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T51	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	13		T137	13		T15	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T232	11		T152	10		T162	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T135	16		T229	1		T91	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T46	1		T232	14		T92	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	4		T50	8		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T130	12		T131	12		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T18	1		T93	11		T200	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T243	9		T172	15		T287	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T13	23		T52	10		T40	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T33	2		T152	16		T253	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T159	11		T173	1		T291	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T158	12		T16	1		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	6		T142	13		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T50	10		T158	16		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T49	5		T199	2		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	18		T47	1		T234	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	2		T138	16		T130	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T25	11		T33	12		T138	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22364

1

T1

12

T2

3

T3

19

auto[1]

auto[0]

4403

1

T3

17

T8

18

T13

23