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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.68 99.07 96.67 100.00 100.00 98.83 98.33 90.87


Total test records in report: 918
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T794 /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1536068655 Jul 04 07:00:24 PM PDT 24 Jul 04 07:09:35 PM PDT 24 493565680317 ps
T795 /workspace/coverage/default/32.adc_ctrl_lowpower_counter.495070352 Jul 04 07:04:26 PM PDT 24 Jul 04 07:04:52 PM PDT 24 22150675226 ps
T796 /workspace/coverage/default/26.adc_ctrl_alert_test.3280925825 Jul 04 07:03:15 PM PDT 24 Jul 04 07:03:17 PM PDT 24 513766750 ps
T110 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.995992340 Jul 04 06:53:40 PM PDT 24 Jul 04 06:53:42 PM PDT 24 395538069 ps
T64 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2255073538 Jul 04 06:53:46 PM PDT 24 Jul 04 06:53:49 PM PDT 24 3987908215 ps
T65 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3163110526 Jul 04 06:53:42 PM PDT 24 Jul 04 06:53:50 PM PDT 24 8309270920 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2743568611 Jul 04 06:53:19 PM PDT 24 Jul 04 06:53:20 PM PDT 24 596935501 ps
T797 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2967320837 Jul 04 06:53:58 PM PDT 24 Jul 04 06:54:01 PM PDT 24 458246473 ps
T798 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1060562092 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:52 PM PDT 24 371046436 ps
T98 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2793291037 Jul 04 06:53:43 PM PDT 24 Jul 04 06:53:45 PM PDT 24 595115675 ps
T799 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1052953046 Jul 04 06:54:00 PM PDT 24 Jul 04 06:54:01 PM PDT 24 528918781 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1614401909 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:33 PM PDT 24 1231752573 ps
T74 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4291999889 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:40 PM PDT 24 515105147 ps
T81 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1174054117 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:32 PM PDT 24 904687100 ps
T800 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.63687057 Jul 04 06:53:31 PM PDT 24 Jul 04 06:53:32 PM PDT 24 384231152 ps
T61 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3699402014 Jul 04 06:53:44 PM PDT 24 Jul 04 06:53:52 PM PDT 24 2146697624 ps
T801 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.679627150 Jul 04 06:54:04 PM PDT 24 Jul 04 06:54:05 PM PDT 24 496882879 ps
T75 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.725401760 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:55 PM PDT 24 863026828 ps
T80 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.508659716 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:31 PM PDT 24 612821487 ps
T119 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3300483048 Jul 04 06:53:32 PM PDT 24 Jul 04 06:53:33 PM PDT 24 433910762 ps
T113 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.290366947 Jul 04 06:53:23 PM PDT 24 Jul 04 06:53:25 PM PDT 24 596652338 ps
T83 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1152788586 Jul 04 06:53:48 PM PDT 24 Jul 04 06:53:49 PM PDT 24 419696335 ps
T76 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1086115059 Jul 04 06:53:52 PM PDT 24 Jul 04 06:53:56 PM PDT 24 515195829 ps
T62 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3699734230 Jul 04 06:53:48 PM PDT 24 Jul 04 06:53:55 PM PDT 24 2698000210 ps
T108 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1033096375 Jul 04 06:53:44 PM PDT 24 Jul 04 06:53:46 PM PDT 24 541149340 ps
T63 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3012127476 Jul 04 06:53:30 PM PDT 24 Jul 04 06:54:39 PM PDT 24 21170224346 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1950663998 Jul 04 06:53:31 PM PDT 24 Jul 04 06:53:41 PM PDT 24 3896678713 ps
T802 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.319704516 Jul 04 06:53:58 PM PDT 24 Jul 04 06:54:00 PM PDT 24 502753384 ps
T126 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1490548078 Jul 04 06:53:42 PM PDT 24 Jul 04 06:53:48 PM PDT 24 2203165722 ps
T129 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3157415146 Jul 04 06:53:22 PM PDT 24 Jul 04 06:55:05 PM PDT 24 26192158666 ps
T82 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1111230849 Jul 04 06:53:40 PM PDT 24 Jul 04 06:53:41 PM PDT 24 426233790 ps
T77 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.190720867 Jul 04 06:53:44 PM PDT 24 Jul 04 06:53:47 PM PDT 24 921803662 ps
T78 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.911656426 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:33 PM PDT 24 530045294 ps
T803 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2767634349 Jul 04 06:53:50 PM PDT 24 Jul 04 06:53:52 PM PDT 24 508556747 ps
T127 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3950658588 Jul 04 06:53:45 PM PDT 24 Jul 04 06:53:46 PM PDT 24 552846954 ps
T804 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1329998092 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:39 PM PDT 24 408905268 ps
T805 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1141732941 Jul 04 06:53:46 PM PDT 24 Jul 04 06:53:47 PM PDT 24 556021886 ps
T66 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.639184532 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:45 PM PDT 24 8457348861 ps
T806 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.561179271 Jul 04 06:54:05 PM PDT 24 Jul 04 06:54:07 PM PDT 24 493542742 ps
T114 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1261278182 Jul 04 06:53:31 PM PDT 24 Jul 04 06:53:36 PM PDT 24 1252570838 ps
T807 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2077228427 Jul 04 06:53:58 PM PDT 24 Jul 04 06:53:59 PM PDT 24 639429296 ps
T69 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3937086453 Jul 04 06:53:52 PM PDT 24 Jul 04 06:53:54 PM PDT 24 4850953888 ps
T115 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.306077722 Jul 04 06:53:43 PM PDT 24 Jul 04 06:53:44 PM PDT 24 579394151 ps
T128 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3944357109 Jul 04 06:53:55 PM PDT 24 Jul 04 06:53:59 PM PDT 24 2160167555 ps
T808 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3459106404 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:53 PM PDT 24 468349827 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1776628176 Jul 04 06:53:49 PM PDT 24 Jul 04 06:53:56 PM PDT 24 4394009326 ps
T810 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.617052799 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:35 PM PDT 24 4428206502 ps
T811 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1215794697 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:54 PM PDT 24 451630940 ps
T812 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2552169465 Jul 04 06:53:38 PM PDT 24 Jul 04 06:55:47 PM PDT 24 26558484157 ps
T116 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4090320571 Jul 04 06:53:55 PM PDT 24 Jul 04 06:53:57 PM PDT 24 529675636 ps
T813 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.114968548 Jul 04 06:53:23 PM PDT 24 Jul 04 06:53:27 PM PDT 24 4282731375 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2213037097 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:30 PM PDT 24 483590120 ps
T815 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2234754458 Jul 04 06:53:24 PM PDT 24 Jul 04 06:53:29 PM PDT 24 4540346687 ps
T816 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3289438679 Jul 04 06:53:58 PM PDT 24 Jul 04 06:53:59 PM PDT 24 305361883 ps
T817 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4187092606 Jul 04 06:53:40 PM PDT 24 Jul 04 06:53:42 PM PDT 24 524792995 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2824034786 Jul 04 06:53:31 PM PDT 24 Jul 04 06:53:52 PM PDT 24 7813038211 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2909980238 Jul 04 06:53:31 PM PDT 24 Jul 04 06:53:32 PM PDT 24 1183844162 ps
T818 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3604900449 Jul 04 06:53:54 PM PDT 24 Jul 04 06:53:55 PM PDT 24 451887367 ps
T819 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.750107237 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:41 PM PDT 24 568046841 ps
T820 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1899650127 Jul 04 06:53:53 PM PDT 24 Jul 04 06:53:54 PM PDT 24 301765703 ps
T821 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2696954772 Jul 04 06:53:41 PM PDT 24 Jul 04 06:53:43 PM PDT 24 522913146 ps
T822 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2467180519 Jul 04 06:53:58 PM PDT 24 Jul 04 06:54:00 PM PDT 24 509452469 ps
T823 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2676918274 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:33 PM PDT 24 703413755 ps
T824 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3609814674 Jul 04 06:53:46 PM PDT 24 Jul 04 06:53:52 PM PDT 24 2104134790 ps
T825 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1819871765 Jul 04 06:53:47 PM PDT 24 Jul 04 06:53:49 PM PDT 24 444733746 ps
T826 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.840049708 Jul 04 06:53:58 PM PDT 24 Jul 04 06:53:59 PM PDT 24 369197077 ps
T827 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.601226951 Jul 04 06:53:40 PM PDT 24 Jul 04 06:53:43 PM PDT 24 2335953458 ps
T828 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.944100204 Jul 04 06:54:06 PM PDT 24 Jul 04 06:54:07 PM PDT 24 410188025 ps
T829 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4175182247 Jul 04 06:53:54 PM PDT 24 Jul 04 06:53:55 PM PDT 24 525613728 ps
T830 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3529400411 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:40 PM PDT 24 358169953 ps
T118 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3774125908 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:31 PM PDT 24 763320178 ps
T831 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3053542444 Jul 04 06:53:55 PM PDT 24 Jul 04 06:53:56 PM PDT 24 459227058 ps
T84 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1443026450 Jul 04 06:53:51 PM PDT 24 Jul 04 06:54:02 PM PDT 24 8556288534 ps
T353 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.317110869 Jul 04 06:53:49 PM PDT 24 Jul 04 06:53:57 PM PDT 24 8637664487 ps
T832 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2517134214 Jul 04 06:53:44 PM PDT 24 Jul 04 06:53:46 PM PDT 24 837420120 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1120584304 Jul 04 06:53:52 PM PDT 24 Jul 04 06:53:53 PM PDT 24 294309507 ps
T834 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3855722520 Jul 04 06:53:58 PM PDT 24 Jul 04 06:54:02 PM PDT 24 508669579 ps
T835 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3241929368 Jul 04 06:53:57 PM PDT 24 Jul 04 06:53:58 PM PDT 24 443014912 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2459370010 Jul 04 06:53:50 PM PDT 24 Jul 04 06:53:53 PM PDT 24 471052965 ps
T837 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1911139250 Jul 04 06:53:50 PM PDT 24 Jul 04 06:53:52 PM PDT 24 678115239 ps
T838 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1228650799 Jul 04 06:53:37 PM PDT 24 Jul 04 06:53:38 PM PDT 24 361459352 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4213278897 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:42 PM PDT 24 1669522580 ps
T840 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2648838160 Jul 04 06:53:42 PM PDT 24 Jul 04 06:53:43 PM PDT 24 489565078 ps
T841 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.469042852 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:43 PM PDT 24 4601571941 ps
T842 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3782700034 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:53 PM PDT 24 470597954 ps
T352 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3391791534 Jul 04 06:53:47 PM PDT 24 Jul 04 06:54:08 PM PDT 24 8126305202 ps
T843 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3425340866 Jul 04 06:53:59 PM PDT 24 Jul 04 06:54:16 PM PDT 24 4843110676 ps
T844 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2571386921 Jul 04 06:53:57 PM PDT 24 Jul 04 06:53:59 PM PDT 24 341066109 ps
T845 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3822616415 Jul 04 06:53:52 PM PDT 24 Jul 04 06:53:53 PM PDT 24 910130939 ps
T846 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.935951816 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:32 PM PDT 24 498092985 ps
T847 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1421684525 Jul 04 06:53:56 PM PDT 24 Jul 04 06:54:03 PM PDT 24 7979437124 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1430090754 Jul 04 06:53:23 PM PDT 24 Jul 04 06:53:24 PM PDT 24 368530700 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2493360021 Jul 04 06:53:32 PM PDT 24 Jul 04 06:53:48 PM PDT 24 4600375189 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.168086735 Jul 04 06:53:47 PM PDT 24 Jul 04 06:53:48 PM PDT 24 727762216 ps
T851 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1504457565 Jul 04 06:54:06 PM PDT 24 Jul 04 06:54:07 PM PDT 24 357891877 ps
T852 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2307254221 Jul 04 06:53:45 PM PDT 24 Jul 04 06:53:46 PM PDT 24 552221306 ps
T853 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.895234746 Jul 04 06:54:05 PM PDT 24 Jul 04 06:54:07 PM PDT 24 507494227 ps
T854 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3522919737 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:39 PM PDT 24 332695302 ps
T855 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.776875401 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:32 PM PDT 24 566971727 ps
T856 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.850286877 Jul 04 06:53:59 PM PDT 24 Jul 04 06:54:01 PM PDT 24 325110862 ps
T857 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.815915374 Jul 04 06:54:06 PM PDT 24 Jul 04 06:54:08 PM PDT 24 422787310 ps
T858 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2459955804 Jul 04 06:54:08 PM PDT 24 Jul 04 06:54:09 PM PDT 24 531510975 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2580726505 Jul 04 06:53:30 PM PDT 24 Jul 04 06:54:30 PM PDT 24 49804874441 ps
T859 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3254912535 Jul 04 06:53:37 PM PDT 24 Jul 04 06:53:39 PM PDT 24 441038094 ps
T860 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.865005386 Jul 04 06:54:00 PM PDT 24 Jul 04 06:54:02 PM PDT 24 499966027 ps
T861 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3503106884 Jul 04 06:53:58 PM PDT 24 Jul 04 06:53:59 PM PDT 24 287050325 ps
T862 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1467616989 Jul 04 06:53:57 PM PDT 24 Jul 04 06:53:58 PM PDT 24 563746966 ps
T121 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1209676680 Jul 04 06:53:47 PM PDT 24 Jul 04 06:53:48 PM PDT 24 524755941 ps
T863 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.557048810 Jul 04 06:54:08 PM PDT 24 Jul 04 06:54:09 PM PDT 24 347061617 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3841381707 Jul 04 06:53:56 PM PDT 24 Jul 04 06:53:57 PM PDT 24 538213625 ps
T865 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3152889595 Jul 04 06:53:59 PM PDT 24 Jul 04 06:54:00 PM PDT 24 392957449 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.987160073 Jul 04 06:53:48 PM PDT 24 Jul 04 06:53:49 PM PDT 24 600403025 ps
T867 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3476890589 Jul 04 06:53:37 PM PDT 24 Jul 04 06:53:40 PM PDT 24 370816099 ps
T868 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1935934332 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:40 PM PDT 24 507533870 ps
T869 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1424027634 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:32 PM PDT 24 392308469 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2706724386 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:52 PM PDT 24 356021774 ps
T871 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3055766393 Jul 04 06:53:23 PM PDT 24 Jul 04 06:53:25 PM PDT 24 612406760 ps
T872 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3441376931 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:30 PM PDT 24 492284928 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.390736919 Jul 04 06:53:29 PM PDT 24 Jul 04 06:54:56 PM PDT 24 48551542876 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4134548033 Jul 04 06:53:46 PM PDT 24 Jul 04 06:53:47 PM PDT 24 493822917 ps
T875 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2153752844 Jul 04 06:54:06 PM PDT 24 Jul 04 06:54:07 PM PDT 24 398969934 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3065809472 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:30 PM PDT 24 310619079 ps
T877 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.565411969 Jul 04 06:54:02 PM PDT 24 Jul 04 06:54:04 PM PDT 24 499004306 ps
T878 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2128396878 Jul 04 06:53:57 PM PDT 24 Jul 04 06:53:59 PM PDT 24 299625933 ps
T879 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2948903262 Jul 04 06:53:53 PM PDT 24 Jul 04 06:53:56 PM PDT 24 4599769329 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3809271501 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:32 PM PDT 24 385973961 ps
T881 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.520037240 Jul 04 06:53:52 PM PDT 24 Jul 04 06:53:59 PM PDT 24 7992000984 ps
T85 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1250045454 Jul 04 06:53:59 PM PDT 24 Jul 04 06:54:10 PM PDT 24 4357163908 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.841792509 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:32 PM PDT 24 521027318 ps
T882 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2177276447 Jul 04 06:54:04 PM PDT 24 Jul 04 06:54:05 PM PDT 24 518256014 ps
T883 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2231724586 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:32 PM PDT 24 748558135 ps
T884 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1832222676 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:44 PM PDT 24 642382568 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1675846118 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:46 PM PDT 24 4118970793 ps
T886 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1249146453 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:58 PM PDT 24 2054071950 ps
T887 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.52691887 Jul 04 06:53:40 PM PDT 24 Jul 04 06:53:46 PM PDT 24 2324297260 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3769937463 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:53 PM PDT 24 636621476 ps
T889 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1831766109 Jul 04 06:53:54 PM PDT 24 Jul 04 06:54:01 PM PDT 24 4719888691 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2172249433 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:52 PM PDT 24 8767577968 ps
T891 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4137409181 Jul 04 06:54:00 PM PDT 24 Jul 04 06:54:01 PM PDT 24 447983295 ps
T892 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2936655529 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:40 PM PDT 24 426551531 ps
T893 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.183797283 Jul 04 06:54:00 PM PDT 24 Jul 04 06:54:01 PM PDT 24 384061602 ps
T894 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2103374892 Jul 04 06:53:57 PM PDT 24 Jul 04 06:53:58 PM PDT 24 508251045 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3395523103 Jul 04 06:53:46 PM PDT 24 Jul 04 06:53:49 PM PDT 24 2505359883 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2257785467 Jul 04 06:53:20 PM PDT 24 Jul 04 06:53:21 PM PDT 24 620818222 ps
T897 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.114444813 Jul 04 06:53:58 PM PDT 24 Jul 04 06:54:20 PM PDT 24 4018796316 ps
T898 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2935278964 Jul 04 06:53:36 PM PDT 24 Jul 04 06:53:39 PM PDT 24 462890280 ps
T899 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2207881861 Jul 04 06:53:30 PM PDT 24 Jul 04 06:53:50 PM PDT 24 8117658315 ps
T900 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2298048656 Jul 04 06:53:45 PM PDT 24 Jul 04 06:53:59 PM PDT 24 4857271530 ps
T901 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.257745301 Jul 04 06:53:43 PM PDT 24 Jul 04 06:53:44 PM PDT 24 448314040 ps
T902 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3443850003 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:43 PM PDT 24 3802585650 ps
T903 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2886382390 Jul 04 06:53:32 PM PDT 24 Jul 04 06:53:35 PM PDT 24 1052857433 ps
T123 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1805039901 Jul 04 06:53:57 PM PDT 24 Jul 04 06:53:59 PM PDT 24 517833649 ps
T904 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1942096906 Jul 04 06:53:39 PM PDT 24 Jul 04 06:53:42 PM PDT 24 557251876 ps
T124 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1027060663 Jul 04 06:53:29 PM PDT 24 Jul 04 06:53:31 PM PDT 24 1355039291 ps
T905 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2007102508 Jul 04 06:53:59 PM PDT 24 Jul 04 06:54:00 PM PDT 24 306219863 ps
T906 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3004684478 Jul 04 06:54:00 PM PDT 24 Jul 04 06:54:01 PM PDT 24 339004868 ps
T907 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1873156075 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:42 PM PDT 24 996938791 ps
T908 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3952910724 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:43 PM PDT 24 2402223786 ps
T909 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2449017710 Jul 04 06:53:42 PM PDT 24 Jul 04 06:53:45 PM PDT 24 2833892044 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4217519274 Jul 04 06:53:52 PM PDT 24 Jul 04 06:53:53 PM PDT 24 349797820 ps
T911 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.730056120 Jul 04 06:54:06 PM PDT 24 Jul 04 06:54:07 PM PDT 24 447446446 ps
T912 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1336990947 Jul 04 06:53:51 PM PDT 24 Jul 04 06:53:52 PM PDT 24 403087976 ps
T913 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2177482198 Jul 04 06:53:21 PM PDT 24 Jul 04 06:53:22 PM PDT 24 317226545 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.178393296 Jul 04 06:53:37 PM PDT 24 Jul 04 06:53:49 PM PDT 24 4140446454 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.908001841 Jul 04 06:53:24 PM PDT 24 Jul 04 06:53:26 PM PDT 24 755579052 ps
T916 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.703216996 Jul 04 06:53:45 PM PDT 24 Jul 04 06:53:50 PM PDT 24 472129577 ps
T917 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1906845558 Jul 04 06:53:59 PM PDT 24 Jul 04 06:54:00 PM PDT 24 488935727 ps
T918 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3852001158 Jul 04 06:53:38 PM PDT 24 Jul 04 06:53:41 PM PDT 24 494848136 ps

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.198363634
Short name T6
Test name
Test status
Simulation time 326359226930 ps
CPU time 347.18 seconds
Started Jul 04 07:03:30 PM PDT 24
Finished Jul 04 07:09:17 PM PDT 24
Peak memory 201952 kb
Host smart-d1599835-2372-4970-bee8-6c18967c4f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198363634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.198363634
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3256907070
Short name T54
Test name
Test status
Simulation time 96931917753 ps
CPU time 512.79 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:08:37 PM PDT 24
Peak memory 202196 kb
Host smart-dd52cb0f-5579-4c12-841d-c3b09fbd490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256907070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3256907070
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.570699832
Short name T50
Test name
Test status
Simulation time 351147296493 ps
CPU time 189.03 seconds
Started Jul 04 07:03:59 PM PDT 24
Finished Jul 04 07:07:09 PM PDT 24
Peak memory 201912 kb
Host smart-18492247-a0dd-4079-8ff1-22f52704ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570699832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.570699832
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.703126885
Short name T17
Test name
Test status
Simulation time 301761282017 ps
CPU time 131.85 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:05:58 PM PDT 24
Peak memory 217784 kb
Host smart-f07e0d38-ed58-427b-acd6-a7a601d9b490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703126885 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.703126885
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1221320978
Short name T131
Test name
Test status
Simulation time 613648589243 ps
CPU time 1490.22 seconds
Started Jul 04 07:00:12 PM PDT 24
Finished Jul 04 07:25:03 PM PDT 24
Peak memory 201656 kb
Host smart-b48bf7c0-c8f6-4ce7-b358-64ae9c716d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221320978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1221320978
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1843841786
Short name T335
Test name
Test status
Simulation time 1722064462904 ps
CPU time 1868.91 seconds
Started Jul 04 07:06:11 PM PDT 24
Finished Jul 04 07:37:20 PM PDT 24
Peak memory 202220 kb
Host smart-f77fa89e-9d7f-4786-b4dd-4915ffcfffad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843841786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1843841786
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2432396806
Short name T130
Test name
Test status
Simulation time 620674804127 ps
CPU time 109.24 seconds
Started Jul 04 07:05:27 PM PDT 24
Finished Jul 04 07:07:16 PM PDT 24
Peak memory 201908 kb
Host smart-c647debf-8f13-424b-9f6b-ccf63f31d438
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432396806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2432396806
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.249224961
Short name T138
Test name
Test status
Simulation time 519772768856 ps
CPU time 628.44 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:16:13 PM PDT 24
Peak memory 201912 kb
Host smart-57906091-2db1-4929-895d-e09af71fa7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249224961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.249224961
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3913200637
Short name T142
Test name
Test status
Simulation time 489398223601 ps
CPU time 1028.82 seconds
Started Jul 04 07:02:52 PM PDT 24
Finished Jul 04 07:20:02 PM PDT 24
Peak memory 201916 kb
Host smart-6a44dbdf-e0b6-44af-b90b-4e35f1c2b1f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913200637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3913200637
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1475065654
Short name T19
Test name
Test status
Simulation time 290367513610 ps
CPU time 97.97 seconds
Started Jul 04 07:05:59 PM PDT 24
Finished Jul 04 07:07:37 PM PDT 24
Peak memory 213172 kb
Host smart-2a1fec88-a16c-4e90-b081-256e8c212eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475065654 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1475065654
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.725401760
Short name T75
Test name
Test status
Simulation time 863026828 ps
CPU time 3.44 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:55 PM PDT 24
Peak memory 211012 kb
Host smart-ef1295c9-9d30-4e96-8cab-df08c2155c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725401760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.725401760
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2800705177
Short name T234
Test name
Test status
Simulation time 524831927517 ps
CPU time 1161.5 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:26:17 PM PDT 24
Peak memory 201932 kb
Host smart-0b77835b-6488-4739-8c1b-4c9459c4cbb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800705177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2800705177
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.677335858
Short name T5
Test name
Test status
Simulation time 165790546613 ps
CPU time 378.74 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:09:34 PM PDT 24
Peak memory 201924 kb
Host smart-475be89e-93d8-4074-ac77-c839d9b77f69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=677335858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.677335858
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1011645480
Short name T152
Test name
Test status
Simulation time 555615484545 ps
CPU time 1139.35 seconds
Started Jul 04 07:00:23 PM PDT 24
Finished Jul 04 07:19:22 PM PDT 24
Peak memory 201920 kb
Host smart-8d146c8a-5a52-44c2-83cc-063797b8e05d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011645480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1011645480
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2412940309
Short name T149
Test name
Test status
Simulation time 329405256909 ps
CPU time 305.82 seconds
Started Jul 04 07:01:45 PM PDT 24
Finished Jul 04 07:06:51 PM PDT 24
Peak memory 201924 kb
Host smart-9bb5dd50-5306-48dd-b592-6f84e88e7b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412940309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2412940309
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.554551944
Short name T181
Test name
Test status
Simulation time 305532959 ps
CPU time 0.8 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:00:10 PM PDT 24
Peak memory 201664 kb
Host smart-703da24b-627b-40a2-8686-758295647856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554551944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.554551944
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2804325211
Short name T229
Test name
Test status
Simulation time 34839637003 ps
CPU time 83.37 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:01:42 PM PDT 24
Peak memory 210224 kb
Host smart-25cfe5e1-2e95-4108-8ac6-e0777802aa17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804325211 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2804325211
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3012127476
Short name T63
Test name
Test status
Simulation time 21170224346 ps
CPU time 68.79 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:54:39 PM PDT 24
Peak memory 201796 kb
Host smart-71dcec92-6d0b-448a-a22b-7ee8b950a8e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012127476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3012127476
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3872791342
Short name T86
Test name
Test status
Simulation time 7566084493 ps
CPU time 4.94 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:13 PM PDT 24
Peak memory 218252 kb
Host smart-2fc8d595-55e1-4140-b69e-0af40a9d5a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872791342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3872791342
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1442183638
Short name T162
Test name
Test status
Simulation time 501032183539 ps
CPU time 1117.08 seconds
Started Jul 04 07:07:36 PM PDT 24
Finished Jul 04 07:26:13 PM PDT 24
Peak memory 202008 kb
Host smart-75358d69-fa49-4e8d-a4eb-8c707586fe14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442183638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1442183638
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.774763799
Short name T49
Test name
Test status
Simulation time 103298989145 ps
CPU time 225.49 seconds
Started Jul 04 07:00:37 PM PDT 24
Finished Jul 04 07:04:23 PM PDT 24
Peak memory 217812 kb
Host smart-d071652b-9a28-460b-a0e2-9f2b7fd12eb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774763799 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.774763799
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3975949252
Short name T164
Test name
Test status
Simulation time 550821846823 ps
CPU time 302.96 seconds
Started Jul 04 07:04:01 PM PDT 24
Finished Jul 04 07:09:04 PM PDT 24
Peak memory 201920 kb
Host smart-6c603252-0679-4111-83fb-2cf44c6c0416
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975949252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3975949252
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4008635161
Short name T46
Test name
Test status
Simulation time 101299034041 ps
CPU time 227.78 seconds
Started Jul 04 07:02:02 PM PDT 24
Finished Jul 04 07:05:50 PM PDT 24
Peak memory 210624 kb
Host smart-e6798274-f528-46ef-a048-5cf667798f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008635161 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4008635161
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1633283716
Short name T140
Test name
Test status
Simulation time 482681945156 ps
CPU time 296.7 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:05:43 PM PDT 24
Peak memory 201972 kb
Host smart-68b975e5-e1c0-4e9e-9662-152580176803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633283716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1633283716
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1423567457
Short name T160
Test name
Test status
Simulation time 488796866133 ps
CPU time 1170.57 seconds
Started Jul 04 07:00:47 PM PDT 24
Finished Jul 04 07:20:18 PM PDT 24
Peak memory 201940 kb
Host smart-0612f602-a5e6-437f-9cc1-a22c116093e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423567457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1423567457
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1678142684
Short name T91
Test name
Test status
Simulation time 496336912501 ps
CPU time 152.09 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:03:13 PM PDT 24
Peak memory 201932 kb
Host smart-d9fb922e-b13c-472f-b811-acbea7b49d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678142684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1678142684
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1379164539
Short name T185
Test name
Test status
Simulation time 522755925351 ps
CPU time 77.28 seconds
Started Jul 04 07:07:02 PM PDT 24
Finished Jul 04 07:08:19 PM PDT 24
Peak memory 201928 kb
Host smart-cfaa9c4a-a1f3-4e99-91a0-a73c393d5cf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379164539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1379164539
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2279086264
Short name T172
Test name
Test status
Simulation time 539274816435 ps
CPU time 302.88 seconds
Started Jul 04 07:04:32 PM PDT 24
Finished Jul 04 07:09:36 PM PDT 24
Peak memory 202020 kb
Host smart-0955b104-569a-4f25-99e0-475a251445b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279086264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2279086264
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2278942144
Short name T106
Test name
Test status
Simulation time 169560491116 ps
CPU time 191.66 seconds
Started Jul 04 07:04:20 PM PDT 24
Finished Jul 04 07:07:32 PM PDT 24
Peak memory 201900 kb
Host smart-664cfa5b-0c03-4549-8717-6a4efd3f2e58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278942144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2278942144
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1443026450
Short name T84
Test name
Test status
Simulation time 8556288534 ps
CPU time 10.83 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:54:02 PM PDT 24
Peak memory 201852 kb
Host smart-94f1b83b-9902-476f-81ca-bcbefbd9ed59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443026450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1443026450
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.890023405
Short name T237
Test name
Test status
Simulation time 344708039674 ps
CPU time 290.45 seconds
Started Jul 04 07:03:14 PM PDT 24
Finished Jul 04 07:08:05 PM PDT 24
Peak memory 217960 kb
Host smart-702ab96c-c255-481f-a8c6-1901bbe0f168
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890023405 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.890023405
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1640041450
Short name T51
Test name
Test status
Simulation time 340932923061 ps
CPU time 465.45 seconds
Started Jul 04 07:03:08 PM PDT 24
Finished Jul 04 07:10:54 PM PDT 24
Peak memory 201916 kb
Host smart-19915f3c-f681-4184-b426-376ae0714ae1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640041450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1640041450
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2646078881
Short name T210
Test name
Test status
Simulation time 583334924861 ps
CPU time 1323.04 seconds
Started Jul 04 07:01:43 PM PDT 24
Finished Jul 04 07:23:47 PM PDT 24
Peak memory 201872 kb
Host smart-9e441935-9a14-4b4c-98da-8a3e83ec88d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646078881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2646078881
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.334839852
Short name T13
Test name
Test status
Simulation time 396953366245 ps
CPU time 433.44 seconds
Started Jul 04 07:04:59 PM PDT 24
Finished Jul 04 07:12:13 PM PDT 24
Peak memory 201872 kb
Host smart-698459a5-3e08-40bc-b067-661a7aac2429
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334839852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.334839852
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4218091349
Short name T279
Test name
Test status
Simulation time 514466052143 ps
CPU time 632.51 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:11:04 PM PDT 24
Peak memory 201872 kb
Host smart-8ca8c0b2-f2e3-43ff-8a3d-8e2a6064cb24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218091349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4218091349
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2743568611
Short name T111
Test name
Test status
Simulation time 596935501 ps
CPU time 0.89 seconds
Started Jul 04 06:53:19 PM PDT 24
Finished Jul 04 06:53:20 PM PDT 24
Peak memory 201504 kb
Host smart-51f3a437-b673-43bf-b02f-43e7f97f8686
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743568611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2743568611
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3088782698
Short name T200
Test name
Test status
Simulation time 350287299542 ps
CPU time 189.73 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:03:19 PM PDT 24
Peak memory 201916 kb
Host smart-6d634ac5-3543-46b9-9e92-cbdbd4db86f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088782698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3088782698
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2990125302
Short name T92
Test name
Test status
Simulation time 491318822716 ps
CPU time 287.36 seconds
Started Jul 04 07:02:05 PM PDT 24
Finished Jul 04 07:06:52 PM PDT 24
Peak memory 201888 kb
Host smart-1ce16a89-860e-405f-aa3a-fca9ab5d078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990125302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2990125302
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.264589909
Short name T135
Test name
Test status
Simulation time 330680174205 ps
CPU time 400.25 seconds
Started Jul 04 07:02:23 PM PDT 24
Finished Jul 04 07:09:03 PM PDT 24
Peak memory 201948 kb
Host smart-84e6eecf-a834-4177-89ff-b1d9695d2e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264589909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
264589909
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2592483685
Short name T207
Test name
Test status
Simulation time 488909067479 ps
CPU time 221.69 seconds
Started Jul 04 07:00:12 PM PDT 24
Finished Jul 04 07:03:54 PM PDT 24
Peak memory 201932 kb
Host smart-d9be459e-1fb9-4ca6-8fdf-311c3f36391c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592483685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2592483685
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3478617351
Short name T150
Test name
Test status
Simulation time 578234132494 ps
CPU time 335.96 seconds
Started Jul 04 07:05:14 PM PDT 24
Finished Jul 04 07:10:50 PM PDT 24
Peak memory 201980 kb
Host smart-2b2a1458-8a09-4bc0-a05b-dc31789d2e92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478617351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3478617351
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.4026099252
Short name T260
Test name
Test status
Simulation time 325104310374 ps
CPU time 750.28 seconds
Started Jul 04 07:02:22 PM PDT 24
Finished Jul 04 07:14:52 PM PDT 24
Peak memory 201912 kb
Host smart-91a0df19-9c5f-4620-b6a2-6264014b00bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026099252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.4026099252
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2737540156
Short name T231
Test name
Test status
Simulation time 406631737948 ps
CPU time 951.06 seconds
Started Jul 04 07:02:37 PM PDT 24
Finished Jul 04 07:18:28 PM PDT 24
Peak memory 201932 kb
Host smart-cbe3bc5f-1f86-46d3-b7e5-030fe55228a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737540156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2737540156
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1660889058
Short name T307
Test name
Test status
Simulation time 232654989297 ps
CPU time 258.22 seconds
Started Jul 04 07:03:21 PM PDT 24
Finished Jul 04 07:07:40 PM PDT 24
Peak memory 201884 kb
Host smart-aec6eae0-4b2a-43cb-bd6e-124ee31e8ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660889058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1660889058
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1235537237
Short name T327
Test name
Test status
Simulation time 329869771665 ps
CPU time 192.62 seconds
Started Jul 04 07:02:25 PM PDT 24
Finished Jul 04 07:05:38 PM PDT 24
Peak memory 201976 kb
Host smart-77711e8c-6989-4213-9802-9c88ebd1fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235537237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1235537237
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.532862720
Short name T57
Test name
Test status
Simulation time 309194813704 ps
CPU time 744.29 seconds
Started Jul 04 07:06:19 PM PDT 24
Finished Jul 04 07:18:43 PM PDT 24
Peak memory 218560 kb
Host smart-98207cbf-4297-436f-b803-abb895b791b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532862720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
532862720
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4111980188
Short name T305
Test name
Test status
Simulation time 525086424145 ps
CPU time 253.13 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:04:32 PM PDT 24
Peak memory 201920 kb
Host smart-19182d3f-99df-499a-a268-aafcf3238089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111980188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4111980188
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2817397082
Short name T283
Test name
Test status
Simulation time 562119833267 ps
CPU time 319.79 seconds
Started Jul 04 07:06:26 PM PDT 24
Finished Jul 04 07:11:47 PM PDT 24
Peak memory 201924 kb
Host smart-d24c9089-530f-491a-a1e7-eaec26381ba0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817397082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2817397082
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3939905634
Short name T294
Test name
Test status
Simulation time 346032319773 ps
CPU time 637.33 seconds
Started Jul 04 07:07:00 PM PDT 24
Finished Jul 04 07:17:38 PM PDT 24
Peak memory 201888 kb
Host smart-7da12dd6-5b2c-422f-8a5c-375527dbf46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939905634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3939905634
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3530690445
Short name T319
Test name
Test status
Simulation time 184276638571 ps
CPU time 219 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:04:20 PM PDT 24
Peak memory 202008 kb
Host smart-06299c36-d330-4c2d-ad95-a1c3f855cf86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530690445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3530690445
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3827937243
Short name T292
Test name
Test status
Simulation time 140369725080 ps
CPU time 410.84 seconds
Started Jul 04 07:01:18 PM PDT 24
Finished Jul 04 07:08:09 PM PDT 24
Peak memory 210588 kb
Host smart-d0ddae8d-1273-4006-b394-19f827a4a4cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827937243 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3827937243
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.206780659
Short name T171
Test name
Test status
Simulation time 272914957030 ps
CPU time 160.64 seconds
Started Jul 04 07:04:27 PM PDT 24
Finished Jul 04 07:07:07 PM PDT 24
Peak memory 201932 kb
Host smart-c1facf58-7f9c-4cae-befd-2950f3ef9859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206780659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.206780659
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3106332180
Short name T281
Test name
Test status
Simulation time 365490574505 ps
CPU time 139.12 seconds
Started Jul 04 07:04:28 PM PDT 24
Finished Jul 04 07:06:48 PM PDT 24
Peak memory 201928 kb
Host smart-e9c961f8-0092-4e09-9227-9e26c1357634
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106332180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3106332180
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3632632004
Short name T297
Test name
Test status
Simulation time 375127149021 ps
CPU time 827.67 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:14:27 PM PDT 24
Peak memory 201892 kb
Host smart-1e9e1962-6a94-48f5-a700-a5922ea0426b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632632004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3632632004
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3775211058
Short name T251
Test name
Test status
Simulation time 588194324433 ps
CPU time 723.02 seconds
Started Jul 04 07:02:18 PM PDT 24
Finished Jul 04 07:14:21 PM PDT 24
Peak memory 201916 kb
Host smart-15c08fbf-6265-4492-83af-f6cb3283f2e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775211058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3775211058
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2588636551
Short name T325
Test name
Test status
Simulation time 163271607358 ps
CPU time 188.96 seconds
Started Jul 04 07:03:53 PM PDT 24
Finished Jul 04 07:07:02 PM PDT 24
Peak memory 201908 kb
Host smart-8f6c7637-8aec-47db-b8ff-68f33c460ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588636551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2588636551
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2018369884
Short name T293
Test name
Test status
Simulation time 293239943143 ps
CPU time 37.29 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:00:46 PM PDT 24
Peak memory 202068 kb
Host smart-efeb41e6-a264-4b83-8a89-be9e4f5d6d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018369884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2018369884
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3248294157
Short name T107
Test name
Test status
Simulation time 512191260839 ps
CPU time 335.48 seconds
Started Jul 04 07:05:22 PM PDT 24
Finished Jul 04 07:10:58 PM PDT 24
Peak memory 201956 kb
Host smart-02cac128-7d09-452a-87af-f3361759dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248294157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3248294157
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1933454746
Short name T306
Test name
Test status
Simulation time 345171062134 ps
CPU time 210.64 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:09:15 PM PDT 24
Peak memory 201976 kb
Host smart-312fbb81-a92f-4a63-8c0b-b4a4040c561e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933454746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1933454746
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.519682811
Short name T339
Test name
Test status
Simulation time 172796511719 ps
CPU time 60.15 seconds
Started Jul 04 07:07:40 PM PDT 24
Finished Jul 04 07:08:40 PM PDT 24
Peak memory 201908 kb
Host smart-242cef86-11bb-454a-901f-af11086f2101
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519682811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.519682811
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1599961307
Short name T269
Test name
Test status
Simulation time 549175275400 ps
CPU time 439.19 seconds
Started Jul 04 07:01:01 PM PDT 24
Finished Jul 04 07:08:20 PM PDT 24
Peak memory 201924 kb
Host smart-e4f9ed47-54ac-4849-a073-6c0ee9e591bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599961307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1599961307
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2577133929
Short name T267
Test name
Test status
Simulation time 45883635919 ps
CPU time 51.98 seconds
Started Jul 04 07:01:26 PM PDT 24
Finished Jul 04 07:02:18 PM PDT 24
Peak memory 210240 kb
Host smart-df60ab85-31a1-403c-ba79-de60d45a69aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577133929 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2577133929
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2087138394
Short name T356
Test name
Test status
Simulation time 126179389226 ps
CPU time 638.33 seconds
Started Jul 04 07:01:50 PM PDT 24
Finished Jul 04 07:12:28 PM PDT 24
Peak memory 202224 kb
Host smart-6e9db7e9-f54b-4151-a439-c40982c0f557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087138394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2087138394
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3245583872
Short name T685
Test name
Test status
Simulation time 77210542898 ps
CPU time 437.63 seconds
Started Jul 04 07:02:04 PM PDT 24
Finished Jul 04 07:09:22 PM PDT 24
Peak memory 202260 kb
Host smart-bb0bf725-7431-4daf-ba06-f2e0c0de7f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245583872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3245583872
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.995438012
Short name T225
Test name
Test status
Simulation time 138269391637 ps
CPU time 423.92 seconds
Started Jul 04 07:02:24 PM PDT 24
Finished Jul 04 07:09:28 PM PDT 24
Peak memory 202288 kb
Host smart-15f757e8-6005-42b9-adc1-b28096c5f433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995438012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.995438012
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2185344773
Short name T244
Test name
Test status
Simulation time 501311796029 ps
CPU time 281.67 seconds
Started Jul 04 07:02:53 PM PDT 24
Finished Jul 04 07:07:35 PM PDT 24
Peak memory 201864 kb
Host smart-343d5fa8-0348-4bf3-b224-6162e8929ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185344773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2185344773
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1710478866
Short name T144
Test name
Test status
Simulation time 334773562993 ps
CPU time 292.97 seconds
Started Jul 04 07:07:26 PM PDT 24
Finished Jul 04 07:12:19 PM PDT 24
Peak memory 201900 kb
Host smart-2e83012d-b4f9-4d2f-82f3-1ffbfe883253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710478866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1710478866
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2614488913
Short name T139
Test name
Test status
Simulation time 358465713756 ps
CPU time 159.07 seconds
Started Jul 04 07:00:26 PM PDT 24
Finished Jul 04 07:03:05 PM PDT 24
Peak memory 201900 kb
Host smart-24424f84-8b22-4bd6-828c-311e8f06d4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614488913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2614488913
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.520037240
Short name T881
Test name
Test status
Simulation time 7992000984 ps
CPU time 6.59 seconds
Started Jul 04 06:53:52 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201812 kb
Host smart-a37b7491-1bf7-4224-8f09-76c752765768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520037240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.520037240
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.398637534
Short name T332
Test name
Test status
Simulation time 350209035211 ps
CPU time 787.8 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:13:12 PM PDT 24
Peak memory 201872 kb
Host smart-3b2e22b2-ac64-4764-aa59-5576209f9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398637534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.398637534
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2454940616
Short name T322
Test name
Test status
Simulation time 146036360048 ps
CPU time 153.43 seconds
Started Jul 04 07:00:12 PM PDT 24
Finished Jul 04 07:02:45 PM PDT 24
Peak memory 210244 kb
Host smart-c9dcecf4-0177-428d-bd0f-d8b6adfabe06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454940616 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2454940616
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2354324348
Short name T301
Test name
Test status
Simulation time 323579134687 ps
CPU time 354.31 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:06:28 PM PDT 24
Peak memory 201928 kb
Host smart-6b3500d6-83f7-4307-b060-dd2176e6a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354324348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2354324348
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.852139244
Short name T12
Test name
Test status
Simulation time 487468864283 ps
CPU time 430.33 seconds
Started Jul 04 07:00:32 PM PDT 24
Finished Jul 04 07:07:43 PM PDT 24
Peak memory 201988 kb
Host smart-e12a62a5-b0d1-449d-80dc-aafe67434cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852139244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.852139244
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1800321457
Short name T205
Test name
Test status
Simulation time 271066718082 ps
CPU time 548.37 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:09:49 PM PDT 24
Peak memory 202232 kb
Host smart-7eca02cf-1bce-4a69-b84a-2ae92298e685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800321457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1800321457
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2302047387
Short name T35
Test name
Test status
Simulation time 110224172933 ps
CPU time 602.27 seconds
Started Jul 04 07:00:48 PM PDT 24
Finished Jul 04 07:10:50 PM PDT 24
Peak memory 202208 kb
Host smart-c4a9f047-7061-4c72-a29f-bce2c3c85b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302047387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2302047387
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2875992007
Short name T220
Test name
Test status
Simulation time 109637434446 ps
CPU time 451.75 seconds
Started Jul 04 07:02:45 PM PDT 24
Finished Jul 04 07:10:17 PM PDT 24
Peak memory 202276 kb
Host smart-cf5cd3e6-1a5e-406b-9c66-7768196c79ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875992007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2875992007
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4028784421
Short name T242
Test name
Test status
Simulation time 437620258577 ps
CPU time 472.99 seconds
Started Jul 04 07:04:48 PM PDT 24
Finished Jul 04 07:12:41 PM PDT 24
Peak memory 202216 kb
Host smart-00c87d25-2706-436c-be64-01431b6f790a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028784421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4028784421
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.4263985994
Short name T173
Test name
Test status
Simulation time 360658962786 ps
CPU time 506.28 seconds
Started Jul 04 07:05:21 PM PDT 24
Finished Jul 04 07:13:47 PM PDT 24
Peak memory 211632 kb
Host smart-f101e569-a401-44ba-a8dd-2b8a9721bc38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263985994 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.4263985994
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3333006160
Short name T300
Test name
Test status
Simulation time 157591711204 ps
CPU time 369.24 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:13:04 PM PDT 24
Peak memory 201896 kb
Host smart-86e05d34-3ca3-4079-8c19-aea85ae8681a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333006160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3333006160
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.549850835
Short name T224
Test name
Test status
Simulation time 81873722944 ps
CPU time 285.42 seconds
Started Jul 04 07:07:32 PM PDT 24
Finished Jul 04 07:12:17 PM PDT 24
Peak memory 202208 kb
Host smart-6ec89761-baf9-4be1-b309-cc09f655d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549850835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.549850835
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.290366947
Short name T113
Test name
Test status
Simulation time 596652338 ps
CPU time 2.17 seconds
Started Jul 04 06:53:23 PM PDT 24
Finished Jul 04 06:53:25 PM PDT 24
Peak memory 201684 kb
Host smart-2b65c494-88ca-4d19-9742-29ccb3872903
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290366947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.290366947
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3157415146
Short name T129
Test name
Test status
Simulation time 26192158666 ps
CPU time 103.1 seconds
Started Jul 04 06:53:22 PM PDT 24
Finished Jul 04 06:55:05 PM PDT 24
Peak memory 201812 kb
Host smart-db165aa5-fa2f-4a19-b6cf-f52d0b3e017f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157415146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3157415146
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2257785467
Short name T896
Test name
Test status
Simulation time 620818222 ps
CPU time 0.87 seconds
Started Jul 04 06:53:20 PM PDT 24
Finished Jul 04 06:53:21 PM PDT 24
Peak memory 201504 kb
Host smart-7c9a16da-bd11-4b61-9a82-64059d12036f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257785467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2257785467
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1430090754
Short name T848
Test name
Test status
Simulation time 368530700 ps
CPU time 1.02 seconds
Started Jul 04 06:53:23 PM PDT 24
Finished Jul 04 06:53:24 PM PDT 24
Peak memory 201596 kb
Host smart-898fca48-1e11-4bb2-bc6f-24ea062d7558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430090754 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1430090754
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2177482198
Short name T913
Test name
Test status
Simulation time 317226545 ps
CPU time 0.82 seconds
Started Jul 04 06:53:21 PM PDT 24
Finished Jul 04 06:53:22 PM PDT 24
Peak memory 201360 kb
Host smart-326d408b-58bd-4828-982d-ad17b8d27828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177482198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2177482198
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.114968548
Short name T813
Test name
Test status
Simulation time 4282731375 ps
CPU time 4.51 seconds
Started Jul 04 06:53:23 PM PDT 24
Finished Jul 04 06:53:27 PM PDT 24
Peak memory 201832 kb
Host smart-f4ed6fd4-663f-4e6c-8a41-e7933b12bacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114968548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.114968548
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3055766393
Short name T871
Test name
Test status
Simulation time 612406760 ps
CPU time 1.8 seconds
Started Jul 04 06:53:23 PM PDT 24
Finished Jul 04 06:53:25 PM PDT 24
Peak memory 201816 kb
Host smart-ab0d17c3-ef0b-4915-88b5-24c7ee3e4ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055766393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3055766393
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2234754458
Short name T815
Test name
Test status
Simulation time 4540346687 ps
CPU time 4.59 seconds
Started Jul 04 06:53:24 PM PDT 24
Finished Jul 04 06:53:29 PM PDT 24
Peak memory 201864 kb
Host smart-f38b8211-2d8b-4140-9366-b54f7362f224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234754458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2234754458
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1614401909
Short name T112
Test name
Test status
Simulation time 1231752573 ps
CPU time 3.06 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:33 PM PDT 24
Peak memory 201692 kb
Host smart-a9167bd4-91fb-40c3-9167-4fecb6f3b35b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614401909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1614401909
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.390736919
Short name T873
Test name
Test status
Simulation time 48551542876 ps
CPU time 86.83 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:54:56 PM PDT 24
Peak memory 201804 kb
Host smart-c359c7b2-624e-413b-9e57-2a35f1e3c1ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390736919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.390736919
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2231724586
Short name T883
Test name
Test status
Simulation time 748558135 ps
CPU time 2.59 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201504 kb
Host smart-1173641f-9037-483e-ae3a-3e8b87ed15d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231724586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2231724586
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.508659716
Short name T80
Test name
Test status
Simulation time 612821487 ps
CPU time 1.6 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:31 PM PDT 24
Peak memory 201580 kb
Host smart-bb360d34-3a4d-4f64-ab8c-635c2ccfe2d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508659716 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.508659716
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1424027634
Short name T869
Test name
Test status
Simulation time 392308469 ps
CPU time 1.12 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201524 kb
Host smart-2675245e-de10-4b9b-a986-3af571afdaf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424027634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1424027634
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3809271501
Short name T880
Test name
Test status
Simulation time 385973961 ps
CPU time 1.08 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201460 kb
Host smart-eb45708e-7501-4eae-aa84-e4842ffa9381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809271501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3809271501
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1950663998
Short name T125
Test name
Test status
Simulation time 3896678713 ps
CPU time 9.47 seconds
Started Jul 04 06:53:31 PM PDT 24
Finished Jul 04 06:53:41 PM PDT 24
Peak memory 201844 kb
Host smart-2b232c89-fb61-484e-8414-7c52b87c43c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950663998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1950663998
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.908001841
Short name T915
Test name
Test status
Simulation time 755579052 ps
CPU time 1.84 seconds
Started Jul 04 06:53:24 PM PDT 24
Finished Jul 04 06:53:26 PM PDT 24
Peak memory 201812 kb
Host smart-87126b3b-4ec5-4e2f-9840-7ad747f2eb11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908001841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.908001841
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2207881861
Short name T899
Test name
Test status
Simulation time 8117658315 ps
CPU time 19.58 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:50 PM PDT 24
Peak memory 201828 kb
Host smart-7505a320-0451-49fc-a8e5-c49a3870e5c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207881861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2207881861
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1033096375
Short name T108
Test name
Test status
Simulation time 541149340 ps
CPU time 2.08 seconds
Started Jul 04 06:53:44 PM PDT 24
Finished Jul 04 06:53:46 PM PDT 24
Peak memory 201540 kb
Host smart-e34f1bcc-39e2-45b5-ab86-65b19a241167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033096375 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1033096375
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1120584304
Short name T833
Test name
Test status
Simulation time 294309507 ps
CPU time 1.39 seconds
Started Jul 04 06:53:52 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 201460 kb
Host smart-f9b0f142-90da-48b9-b40f-e444a227e5f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120584304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1120584304
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4134548033
Short name T874
Test name
Test status
Simulation time 493822917 ps
CPU time 1.24 seconds
Started Jul 04 06:53:46 PM PDT 24
Finished Jul 04 06:53:47 PM PDT 24
Peak memory 201468 kb
Host smart-2d9837fb-c691-4ec8-9012-6ccb2dfe6be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134548033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4134548033
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3699734230
Short name T62
Test name
Test status
Simulation time 2698000210 ps
CPU time 7.04 seconds
Started Jul 04 06:53:48 PM PDT 24
Finished Jul 04 06:53:55 PM PDT 24
Peak memory 201544 kb
Host smart-efdebb7c-0b48-4bea-924e-6c75c6fab7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699734230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3699734230
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.190720867
Short name T77
Test name
Test status
Simulation time 921803662 ps
CPU time 2.93 seconds
Started Jul 04 06:53:44 PM PDT 24
Finished Jul 04 06:53:47 PM PDT 24
Peak memory 210972 kb
Host smart-d0708e30-8e70-4eec-b756-c1f9a937bfce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190720867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.190720867
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3822616415
Short name T845
Test name
Test status
Simulation time 910130939 ps
CPU time 1.45 seconds
Started Jul 04 06:53:52 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 209960 kb
Host smart-3d496b1a-2b78-45ff-ad55-7cb01302edef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822616415 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3822616415
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1819871765
Short name T825
Test name
Test status
Simulation time 444733746 ps
CPU time 1.91 seconds
Started Jul 04 06:53:47 PM PDT 24
Finished Jul 04 06:53:49 PM PDT 24
Peak memory 201528 kb
Host smart-f824c969-74be-42a1-9dd3-d20775a557a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819871765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1819871765
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3782700034
Short name T842
Test name
Test status
Simulation time 470597954 ps
CPU time 1 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 201412 kb
Host smart-8cda97a2-be12-4732-90c6-e9045176bf79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782700034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3782700034
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3699402014
Short name T61
Test name
Test status
Simulation time 2146697624 ps
CPU time 7.09 seconds
Started Jul 04 06:53:44 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201516 kb
Host smart-ad93d2bb-032e-4a81-bc4b-32aecb7817ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699402014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3699402014
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2517134214
Short name T832
Test name
Test status
Simulation time 837420120 ps
CPU time 2.17 seconds
Started Jul 04 06:53:44 PM PDT 24
Finished Jul 04 06:53:46 PM PDT 24
Peak memory 211020 kb
Host smart-dd8bbe8d-b81a-4fc1-978b-d039dd39f89f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517134214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2517134214
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3391791534
Short name T352
Test name
Test status
Simulation time 8126305202 ps
CPU time 21.13 seconds
Started Jul 04 06:53:47 PM PDT 24
Finished Jul 04 06:54:08 PM PDT 24
Peak memory 201856 kb
Host smart-9018e93e-8130-4d21-96f4-4ddd9f80d5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391791534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3391791534
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1152788586
Short name T83
Test name
Test status
Simulation time 419696335 ps
CPU time 1.22 seconds
Started Jul 04 06:53:48 PM PDT 24
Finished Jul 04 06:53:49 PM PDT 24
Peak memory 201504 kb
Host smart-5e42575d-1ca9-4c88-a86f-cf8aa276c93c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152788586 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1152788586
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.987160073
Short name T866
Test name
Test status
Simulation time 600403025 ps
CPU time 0.82 seconds
Started Jul 04 06:53:48 PM PDT 24
Finished Jul 04 06:53:49 PM PDT 24
Peak memory 201508 kb
Host smart-a6aa626c-222b-44b6-b2b2-2ab14909af16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987160073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.987160073
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1141732941
Short name T805
Test name
Test status
Simulation time 556021886 ps
CPU time 0.91 seconds
Started Jul 04 06:53:46 PM PDT 24
Finished Jul 04 06:53:47 PM PDT 24
Peak memory 201456 kb
Host smart-00dfbf6f-b351-4c87-922a-f5fedefa7977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141732941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1141732941
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3395523103
Short name T895
Test name
Test status
Simulation time 2505359883 ps
CPU time 3.39 seconds
Started Jul 04 06:53:46 PM PDT 24
Finished Jul 04 06:53:49 PM PDT 24
Peak memory 201620 kb
Host smart-9461e945-be54-4c3d-b362-34758814dae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395523103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3395523103
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.703216996
Short name T916
Test name
Test status
Simulation time 472129577 ps
CPU time 4.06 seconds
Started Jul 04 06:53:45 PM PDT 24
Finished Jul 04 06:53:50 PM PDT 24
Peak memory 210952 kb
Host smart-a6ff23b5-8798-44d9-a887-d6d94529930a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703216996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.703216996
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.317110869
Short name T353
Test name
Test status
Simulation time 8637664487 ps
CPU time 8.25 seconds
Started Jul 04 06:53:49 PM PDT 24
Finished Jul 04 06:53:57 PM PDT 24
Peak memory 201892 kb
Host smart-b43d1edf-2335-45f3-ade5-bdaa5b8b8fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317110869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.317110869
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2793291037
Short name T98
Test name
Test status
Simulation time 595115675 ps
CPU time 1.4 seconds
Started Jul 04 06:53:43 PM PDT 24
Finished Jul 04 06:53:45 PM PDT 24
Peak memory 210012 kb
Host smart-442dfb11-6f27-41a4-8f16-01e086b07abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793291037 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2793291037
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3950658588
Short name T127
Test name
Test status
Simulation time 552846954 ps
CPU time 1 seconds
Started Jul 04 06:53:45 PM PDT 24
Finished Jul 04 06:53:46 PM PDT 24
Peak memory 201500 kb
Host smart-21fa325e-c5b4-4cff-8c76-23de74665287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950658588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3950658588
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4217519274
Short name T910
Test name
Test status
Simulation time 349797820 ps
CPU time 0.83 seconds
Started Jul 04 06:53:52 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 201416 kb
Host smart-4da58448-fc17-475c-bdbb-73b682c51a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217519274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4217519274
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3609814674
Short name T824
Test name
Test status
Simulation time 2104134790 ps
CPU time 5.46 seconds
Started Jul 04 06:53:46 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201552 kb
Host smart-7c371a93-5401-42d9-89fe-64d96d9ee088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609814674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3609814674
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1086115059
Short name T76
Test name
Test status
Simulation time 515195829 ps
CPU time 2.97 seconds
Started Jul 04 06:53:52 PM PDT 24
Finished Jul 04 06:53:56 PM PDT 24
Peak memory 201756 kb
Host smart-59b35fc5-b32f-402b-8dc8-0a6c224114ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086115059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1086115059
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2255073538
Short name T64
Test name
Test status
Simulation time 3987908215 ps
CPU time 3.03 seconds
Started Jul 04 06:53:46 PM PDT 24
Finished Jul 04 06:53:49 PM PDT 24
Peak memory 201864 kb
Host smart-7e6000c0-df99-41cf-a1df-a69613126554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255073538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2255073538
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3459106404
Short name T808
Test name
Test status
Simulation time 468349827 ps
CPU time 1.89 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 201592 kb
Host smart-5eee59e4-b864-46bd-8605-ee844d4694e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459106404 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3459106404
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1209676680
Short name T121
Test name
Test status
Simulation time 524755941 ps
CPU time 1.05 seconds
Started Jul 04 06:53:47 PM PDT 24
Finished Jul 04 06:53:48 PM PDT 24
Peak memory 201508 kb
Host smart-7e3cdb1a-bddf-4a4c-bb6a-df3d9b6a6ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209676680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1209676680
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2307254221
Short name T852
Test name
Test status
Simulation time 552221306 ps
CPU time 0.92 seconds
Started Jul 04 06:53:45 PM PDT 24
Finished Jul 04 06:53:46 PM PDT 24
Peak memory 201456 kb
Host smart-7ae04176-cbc1-449e-9b43-8b1990f66294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307254221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2307254221
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3944357109
Short name T128
Test name
Test status
Simulation time 2160167555 ps
CPU time 3.4 seconds
Started Jul 04 06:53:55 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201652 kb
Host smart-03b89e1e-22c6-4e4c-b48c-dc1a59dbb939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944357109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3944357109
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.168086735
Short name T850
Test name
Test status
Simulation time 727762216 ps
CPU time 1.76 seconds
Started Jul 04 06:53:47 PM PDT 24
Finished Jul 04 06:53:48 PM PDT 24
Peak memory 201772 kb
Host smart-851d1a42-57ac-458f-8cdc-200448d8fb87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168086735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.168086735
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2298048656
Short name T900
Test name
Test status
Simulation time 4857271530 ps
CPU time 13.28 seconds
Started Jul 04 06:53:45 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201828 kb
Host smart-59ba0b0f-9fbe-4b68-a5c9-ce7ece5d3ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298048656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2298048656
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1911139250
Short name T837
Test name
Test status
Simulation time 678115239 ps
CPU time 1.33 seconds
Started Jul 04 06:53:50 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201544 kb
Host smart-210c0931-65e9-47c2-9e57-0ecd16ba97dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911139250 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1911139250
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1805039901
Short name T123
Test name
Test status
Simulation time 517833649 ps
CPU time 1.99 seconds
Started Jul 04 06:53:57 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201500 kb
Host smart-416cd6e6-522a-4d17-8e57-a0bba1220dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805039901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1805039901
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1899650127
Short name T820
Test name
Test status
Simulation time 301765703 ps
CPU time 0.99 seconds
Started Jul 04 06:53:53 PM PDT 24
Finished Jul 04 06:53:54 PM PDT 24
Peak memory 201432 kb
Host smart-e7193e26-ad0c-4842-a5a2-1e4cbfb80bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899650127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1899650127
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1249146453
Short name T886
Test name
Test status
Simulation time 2054071950 ps
CPU time 6.93 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:58 PM PDT 24
Peak memory 201536 kb
Host smart-87e3d62f-72d9-46d1-9384-0a6a345f762c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249146453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1249146453
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2459370010
Short name T836
Test name
Test status
Simulation time 471052965 ps
CPU time 3.14 seconds
Started Jul 04 06:53:50 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 210996 kb
Host smart-d6da2945-6f38-4737-9717-654b2c61aa24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459370010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2459370010
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3937086453
Short name T69
Test name
Test status
Simulation time 4850953888 ps
CPU time 2.3 seconds
Started Jul 04 06:53:52 PM PDT 24
Finished Jul 04 06:53:54 PM PDT 24
Peak memory 201792 kb
Host smart-c238cfce-bb9b-42d1-897c-e78c0f8b503d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937086453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3937086453
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2767634349
Short name T803
Test name
Test status
Simulation time 508556747 ps
CPU time 1.44 seconds
Started Jul 04 06:53:50 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201572 kb
Host smart-ce7fbe73-79d1-4fd4-aa68-42882a87fa1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767634349 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2767634349
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3053542444
Short name T831
Test name
Test status
Simulation time 459227058 ps
CPU time 0.87 seconds
Started Jul 04 06:53:55 PM PDT 24
Finished Jul 04 06:53:56 PM PDT 24
Peak memory 201500 kb
Host smart-38522b37-973a-4613-bd8e-592d4344dd60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053542444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3053542444
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1060562092
Short name T798
Test name
Test status
Simulation time 371046436 ps
CPU time 1.43 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201456 kb
Host smart-18274b4f-cbfb-4510-b2b8-02bba63d7c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060562092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1060562092
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1776628176
Short name T809
Test name
Test status
Simulation time 4394009326 ps
CPU time 6.4 seconds
Started Jul 04 06:53:49 PM PDT 24
Finished Jul 04 06:53:56 PM PDT 24
Peak memory 201908 kb
Host smart-1dad7bc1-9e5c-49ec-8e9d-cbff143ce26d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776628176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1776628176
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3769937463
Short name T888
Test name
Test status
Simulation time 636621476 ps
CPU time 2.48 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:53 PM PDT 24
Peak memory 201760 kb
Host smart-89590208-fade-430f-ba2e-30970ad5902e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769937463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3769937463
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1831766109
Short name T889
Test name
Test status
Simulation time 4719888691 ps
CPU time 6.61 seconds
Started Jul 04 06:53:54 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201836 kb
Host smart-57af0065-34f8-49c8-b725-2de10c46587d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831766109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1831766109
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4175182247
Short name T829
Test name
Test status
Simulation time 525613728 ps
CPU time 1.25 seconds
Started Jul 04 06:53:54 PM PDT 24
Finished Jul 04 06:53:55 PM PDT 24
Peak memory 201560 kb
Host smart-ece2b6c8-1f9d-47a8-b964-6c06f6574dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175182247 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4175182247
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3604900449
Short name T818
Test name
Test status
Simulation time 451887367 ps
CPU time 1.05 seconds
Started Jul 04 06:53:54 PM PDT 24
Finished Jul 04 06:53:55 PM PDT 24
Peak memory 201476 kb
Host smart-a957cb30-3569-441a-bec7-529a1f68c172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604900449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3604900449
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2706724386
Short name T870
Test name
Test status
Simulation time 356021774 ps
CPU time 0.81 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201408 kb
Host smart-52f8199d-31c9-4046-bd97-96b316cd58ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706724386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2706724386
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2948903262
Short name T879
Test name
Test status
Simulation time 4599769329 ps
CPU time 2.17 seconds
Started Jul 04 06:53:53 PM PDT 24
Finished Jul 04 06:53:56 PM PDT 24
Peak memory 201868 kb
Host smart-84930f40-384e-4e40-a51b-95da607b9912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948903262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2948903262
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1215794697
Short name T811
Test name
Test status
Simulation time 451630940 ps
CPU time 2.71 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:54 PM PDT 24
Peak memory 201744 kb
Host smart-3e300bed-3edf-4b1c-95e5-3bd1e6853ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215794697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1215794697
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1421684525
Short name T847
Test name
Test status
Simulation time 7979437124 ps
CPU time 6.58 seconds
Started Jul 04 06:53:56 PM PDT 24
Finished Jul 04 06:54:03 PM PDT 24
Peak memory 201856 kb
Host smart-5619e33f-3e8b-4c97-98b1-e3647aaadeeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421684525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1421684525
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1467616989
Short name T862
Test name
Test status
Simulation time 563746966 ps
CPU time 0.96 seconds
Started Jul 04 06:53:57 PM PDT 24
Finished Jul 04 06:53:58 PM PDT 24
Peak memory 201588 kb
Host smart-700670c9-8b9c-4bc2-abc3-9790dce63420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467616989 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1467616989
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4090320571
Short name T116
Test name
Test status
Simulation time 529675636 ps
CPU time 1.13 seconds
Started Jul 04 06:53:55 PM PDT 24
Finished Jul 04 06:53:57 PM PDT 24
Peak memory 201500 kb
Host smart-8ab723d4-f4df-496c-b938-87ab22f75cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090320571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4090320571
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1336990947
Short name T912
Test name
Test status
Simulation time 403087976 ps
CPU time 0.89 seconds
Started Jul 04 06:53:51 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201412 kb
Host smart-05a4f921-0f2d-445a-ab19-9aa290e606d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336990947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1336990947
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.114444813
Short name T897
Test name
Test status
Simulation time 4018796316 ps
CPU time 21.13 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:54:20 PM PDT 24
Peak memory 201832 kb
Host smart-af7bdaa9-660f-4684-a9cb-64b7e83364c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114444813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.114444813
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3841381707
Short name T864
Test name
Test status
Simulation time 538213625 ps
CPU time 1.51 seconds
Started Jul 04 06:53:56 PM PDT 24
Finished Jul 04 06:53:57 PM PDT 24
Peak memory 201568 kb
Host smart-f2ca6c83-2379-4478-9b0f-a132f99687ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841381707 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3841381707
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2077228427
Short name T807
Test name
Test status
Simulation time 639429296 ps
CPU time 0.87 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201512 kb
Host smart-61c8c6f0-fc5c-4eea-8b46-706ae3ee268f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077228427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2077228427
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.865005386
Short name T860
Test name
Test status
Simulation time 499966027 ps
CPU time 1.83 seconds
Started Jul 04 06:54:00 PM PDT 24
Finished Jul 04 06:54:02 PM PDT 24
Peak memory 201444 kb
Host smart-056387ab-1cf6-457c-8d47-649169a16403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865005386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.865005386
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3425340866
Short name T843
Test name
Test status
Simulation time 4843110676 ps
CPU time 16.83 seconds
Started Jul 04 06:53:59 PM PDT 24
Finished Jul 04 06:54:16 PM PDT 24
Peak memory 201892 kb
Host smart-767ee8ae-c511-4086-9676-e4b77058820d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425340866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3425340866
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3855722520
Short name T834
Test name
Test status
Simulation time 508669579 ps
CPU time 3.35 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:54:02 PM PDT 24
Peak memory 211064 kb
Host smart-f0e255d3-97c0-4257-a16e-f466e0d431c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855722520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3855722520
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1250045454
Short name T85
Test name
Test status
Simulation time 4357163908 ps
CPU time 10.86 seconds
Started Jul 04 06:53:59 PM PDT 24
Finished Jul 04 06:54:10 PM PDT 24
Peak memory 201784 kb
Host smart-d7387e34-6356-497b-8f00-e2911dfd2428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250045454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1250045454
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1261278182
Short name T114
Test name
Test status
Simulation time 1252570838 ps
CPU time 4.94 seconds
Started Jul 04 06:53:31 PM PDT 24
Finished Jul 04 06:53:36 PM PDT 24
Peak memory 201748 kb
Host smart-3b3a3d63-f187-446a-8582-c7ee43a9711a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261278182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1261278182
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2909980238
Short name T117
Test name
Test status
Simulation time 1183844162 ps
CPU time 0.96 seconds
Started Jul 04 06:53:31 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201480 kb
Host smart-343e7193-24eb-4e52-96d2-2cc135cd6228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909980238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2909980238
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3441376931
Short name T872
Test name
Test status
Simulation time 492284928 ps
CPU time 1.14 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:30 PM PDT 24
Peak memory 201584 kb
Host smart-6ff12193-fb26-4f29-a122-e05f1601bb45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441376931 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3441376931
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3300483048
Short name T119
Test name
Test status
Simulation time 433910762 ps
CPU time 1.23 seconds
Started Jul 04 06:53:32 PM PDT 24
Finished Jul 04 06:53:33 PM PDT 24
Peak memory 201476 kb
Host smart-23273bc2-de54-40cc-8987-cff4fbdef4c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300483048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3300483048
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.63687057
Short name T800
Test name
Test status
Simulation time 384231152 ps
CPU time 0.87 seconds
Started Jul 04 06:53:31 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201468 kb
Host smart-32b3fbb6-0b52-4b7a-afda-d3d889f7bec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63687057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.63687057
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2493360021
Short name T849
Test name
Test status
Simulation time 4600375189 ps
CPU time 16.53 seconds
Started Jul 04 06:53:32 PM PDT 24
Finished Jul 04 06:53:48 PM PDT 24
Peak memory 201816 kb
Host smart-f19aba7b-8dcb-4a5d-b8e5-b9f20c9a6909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493360021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2493360021
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.911656426
Short name T78
Test name
Test status
Simulation time 530045294 ps
CPU time 3.28 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:33 PM PDT 24
Peak memory 201768 kb
Host smart-13e0e807-9aac-4c87-8f55-702d0a51de2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911656426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.911656426
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2824034786
Short name T70
Test name
Test status
Simulation time 7813038211 ps
CPU time 20.17 seconds
Started Jul 04 06:53:31 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201860 kb
Host smart-66e553f8-a404-4ff8-ae38-06ef2e4b424f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824034786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2824034786
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2571386921
Short name T844
Test name
Test status
Simulation time 341066109 ps
CPU time 1.56 seconds
Started Jul 04 06:53:57 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201456 kb
Host smart-05652b5d-382a-4438-a87f-3279ed0fdc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571386921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2571386921
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3503106884
Short name T861
Test name
Test status
Simulation time 287050325 ps
CPU time 1.2 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201400 kb
Host smart-94406bed-8e9e-4a3b-9d67-3ba15b5636c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503106884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3503106884
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2007102508
Short name T905
Test name
Test status
Simulation time 306219863 ps
CPU time 1.05 seconds
Started Jul 04 06:53:59 PM PDT 24
Finished Jul 04 06:54:00 PM PDT 24
Peak memory 201432 kb
Host smart-18932539-d3f3-4f18-a4ed-fd92395eaf0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007102508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2007102508
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3241929368
Short name T835
Test name
Test status
Simulation time 443014912 ps
CPU time 0.74 seconds
Started Jul 04 06:53:57 PM PDT 24
Finished Jul 04 06:53:58 PM PDT 24
Peak memory 201476 kb
Host smart-c1e1ac1f-9554-4e54-8e86-598dba9d9ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241929368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3241929368
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3152889595
Short name T865
Test name
Test status
Simulation time 392957449 ps
CPU time 1.47 seconds
Started Jul 04 06:53:59 PM PDT 24
Finished Jul 04 06:54:00 PM PDT 24
Peak memory 201384 kb
Host smart-1600a4cd-5281-49c2-a5bf-7dcbfb56cb26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152889595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3152889595
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1052953046
Short name T799
Test name
Test status
Simulation time 528918781 ps
CPU time 1.02 seconds
Started Jul 04 06:54:00 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201464 kb
Host smart-95ba7db0-d3c2-40ea-97a5-d56fea3a59f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052953046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1052953046
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2128396878
Short name T878
Test name
Test status
Simulation time 299625933 ps
CPU time 1.36 seconds
Started Jul 04 06:53:57 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201452 kb
Host smart-7604d1bd-63bc-4ccb-a86b-2feb0582a999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128396878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2128396878
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3004684478
Short name T906
Test name
Test status
Simulation time 339004868 ps
CPU time 0.84 seconds
Started Jul 04 06:54:00 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201436 kb
Host smart-074922ac-a8c6-4c86-bcaa-67c1df514446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004684478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3004684478
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.183797283
Short name T893
Test name
Test status
Simulation time 384061602 ps
CPU time 0.81 seconds
Started Jul 04 06:54:00 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201444 kb
Host smart-57c47383-76ad-438f-ad44-7be99b93f225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183797283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.183797283
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3289438679
Short name T816
Test name
Test status
Simulation time 305361883 ps
CPU time 1.32 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201448 kb
Host smart-9f5e77fc-52b1-4cae-a749-042ae63f2839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289438679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3289438679
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2676918274
Short name T823
Test name
Test status
Simulation time 703413755 ps
CPU time 2.85 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:33 PM PDT 24
Peak memory 201716 kb
Host smart-0fc6b6f9-5958-42c9-ad23-06fd4cdc8c09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676918274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2676918274
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2580726505
Short name T120
Test name
Test status
Simulation time 49804874441 ps
CPU time 59.83 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:54:30 PM PDT 24
Peak memory 201808 kb
Host smart-164b5efa-a27d-4bf1-8665-09378f26567e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580726505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2580726505
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3774125908
Short name T118
Test name
Test status
Simulation time 763320178 ps
CPU time 1.62 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:31 PM PDT 24
Peak memory 201508 kb
Host smart-d4f20d23-8a6c-4ef0-9fad-525ad74805f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774125908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3774125908
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1174054117
Short name T81
Test name
Test status
Simulation time 904687100 ps
CPU time 1.41 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 209940 kb
Host smart-2c5034e0-7bdb-4442-a128-6c35c9781679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174054117 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1174054117
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.841792509
Short name T122
Test name
Test status
Simulation time 521027318 ps
CPU time 1.6 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201512 kb
Host smart-db7b166c-a064-4fe0-915f-955374c9aa35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841792509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.841792509
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3065809472
Short name T876
Test name
Test status
Simulation time 310619079 ps
CPU time 0.98 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:30 PM PDT 24
Peak memory 201384 kb
Host smart-cc347b1c-db9c-4a94-a9e2-b08c2d55e74b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065809472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3065809472
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1675846118
Short name T885
Test name
Test status
Simulation time 4118970793 ps
CPU time 16.44 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:46 PM PDT 24
Peak memory 201744 kb
Host smart-7f3f1ef5-bf1d-4f68-8f16-2ec8a496d4f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675846118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1675846118
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2886382390
Short name T903
Test name
Test status
Simulation time 1052857433 ps
CPU time 2.87 seconds
Started Jul 04 06:53:32 PM PDT 24
Finished Jul 04 06:53:35 PM PDT 24
Peak memory 218084 kb
Host smart-b06997de-61c9-4aa0-838a-cb2d0978183d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886382390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2886382390
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2172249433
Short name T890
Test name
Test status
Simulation time 8767577968 ps
CPU time 21.95 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:52 PM PDT 24
Peak memory 201880 kb
Host smart-43abd17a-98de-43d6-a4d2-f76559551fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172249433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2172249433
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4137409181
Short name T891
Test name
Test status
Simulation time 447983295 ps
CPU time 1.65 seconds
Started Jul 04 06:54:00 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201400 kb
Host smart-4c257559-6eca-419b-b1b7-bcc8ad3dbae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137409181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4137409181
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2467180519
Short name T822
Test name
Test status
Simulation time 509452469 ps
CPU time 0.96 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:54:00 PM PDT 24
Peak memory 201456 kb
Host smart-77b0c495-96bb-4514-b2c6-45683ff20b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467180519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2467180519
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1906845558
Short name T917
Test name
Test status
Simulation time 488935727 ps
CPU time 1.22 seconds
Started Jul 04 06:53:59 PM PDT 24
Finished Jul 04 06:54:00 PM PDT 24
Peak memory 201360 kb
Host smart-aac3d197-cff8-4572-b640-04d2039654bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906845558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1906845558
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.840049708
Short name T826
Test name
Test status
Simulation time 369197077 ps
CPU time 1.2 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:53:59 PM PDT 24
Peak memory 201440 kb
Host smart-e8edd1a3-efc6-4e26-afbc-cd627953b42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840049708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.840049708
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.319704516
Short name T802
Test name
Test status
Simulation time 502753384 ps
CPU time 1.04 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:54:00 PM PDT 24
Peak memory 201412 kb
Host smart-5b1b3b31-2dcd-47ed-8a12-ceb6df4ec5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319704516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.319704516
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2103374892
Short name T894
Test name
Test status
Simulation time 508251045 ps
CPU time 0.93 seconds
Started Jul 04 06:53:57 PM PDT 24
Finished Jul 04 06:53:58 PM PDT 24
Peak memory 201420 kb
Host smart-0083f706-35be-4c32-b39e-1d39fd3465ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103374892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2103374892
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.850286877
Short name T856
Test name
Test status
Simulation time 325110862 ps
CPU time 1.33 seconds
Started Jul 04 06:53:59 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201448 kb
Host smart-4935f6b4-3e5c-4c2b-861f-610f659b14be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850286877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.850286877
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2967320837
Short name T797
Test name
Test status
Simulation time 458246473 ps
CPU time 1.74 seconds
Started Jul 04 06:53:58 PM PDT 24
Finished Jul 04 06:54:01 PM PDT 24
Peak memory 201476 kb
Host smart-57d51d6b-6fbe-4e42-8c7c-4717fc8a9b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967320837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2967320837
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2153752844
Short name T875
Test name
Test status
Simulation time 398969934 ps
CPU time 0.72 seconds
Started Jul 04 06:54:06 PM PDT 24
Finished Jul 04 06:54:07 PM PDT 24
Peak memory 201420 kb
Host smart-821698a5-a572-4bd6-b34a-8866e63ab85c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153752844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2153752844
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.730056120
Short name T911
Test name
Test status
Simulation time 447446446 ps
CPU time 1.16 seconds
Started Jul 04 06:54:06 PM PDT 24
Finished Jul 04 06:54:07 PM PDT 24
Peak memory 201448 kb
Host smart-9576a2f9-0d2f-463e-9d16-59b7de2c6a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730056120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.730056120
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1873156075
Short name T907
Test name
Test status
Simulation time 996938791 ps
CPU time 3.2 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:42 PM PDT 24
Peak memory 201740 kb
Host smart-444ce165-9bcb-4b4a-9f06-779ac6b41ff9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873156075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1873156075
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2552169465
Short name T812
Test name
Test status
Simulation time 26558484157 ps
CPU time 128.91 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:55:47 PM PDT 24
Peak memory 201816 kb
Host smart-2e775cc4-a51c-410a-9408-bcbf964b3f36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552169465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2552169465
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1027060663
Short name T124
Test name
Test status
Simulation time 1355039291 ps
CPU time 1.54 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:31 PM PDT 24
Peak memory 201508 kb
Host smart-73846e85-0406-4a1a-b782-c326f306bcb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027060663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1027060663
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1111230849
Short name T82
Test name
Test status
Simulation time 426233790 ps
CPU time 1.26 seconds
Started Jul 04 06:53:40 PM PDT 24
Finished Jul 04 06:53:41 PM PDT 24
Peak memory 201600 kb
Host smart-6481e2ab-f4e3-434a-830b-8b11b36de26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111230849 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1111230849
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.776875401
Short name T855
Test name
Test status
Simulation time 566971727 ps
CPU time 2.1 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201488 kb
Host smart-9f55c413-7030-4a68-be4e-792ea2c3b1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776875401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.776875401
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.935951816
Short name T846
Test name
Test status
Simulation time 498092985 ps
CPU time 1.8 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:32 PM PDT 24
Peak memory 201412 kb
Host smart-393f9945-4e20-4da6-80b6-17f931221b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935951816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.935951816
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4213278897
Short name T839
Test name
Test status
Simulation time 1669522580 ps
CPU time 2.63 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:42 PM PDT 24
Peak memory 201488 kb
Host smart-22383ee7-4d3b-40b1-bcbe-b63020a43389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213278897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4213278897
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2213037097
Short name T814
Test name
Test status
Simulation time 483590120 ps
CPU time 1.3 seconds
Started Jul 04 06:53:29 PM PDT 24
Finished Jul 04 06:53:30 PM PDT 24
Peak memory 201772 kb
Host smart-02b38e2d-21f7-447f-9d4c-1f4b25bd3864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213037097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2213037097
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.617052799
Short name T810
Test name
Test status
Simulation time 4428206502 ps
CPU time 4.31 seconds
Started Jul 04 06:53:30 PM PDT 24
Finished Jul 04 06:53:35 PM PDT 24
Peak memory 201724 kb
Host smart-a7b40895-4f5d-4367-9714-2a49d04b6916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617052799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.617052799
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.565411969
Short name T877
Test name
Test status
Simulation time 499004306 ps
CPU time 1.29 seconds
Started Jul 04 06:54:02 PM PDT 24
Finished Jul 04 06:54:04 PM PDT 24
Peak memory 201448 kb
Host smart-c79c635d-25f6-4819-b316-1e67944299e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565411969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.565411969
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2177276447
Short name T882
Test name
Test status
Simulation time 518256014 ps
CPU time 0.89 seconds
Started Jul 04 06:54:04 PM PDT 24
Finished Jul 04 06:54:05 PM PDT 24
Peak memory 201452 kb
Host smart-e8c85c9e-890d-4fb3-b0f1-78c1873789a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177276447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2177276447
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.557048810
Short name T863
Test name
Test status
Simulation time 347061617 ps
CPU time 1.4 seconds
Started Jul 04 06:54:08 PM PDT 24
Finished Jul 04 06:54:09 PM PDT 24
Peak memory 201404 kb
Host smart-f4435cae-f827-455e-86ea-87a37dfd4b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557048810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.557048810
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.895234746
Short name T853
Test name
Test status
Simulation time 507494227 ps
CPU time 1.72 seconds
Started Jul 04 06:54:05 PM PDT 24
Finished Jul 04 06:54:07 PM PDT 24
Peak memory 201440 kb
Host smart-e6ba6d2e-6762-491d-8d50-9029937fb283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895234746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.895234746
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.815915374
Short name T857
Test name
Test status
Simulation time 422787310 ps
CPU time 1.58 seconds
Started Jul 04 06:54:06 PM PDT 24
Finished Jul 04 06:54:08 PM PDT 24
Peak memory 201444 kb
Host smart-d599fc5b-2b4c-4006-9337-74d5412517cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815915374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.815915374
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.679627150
Short name T801
Test name
Test status
Simulation time 496882879 ps
CPU time 0.94 seconds
Started Jul 04 06:54:04 PM PDT 24
Finished Jul 04 06:54:05 PM PDT 24
Peak memory 201456 kb
Host smart-cdda9342-4e40-44c9-82ca-b3784043332e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679627150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.679627150
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1504457565
Short name T851
Test name
Test status
Simulation time 357891877 ps
CPU time 0.87 seconds
Started Jul 04 06:54:06 PM PDT 24
Finished Jul 04 06:54:07 PM PDT 24
Peak memory 201460 kb
Host smart-4c087109-66b6-4b78-9b88-87c301e1bbca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504457565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1504457565
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.944100204
Short name T828
Test name
Test status
Simulation time 410188025 ps
CPU time 0.76 seconds
Started Jul 04 06:54:06 PM PDT 24
Finished Jul 04 06:54:07 PM PDT 24
Peak memory 201448 kb
Host smart-a4d587bd-0ec3-491e-b864-18f02749ffcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944100204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.944100204
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.561179271
Short name T806
Test name
Test status
Simulation time 493542742 ps
CPU time 1.89 seconds
Started Jul 04 06:54:05 PM PDT 24
Finished Jul 04 06:54:07 PM PDT 24
Peak memory 201404 kb
Host smart-411fb57a-e681-4e19-b3a8-68b9bfa45e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561179271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.561179271
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2459955804
Short name T858
Test name
Test status
Simulation time 531510975 ps
CPU time 0.82 seconds
Started Jul 04 06:54:08 PM PDT 24
Finished Jul 04 06:54:09 PM PDT 24
Peak memory 201384 kb
Host smart-608bc177-97b5-40da-9a37-f1c99cb44d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459955804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2459955804
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1942096906
Short name T904
Test name
Test status
Simulation time 557251876 ps
CPU time 2.06 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:42 PM PDT 24
Peak memory 201604 kb
Host smart-1a4f716c-0a93-460b-9ddf-65040f5ff7b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942096906 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1942096906
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.995992340
Short name T110
Test name
Test status
Simulation time 395538069 ps
CPU time 1.15 seconds
Started Jul 04 06:53:40 PM PDT 24
Finished Jul 04 06:53:42 PM PDT 24
Peak memory 201520 kb
Host smart-ae3120dd-462f-400a-94d7-32630ad4bd49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995992340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.995992340
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1935934332
Short name T868
Test name
Test status
Simulation time 507533870 ps
CPU time 1.76 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:40 PM PDT 24
Peak memory 201408 kb
Host smart-08419ccb-64f2-4d26-b8ec-03d01840482b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935934332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1935934332
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3952910724
Short name T908
Test name
Test status
Simulation time 2402223786 ps
CPU time 4.54 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:43 PM PDT 24
Peak memory 201612 kb
Host smart-153b7a05-1f7a-4615-b6a7-f5003b8ee63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952910724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3952910724
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2935278964
Short name T898
Test name
Test status
Simulation time 462890280 ps
CPU time 3 seconds
Started Jul 04 06:53:36 PM PDT 24
Finished Jul 04 06:53:39 PM PDT 24
Peak memory 201764 kb
Host smart-a879d4a0-7f8d-4c4c-926e-6f266058aa19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935278964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2935278964
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.469042852
Short name T841
Test name
Test status
Simulation time 4601571941 ps
CPU time 4.36 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:43 PM PDT 24
Peak memory 201900 kb
Host smart-8286db82-c9ea-451d-9073-da706ae5204d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469042852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.469042852
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4187092606
Short name T817
Test name
Test status
Simulation time 524792995 ps
CPU time 2.1 seconds
Started Jul 04 06:53:40 PM PDT 24
Finished Jul 04 06:53:42 PM PDT 24
Peak memory 201596 kb
Host smart-a808b6eb-7bb0-446a-ae9f-3a0273b36a31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187092606 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4187092606
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.257745301
Short name T901
Test name
Test status
Simulation time 448314040 ps
CPU time 1.2 seconds
Started Jul 04 06:53:43 PM PDT 24
Finished Jul 04 06:53:44 PM PDT 24
Peak memory 201512 kb
Host smart-952ba183-2567-41fe-9cc7-892deb9f9c85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257745301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.257745301
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1228650799
Short name T838
Test name
Test status
Simulation time 361459352 ps
CPU time 0.85 seconds
Started Jul 04 06:53:37 PM PDT 24
Finished Jul 04 06:53:38 PM PDT 24
Peak memory 201428 kb
Host smart-01f11a82-71fb-4dbb-98d0-1c0e1b31d455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228650799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1228650799
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.601226951
Short name T827
Test name
Test status
Simulation time 2335953458 ps
CPU time 2.43 seconds
Started Jul 04 06:53:40 PM PDT 24
Finished Jul 04 06:53:43 PM PDT 24
Peak memory 201636 kb
Host smart-f3a1427c-fc71-4600-be6d-440b56b355eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601226951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.601226951
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2696954772
Short name T821
Test name
Test status
Simulation time 522913146 ps
CPU time 1.74 seconds
Started Jul 04 06:53:41 PM PDT 24
Finished Jul 04 06:53:43 PM PDT 24
Peak memory 201828 kb
Host smart-881af05f-74d1-4d35-a79f-e6d2eaca4f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696954772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2696954772
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.639184532
Short name T66
Test name
Test status
Simulation time 8457348861 ps
CPU time 5.66 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:45 PM PDT 24
Peak memory 201908 kb
Host smart-69514493-ee82-4ec9-b1a4-e8c5a085a44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639184532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.639184532
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4291999889
Short name T74
Test name
Test status
Simulation time 515105147 ps
CPU time 1.61 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:40 PM PDT 24
Peak memory 201576 kb
Host smart-c2c96f1e-d678-4317-9dc4-e5410c9bc946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291999889 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4291999889
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2648838160
Short name T840
Test name
Test status
Simulation time 489565078 ps
CPU time 1.01 seconds
Started Jul 04 06:53:42 PM PDT 24
Finished Jul 04 06:53:43 PM PDT 24
Peak memory 201524 kb
Host smart-a620a900-2bf4-476b-afc0-b31726005a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648838160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2648838160
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3522919737
Short name T854
Test name
Test status
Simulation time 332695302 ps
CPU time 1.35 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:39 PM PDT 24
Peak memory 201416 kb
Host smart-54ed32d7-a02d-41c7-92a9-87e168d2ec9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522919737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3522919737
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2449017710
Short name T909
Test name
Test status
Simulation time 2833892044 ps
CPU time 2.69 seconds
Started Jul 04 06:53:42 PM PDT 24
Finished Jul 04 06:53:45 PM PDT 24
Peak memory 201648 kb
Host smart-61f37527-6a54-4f78-b520-dcfd4e1ab6c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449017710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2449017710
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.750107237
Short name T819
Test name
Test status
Simulation time 568046841 ps
CPU time 2.35 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:41 PM PDT 24
Peak memory 201824 kb
Host smart-386c8543-826a-4558-8f8d-a6a10dd43a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750107237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.750107237
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3443850003
Short name T902
Test name
Test status
Simulation time 3802585650 ps
CPU time 4 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:43 PM PDT 24
Peak memory 201848 kb
Host smart-dca69748-6733-4e59-b9e9-ed47a1ede397
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443850003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3443850003
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3254912535
Short name T859
Test name
Test status
Simulation time 441038094 ps
CPU time 1.06 seconds
Started Jul 04 06:53:37 PM PDT 24
Finished Jul 04 06:53:39 PM PDT 24
Peak memory 201576 kb
Host smart-d43f4182-09c5-456e-bc79-d9345c44433d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254912535 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3254912535
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.306077722
Short name T115
Test name
Test status
Simulation time 579394151 ps
CPU time 1.12 seconds
Started Jul 04 06:53:43 PM PDT 24
Finished Jul 04 06:53:44 PM PDT 24
Peak memory 201512 kb
Host smart-0027d9b9-3c12-4ea9-86da-60f274ec66dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306077722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.306077722
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2936655529
Short name T892
Test name
Test status
Simulation time 426551531 ps
CPU time 0.89 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:40 PM PDT 24
Peak memory 201364 kb
Host smart-3f0c7e60-129b-4939-b8f2-e491db3e2a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936655529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2936655529
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1490548078
Short name T126
Test name
Test status
Simulation time 2203165722 ps
CPU time 5.44 seconds
Started Jul 04 06:53:42 PM PDT 24
Finished Jul 04 06:53:48 PM PDT 24
Peak memory 201628 kb
Host smart-8d2ed9c1-7e9b-438b-80fc-c8001b1dfff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490548078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1490548078
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1832222676
Short name T884
Test name
Test status
Simulation time 642382568 ps
CPU time 4.16 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:44 PM PDT 24
Peak memory 210024 kb
Host smart-e915e0d0-9203-4f37-afd8-d98e2474e24f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832222676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1832222676
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3163110526
Short name T65
Test name
Test status
Simulation time 8309270920 ps
CPU time 7.28 seconds
Started Jul 04 06:53:42 PM PDT 24
Finished Jul 04 06:53:50 PM PDT 24
Peak memory 201880 kb
Host smart-2ed4dcfe-80ab-4972-b65c-7e7c6fc4c831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163110526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3163110526
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3529400411
Short name T830
Test name
Test status
Simulation time 358169953 ps
CPU time 1.24 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:40 PM PDT 24
Peak memory 201572 kb
Host smart-40f063be-5811-49c6-82b1-e637f875b4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529400411 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3529400411
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3852001158
Short name T918
Test name
Test status
Simulation time 494848136 ps
CPU time 1.88 seconds
Started Jul 04 06:53:38 PM PDT 24
Finished Jul 04 06:53:41 PM PDT 24
Peak memory 201492 kb
Host smart-1337c3f1-3f68-4d91-967e-afbf66774b56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852001158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3852001158
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1329998092
Short name T804
Test name
Test status
Simulation time 408905268 ps
CPU time 0.74 seconds
Started Jul 04 06:53:39 PM PDT 24
Finished Jul 04 06:53:39 PM PDT 24
Peak memory 201428 kb
Host smart-f88c98f4-e3cf-47e7-9738-efcd25697a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329998092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1329998092
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.52691887
Short name T887
Test name
Test status
Simulation time 2324297260 ps
CPU time 6.29 seconds
Started Jul 04 06:53:40 PM PDT 24
Finished Jul 04 06:53:46 PM PDT 24
Peak memory 201648 kb
Host smart-b9c3b835-7cd0-4b6f-b335-263e397b5b79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52691887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctr
l_same_csr_outstanding.52691887
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3476890589
Short name T867
Test name
Test status
Simulation time 370816099 ps
CPU time 2.63 seconds
Started Jul 04 06:53:37 PM PDT 24
Finished Jul 04 06:53:40 PM PDT 24
Peak memory 210988 kb
Host smart-2a686607-5f22-428b-adb5-9b8db43395ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476890589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3476890589
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.178393296
Short name T914
Test name
Test status
Simulation time 4140446454 ps
CPU time 11.71 seconds
Started Jul 04 06:53:37 PM PDT 24
Finished Jul 04 06:53:49 PM PDT 24
Peak memory 201828 kb
Host smart-9109fd2e-5f19-4f2d-8d50-890bc6c231d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178393296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.178393296
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1588948881
Short name T542
Test name
Test status
Simulation time 513507484 ps
CPU time 0.9 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:00:09 PM PDT 24
Peak memory 201680 kb
Host smart-b90d044b-3b81-4c23-b0dc-974f795a3eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588948881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1588948881
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1658203531
Short name T275
Test name
Test status
Simulation time 203170540818 ps
CPU time 477.94 seconds
Started Jul 04 07:00:12 PM PDT 24
Finished Jul 04 07:08:10 PM PDT 24
Peak memory 202004 kb
Host smart-d66acc91-85be-40df-bd73-e4078b9cd578
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658203531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1658203531
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3151355242
Short name T288
Test name
Test status
Simulation time 325011612511 ps
CPU time 194.7 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:03:22 PM PDT 24
Peak memory 201844 kb
Host smart-35397099-5743-4b5c-8a7d-6919342ba871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151355242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3151355242
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3543017122
Short name T671
Test name
Test status
Simulation time 488981935578 ps
CPU time 149.78 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:02:34 PM PDT 24
Peak memory 201852 kb
Host smart-1abac7aa-826e-4526-9201-aaa27106f79e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543017122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3543017122
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2569112150
Short name T468
Test name
Test status
Simulation time 320573816388 ps
CPU time 355.49 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:05:59 PM PDT 24
Peak memory 201916 kb
Host smart-d160ea78-1b96-45f0-8c96-8f1f562fe8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569112150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2569112150
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3619329686
Short name T718
Test name
Test status
Simulation time 159688586309 ps
CPU time 376.61 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:06:21 PM PDT 24
Peak memory 201896 kb
Host smart-3d407654-1ee9-4a28-a3b3-3bc3a9bef219
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619329686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3619329686
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1315224244
Short name T771
Test name
Test status
Simulation time 545189848004 ps
CPU time 1135.44 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:18:59 PM PDT 24
Peak memory 201912 kb
Host smart-7eb48c52-d3e5-4857-bdf7-b43c4b050587
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315224244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1315224244
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2804471217
Short name T40
Test name
Test status
Simulation time 198097027522 ps
CPU time 224.87 seconds
Started Jul 04 07:00:05 PM PDT 24
Finished Jul 04 07:03:50 PM PDT 24
Peak memory 201908 kb
Host smart-d20c3ca4-7ced-42ea-8203-5653893acdb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804471217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2804471217
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.670286857
Short name T574
Test name
Test status
Simulation time 73257089519 ps
CPU time 247.48 seconds
Started Jul 04 07:00:02 PM PDT 24
Finished Jul 04 07:04:09 PM PDT 24
Peak memory 202244 kb
Host smart-fa1e3509-1838-47e7-a478-fbcd9789a3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670286857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.670286857
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3579835990
Short name T487
Test name
Test status
Simulation time 33066600498 ps
CPU time 17.99 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:26 PM PDT 24
Peak memory 201732 kb
Host smart-e7d100ae-8760-4ec3-a4f4-3f1f3243fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579835990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3579835990
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2436517864
Short name T440
Test name
Test status
Simulation time 4158629473 ps
CPU time 9.02 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:16 PM PDT 24
Peak memory 201708 kb
Host smart-255db936-d1e1-4fa6-91c7-feeb37ba1bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436517864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2436517864
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2333105363
Short name T426
Test name
Test status
Simulation time 6210004791 ps
CPU time 13.51 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:00:21 PM PDT 24
Peak memory 201712 kb
Host smart-03ff85e6-0b66-4cde-9488-3042a3d6767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333105363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2333105363
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3713534614
Short name T785
Test name
Test status
Simulation time 10068075226 ps
CPU time 13.03 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:20 PM PDT 24
Peak memory 201700 kb
Host smart-551cc282-d605-49af-adc5-70681787fe81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713534614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3713534614
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.526744707
Short name T576
Test name
Test status
Simulation time 328601543824 ps
CPU time 354.55 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:06:02 PM PDT 24
Peak memory 201892 kb
Host smart-4e72964f-f001-4858-883b-8a3dc6dc0e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526744707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.526744707
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3757912453
Short name T583
Test name
Test status
Simulation time 336973479724 ps
CPU time 72.73 seconds
Started Jul 04 07:00:12 PM PDT 24
Finished Jul 04 07:01:25 PM PDT 24
Peak memory 201348 kb
Host smart-21f13b20-ca9b-45d8-b6f6-653bbc4cf51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757912453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3757912453
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3677610925
Short name T427
Test name
Test status
Simulation time 491361256118 ps
CPU time 661.93 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:11:09 PM PDT 24
Peak memory 201896 kb
Host smart-5333bbf8-488d-4a7b-9438-237083e9abc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677610925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3677610925
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1709099671
Short name T526
Test name
Test status
Simulation time 331400075195 ps
CPU time 713.83 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:12:01 PM PDT 24
Peak memory 201876 kb
Host smart-16d5971f-2c58-4b4b-b100-3a1a9a735157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709099671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1709099671
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3589539671
Short name T177
Test name
Test status
Simulation time 319094489700 ps
CPU time 761.99 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:12:45 PM PDT 24
Peak memory 201892 kb
Host smart-a6fd2791-e422-4fa2-936b-51bd0b644496
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589539671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3589539671
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2282255281
Short name T266
Test name
Test status
Simulation time 353207369581 ps
CPU time 784.8 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:13:08 PM PDT 24
Peak memory 201952 kb
Host smart-e5609b23-ef9c-45e3-8ec2-e74f74d94592
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282255281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2282255281
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1466703697
Short name T204
Test name
Test status
Simulation time 405019902191 ps
CPU time 251.82 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:04:20 PM PDT 24
Peak memory 201864 kb
Host smart-d8bd396c-9668-46c1-b5bf-b040a09d94a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466703697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1466703697
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.752028174
Short name T635
Test name
Test status
Simulation time 45294892580 ps
CPU time 26.51 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:29 PM PDT 24
Peak memory 201704 kb
Host smart-d877d095-b9a1-4494-a0a7-3d0cef65284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752028174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.752028174
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1643816791
Short name T662
Test name
Test status
Simulation time 3936420855 ps
CPU time 3.02 seconds
Started Jul 04 07:00:06 PM PDT 24
Finished Jul 04 07:00:09 PM PDT 24
Peak memory 201704 kb
Host smart-f4574703-b1bc-49cb-9d96-7eda4953b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643816791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1643816791
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2017404174
Short name T72
Test name
Test status
Simulation time 4188786123 ps
CPU time 5.89 seconds
Started Jul 04 07:00:04 PM PDT 24
Finished Jul 04 07:00:11 PM PDT 24
Peak memory 217160 kb
Host smart-69a28403-6879-4f71-9507-4c6269d3b0d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017404174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2017404174
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1772418267
Short name T424
Test name
Test status
Simulation time 5893148263 ps
CPU time 11.44 seconds
Started Jul 04 07:00:03 PM PDT 24
Finished Jul 04 07:00:15 PM PDT 24
Peak memory 201752 kb
Host smart-75b4533a-d7d7-47b0-b3b4-3e9902d863aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772418267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1772418267
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.93953594
Short name T272
Test name
Test status
Simulation time 48430788053 ps
CPU time 145.16 seconds
Started Jul 04 07:00:05 PM PDT 24
Finished Jul 04 07:02:31 PM PDT 24
Peak memory 210576 kb
Host smart-3b90637a-9574-4e21-ad90-0c5d5d9e49e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93953594 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.93953594
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2984197482
Short name T557
Test name
Test status
Simulation time 523091105 ps
CPU time 1.72 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:00:41 PM PDT 24
Peak memory 201676 kb
Host smart-41466310-8a3e-4a1a-a945-46cc5a7509d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984197482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2984197482
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.556138475
Short name T591
Test name
Test status
Simulation time 527722276202 ps
CPU time 205.41 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:04:05 PM PDT 24
Peak memory 201928 kb
Host smart-2f62db99-d2a9-4c95-93cb-0674468f80d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556138475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.556138475
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.813594431
Short name T711
Test name
Test status
Simulation time 371141637275 ps
CPU time 791.17 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:13:50 PM PDT 24
Peak memory 201904 kb
Host smart-1ce3f9cf-1c51-4f76-bc86-268a7a3b6d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813594431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.813594431
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.4072208603
Short name T604
Test name
Test status
Simulation time 331919060259 ps
CPU time 189.45 seconds
Started Jul 04 07:00:30 PM PDT 24
Finished Jul 04 07:03:39 PM PDT 24
Peak memory 201860 kb
Host smart-3294c378-729a-4c55-ba61-dab7e9a33dab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072208603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.4072208603
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2704773473
Short name T31
Test name
Test status
Simulation time 490164904386 ps
CPU time 167.98 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:03:22 PM PDT 24
Peak memory 201928 kb
Host smart-f6e1a7ca-4ca2-4a25-a4a4-4699d8fa3550
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704773473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2704773473
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1275073363
Short name T722
Test name
Test status
Simulation time 359685487661 ps
CPU time 416.06 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:07:36 PM PDT 24
Peak memory 201980 kb
Host smart-2021fc6f-d1a3-4e29-a61f-4eac87130552
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275073363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1275073363
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1389233829
Short name T395
Test name
Test status
Simulation time 415173802415 ps
CPU time 263.42 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:05:03 PM PDT 24
Peak memory 201908 kb
Host smart-1ce56804-8a11-40dd-9c05-389e7cc11610
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389233829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1389233829
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2970491535
Short name T485
Test name
Test status
Simulation time 99314960139 ps
CPU time 370.15 seconds
Started Jul 04 07:00:37 PM PDT 24
Finished Jul 04 07:06:49 PM PDT 24
Peak memory 202200 kb
Host smart-c3ae3457-3c30-414b-ac46-1cd334631d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970491535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2970491535
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.901501568
Short name T461
Test name
Test status
Simulation time 28050360756 ps
CPU time 4.01 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:00:43 PM PDT 24
Peak memory 201724 kb
Host smart-49446d77-eabc-4fb6-8719-1dc5bf913ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901501568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.901501568
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1807684243
Short name T486
Test name
Test status
Simulation time 4886663762 ps
CPU time 3.35 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:00:44 PM PDT 24
Peak memory 201732 kb
Host smart-45a2f36a-c4c4-4469-a6ed-83431db0c5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807684243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1807684243
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.52975589
Short name T429
Test name
Test status
Simulation time 5799070821 ps
CPU time 13.09 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:00:46 PM PDT 24
Peak memory 201740 kb
Host smart-54bf0c62-2d98-490d-a0c6-25a6bee6fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52975589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.52975589
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3290360397
Short name T465
Test name
Test status
Simulation time 308353970 ps
CPU time 0.89 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:00:40 PM PDT 24
Peak memory 201676 kb
Host smart-58e84a8b-56df-42c5-a62e-d6051b974a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290360397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3290360397
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3567313846
Short name T271
Test name
Test status
Simulation time 344267903282 ps
CPU time 776.31 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:13:37 PM PDT 24
Peak memory 201928 kb
Host smart-1f2acb6d-7554-4629-a597-c9592b3a1d85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567313846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3567313846
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3193029512
Short name T315
Test name
Test status
Simulation time 515925077052 ps
CPU time 1194.39 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:20:34 PM PDT 24
Peak memory 201984 kb
Host smart-e0366f87-aba5-45df-bd00-58fff01a763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193029512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3193029512
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.171152396
Short name T536
Test name
Test status
Simulation time 328271029753 ps
CPU time 354.9 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:06:35 PM PDT 24
Peak memory 201976 kb
Host smart-e427b55d-5aca-47f8-9a89-745ed19ae4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171152396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.171152396
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.365301112
Short name T421
Test name
Test status
Simulation time 327998391100 ps
CPU time 194.88 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:03:56 PM PDT 24
Peak memory 201864 kb
Host smart-7972ddfb-167c-47c5-a602-893484982cf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=365301112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.365301112
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2394472847
Short name T782
Test name
Test status
Simulation time 165518832821 ps
CPU time 179.02 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:03:38 PM PDT 24
Peak memory 201952 kb
Host smart-2cdc2a07-51e3-423f-8a3c-d6173d7985f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394472847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2394472847
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.34003261
Short name T661
Test name
Test status
Simulation time 167072535603 ps
CPU time 64.74 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:01:44 PM PDT 24
Peak memory 201916 kb
Host smart-a50233f5-885d-4a50-b571-b8b76a1b6b73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=34003261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed
.34003261
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3917542851
Short name T755
Test name
Test status
Simulation time 602124802563 ps
CPU time 324.97 seconds
Started Jul 04 07:00:43 PM PDT 24
Finished Jul 04 07:06:08 PM PDT 24
Peak memory 201980 kb
Host smart-d76040e6-fa5d-4030-960f-f6e41694c42c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917542851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3917542851
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4121679920
Short name T783
Test name
Test status
Simulation time 83833004211 ps
CPU time 398.6 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:07:18 PM PDT 24
Peak memory 202280 kb
Host smart-bb0c75ff-ee6c-41cc-8d96-45285328eaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121679920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4121679920
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1043480376
Short name T672
Test name
Test status
Simulation time 29837539464 ps
CPU time 18.73 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:00:59 PM PDT 24
Peak memory 201692 kb
Host smart-d9b7b6ec-bcfb-4e6e-81b9-c2a8e14793cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043480376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1043480376
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3340685761
Short name T645
Test name
Test status
Simulation time 3478382721 ps
CPU time 8.53 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:00:48 PM PDT 24
Peak memory 201676 kb
Host smart-45d1f9c0-9c02-465a-82f6-f9238c5f21db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340685761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3340685761
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2821079194
Short name T753
Test name
Test status
Simulation time 5776617783 ps
CPU time 7.97 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:00:48 PM PDT 24
Peak memory 201720 kb
Host smart-134b2085-67f2-41a7-90c3-19f0bfd32e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821079194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2821079194
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.876782243
Short name T690
Test name
Test status
Simulation time 373645945235 ps
CPU time 110.51 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:02:30 PM PDT 24
Peak memory 201896 kb
Host smart-f9e4331f-5177-4b47-916f-286b0f1d9e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876782243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
876782243
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.713401611
Short name T68
Test name
Test status
Simulation time 62163325982 ps
CPU time 126.21 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:02:46 PM PDT 24
Peak memory 210892 kb
Host smart-6cf0f395-070d-4596-a20e-e2956e517d20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713401611 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.713401611
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.256587646
Short name T504
Test name
Test status
Simulation time 289077898 ps
CPU time 1.03 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:00:41 PM PDT 24
Peak memory 201632 kb
Host smart-65fb2f60-8dd5-4de0-afd6-ecf28e721eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256587646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.256587646
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2623750658
Short name T520
Test name
Test status
Simulation time 197766177763 ps
CPU time 71.13 seconds
Started Jul 04 07:00:38 PM PDT 24
Finished Jul 04 07:01:50 PM PDT 24
Peak memory 201928 kb
Host smart-910449da-cb73-43fb-a51b-6f2d2c036f4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623750658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2623750658
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1612463724
Short name T189
Test name
Test status
Simulation time 332228127165 ps
CPU time 182.92 seconds
Started Jul 04 07:00:40 PM PDT 24
Finished Jul 04 07:03:43 PM PDT 24
Peak memory 201892 kb
Host smart-0b0e8cca-17f2-4303-b24d-8e5f35e67eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612463724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1612463724
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4105404598
Short name T416
Test name
Test status
Simulation time 165983300166 ps
CPU time 187.96 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:03:47 PM PDT 24
Peak memory 201916 kb
Host smart-bd1acb4b-8f8d-4741-ac79-38d67aeffedb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105404598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4105404598
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.237537354
Short name T165
Test name
Test status
Simulation time 327659322698 ps
CPU time 110.55 seconds
Started Jul 04 07:00:43 PM PDT 24
Finished Jul 04 07:02:33 PM PDT 24
Peak memory 201988 kb
Host smart-69538d87-7b11-47cc-abe8-e814153a49cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237537354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.237537354
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3789277508
Short name T719
Test name
Test status
Simulation time 328335296249 ps
CPU time 805.44 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:14:06 PM PDT 24
Peak memory 201920 kb
Host smart-398c931c-d12e-41be-822a-f9398c4ecc5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789277508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3789277508
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2343696450
Short name T186
Test name
Test status
Simulation time 534953186023 ps
CPU time 339.8 seconds
Started Jul 04 07:00:41 PM PDT 24
Finished Jul 04 07:06:21 PM PDT 24
Peak memory 202000 kb
Host smart-3f8dc905-19fb-4957-9151-8e375e5fde85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343696450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2343696450
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2183994222
Short name T652
Test name
Test status
Simulation time 196266855164 ps
CPU time 156.96 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:03:16 PM PDT 24
Peak memory 201916 kb
Host smart-4709dc9d-dafe-4bf0-83da-395c1c965db3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183994222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2183994222
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3538135500
Short name T103
Test name
Test status
Simulation time 80837987696 ps
CPU time 318.24 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:05:58 PM PDT 24
Peak memory 202200 kb
Host smart-e4f59018-a803-4795-8759-04177a4c805d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538135500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3538135500
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2439435530
Short name T781
Test name
Test status
Simulation time 34076996429 ps
CPU time 80.67 seconds
Started Jul 04 07:00:42 PM PDT 24
Finished Jul 04 07:02:03 PM PDT 24
Peak memory 201740 kb
Host smart-dd6d1554-9a8b-4557-894e-93dd1d3591c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439435530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2439435530
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2827948296
Short name T364
Test name
Test status
Simulation time 3885471918 ps
CPU time 6.01 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:00:46 PM PDT 24
Peak memory 201736 kb
Host smart-356becc5-5dcb-42c7-aee6-ef44140861ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827948296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2827948296
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1417999190
Short name T383
Test name
Test status
Simulation time 5897952524 ps
CPU time 7.91 seconds
Started Jul 04 07:00:37 PM PDT 24
Finished Jul 04 07:00:45 PM PDT 24
Peak memory 201748 kb
Host smart-bad16527-9987-47b3-97a3-871715558510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417999190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1417999190
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1213761610
Short name T392
Test name
Test status
Simulation time 295332509 ps
CPU time 1.2 seconds
Started Jul 04 07:00:47 PM PDT 24
Finished Jul 04 07:00:48 PM PDT 24
Peak memory 201612 kb
Host smart-38041fd8-88fd-44d8-b8b1-6049bbbcbf0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213761610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1213761610
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2304296517
Short name T345
Test name
Test status
Simulation time 524046219250 ps
CPU time 200.43 seconds
Started Jul 04 07:00:48 PM PDT 24
Finished Jul 04 07:04:09 PM PDT 24
Peak memory 201916 kb
Host smart-80b5213e-cfa9-4078-9cf4-39050bf14b02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304296517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2304296517
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3279818806
Short name T255
Test name
Test status
Simulation time 163307482126 ps
CPU time 48.34 seconds
Started Jul 04 07:00:50 PM PDT 24
Finished Jul 04 07:01:39 PM PDT 24
Peak memory 201916 kb
Host smart-f721fd9c-9adf-4fee-b112-5bd3c5344420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279818806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3279818806
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1571054844
Short name T749
Test name
Test status
Simulation time 169846365647 ps
CPU time 41.6 seconds
Started Jul 04 07:00:51 PM PDT 24
Finished Jul 04 07:01:33 PM PDT 24
Peak memory 201908 kb
Host smart-84a1b85c-5256-4256-ae93-be677ec40f6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571054844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1571054844
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1818167972
Short name T741
Test name
Test status
Simulation time 166362484897 ps
CPU time 90.34 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:02:10 PM PDT 24
Peak memory 201980 kb
Host smart-52bf615f-0ee5-4084-981f-8f674cb54d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818167972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1818167972
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.220986585
Short name T94
Test name
Test status
Simulation time 501133097782 ps
CPU time 1127.48 seconds
Started Jul 04 07:00:45 PM PDT 24
Finished Jul 04 07:19:33 PM PDT 24
Peak memory 201932 kb
Host smart-64aacadb-648f-4949-bc2f-1b6a9abd1dec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=220986585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.220986585
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4050642535
Short name T259
Test name
Test status
Simulation time 173152480727 ps
CPU time 108.42 seconds
Started Jul 04 07:00:51 PM PDT 24
Finished Jul 04 07:02:40 PM PDT 24
Peak memory 201932 kb
Host smart-b9d66a41-b4ef-497a-b508-4bcbffa67fdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050642535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4050642535
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.266193404
Short name T178
Test name
Test status
Simulation time 584837891937 ps
CPU time 1303.78 seconds
Started Jul 04 07:00:48 PM PDT 24
Finished Jul 04 07:22:32 PM PDT 24
Peak memory 201916 kb
Host smart-d0fd8cb2-937c-461f-bfe8-80e36b15550c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266193404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.266193404
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.281873229
Short name T475
Test name
Test status
Simulation time 100182617766 ps
CPU time 564.28 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:10:10 PM PDT 24
Peak memory 202232 kb
Host smart-cf238dea-e539-4f5d-8406-423098280c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281873229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.281873229
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4232763916
Short name T36
Test name
Test status
Simulation time 35246541829 ps
CPU time 75.79 seconds
Started Jul 04 07:00:45 PM PDT 24
Finished Jul 04 07:02:01 PM PDT 24
Peak memory 201720 kb
Host smart-f53a1a86-324b-4fbe-8658-47328960c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232763916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4232763916
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2270220831
Short name T609
Test name
Test status
Simulation time 4680332303 ps
CPU time 6.53 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:00:54 PM PDT 24
Peak memory 201728 kb
Host smart-b5560d0d-6207-4e3d-8799-1121dd71fad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270220831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2270220831
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.674555838
Short name T447
Test name
Test status
Simulation time 5648032705 ps
CPU time 6.94 seconds
Started Jul 04 07:00:39 PM PDT 24
Finished Jul 04 07:00:47 PM PDT 24
Peak memory 201744 kb
Host smart-1a316a0b-85db-488b-8583-388742c5fcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674555838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.674555838
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2135538222
Short name T247
Test name
Test status
Simulation time 654225743137 ps
CPU time 1364.2 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:23:31 PM PDT 24
Peak memory 201912 kb
Host smart-75864083-467e-49d2-b070-d8b6188f8cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135538222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2135538222
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1597291102
Short name T97
Test name
Test status
Simulation time 393981119806 ps
CPU time 531.58 seconds
Started Jul 04 07:00:45 PM PDT 24
Finished Jul 04 07:09:37 PM PDT 24
Peak memory 210532 kb
Host smart-e4cbf10c-58e5-4806-8b21-bd6b8dd1f465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597291102 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1597291102
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1584537831
Short name T669
Test name
Test status
Simulation time 356642540 ps
CPU time 0.81 seconds
Started Jul 04 07:00:51 PM PDT 24
Finished Jul 04 07:00:52 PM PDT 24
Peak memory 201660 kb
Host smart-847d1d4d-ced3-48d3-8949-c5fbb5c4a2ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584537831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1584537831
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.681270400
Short name T626
Test name
Test status
Simulation time 181741681974 ps
CPU time 259.92 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:05:06 PM PDT 24
Peak memory 201992 kb
Host smart-689f90ec-c27c-4217-aff8-7b796d306deb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681270400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.681270400
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3385587474
Short name T331
Test name
Test status
Simulation time 182988545598 ps
CPU time 426.26 seconds
Started Jul 04 07:00:49 PM PDT 24
Finished Jul 04 07:07:55 PM PDT 24
Peak memory 201900 kb
Host smart-563ab469-276b-46eb-b4e5-8231095e647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385587474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3385587474
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1490602060
Short name T90
Test name
Test status
Simulation time 484617742806 ps
CPU time 583.94 seconds
Started Jul 04 07:00:50 PM PDT 24
Finished Jul 04 07:10:35 PM PDT 24
Peak memory 201908 kb
Host smart-d668fa7a-a0e0-4e82-bcf2-c10b6a2aa0b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490602060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1490602060
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.755531197
Short name T241
Test name
Test status
Simulation time 330866002947 ps
CPU time 776.31 seconds
Started Jul 04 07:00:45 PM PDT 24
Finished Jul 04 07:13:42 PM PDT 24
Peak memory 201860 kb
Host smart-5703a982-7139-4b16-a12a-948431fb7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755531197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.755531197
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2049205148
Short name T400
Test name
Test status
Simulation time 489788899891 ps
CPU time 159.45 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:03:25 PM PDT 24
Peak memory 201864 kb
Host smart-0ed8f40a-a575-4873-aa86-a208f49b7172
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049205148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2049205148
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.407804022
Short name T253
Test name
Test status
Simulation time 549388540215 ps
CPU time 649.92 seconds
Started Jul 04 07:00:49 PM PDT 24
Finished Jul 04 07:11:39 PM PDT 24
Peak memory 201916 kb
Host smart-135430cc-220f-4132-9747-3c86457761af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407804022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.407804022
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1296089705
Short name T562
Test name
Test status
Simulation time 621150765982 ps
CPU time 237.67 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:04:44 PM PDT 24
Peak memory 201892 kb
Host smart-36513a97-dc85-4ac4-90d9-36368457e729
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296089705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1296089705
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3592714227
Short name T372
Test name
Test status
Simulation time 23466480176 ps
CPU time 54.41 seconds
Started Jul 04 07:00:47 PM PDT 24
Finished Jul 04 07:01:42 PM PDT 24
Peak memory 201724 kb
Host smart-eb0dfe3e-5239-44a4-b8d8-2e01a4a6a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592714227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3592714227
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2983409654
Short name T541
Test name
Test status
Simulation time 4307093085 ps
CPU time 4 seconds
Started Jul 04 07:00:49 PM PDT 24
Finished Jul 04 07:00:53 PM PDT 24
Peak memory 201720 kb
Host smart-6c32e1f2-d220-416b-954c-0bd88e76ea4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983409654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2983409654
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.672211696
Short name T734
Test name
Test status
Simulation time 5657888598 ps
CPU time 13.62 seconds
Started Jul 04 07:00:47 PM PDT 24
Finished Jul 04 07:01:01 PM PDT 24
Peak memory 201708 kb
Host smart-ddd1105b-f67b-4724-bbc1-4239fa83223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672211696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.672211696
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2484080583
Short name T630
Test name
Test status
Simulation time 367588777384 ps
CPU time 883.83 seconds
Started Jul 04 07:00:46 PM PDT 24
Finished Jul 04 07:15:30 PM PDT 24
Peak memory 201936 kb
Host smart-f5550dff-a252-45cb-884a-7be452da5a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484080583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2484080583
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3040337540
Short name T451
Test name
Test status
Simulation time 30840815350 ps
CPU time 38.51 seconds
Started Jul 04 07:00:45 PM PDT 24
Finished Jul 04 07:01:23 PM PDT 24
Peak memory 210248 kb
Host smart-e86259a8-9610-4c06-934a-bca02d50259f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040337540 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3040337540
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.4141606993
Short name T565
Test name
Test status
Simulation time 516681347 ps
CPU time 1.71 seconds
Started Jul 04 07:01:01 PM PDT 24
Finished Jul 04 07:01:03 PM PDT 24
Peak memory 201608 kb
Host smart-3830d8ec-042c-440f-9b44-52d5aa2de8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141606993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4141606993
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2259184589
Short name T336
Test name
Test status
Simulation time 368303915806 ps
CPU time 206.13 seconds
Started Jul 04 07:00:58 PM PDT 24
Finished Jul 04 07:04:24 PM PDT 24
Peak memory 201932 kb
Host smart-611e3246-6a27-49ad-834c-395212b52a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259184589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2259184589
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4050436665
Short name T309
Test name
Test status
Simulation time 497429116240 ps
CPU time 529.16 seconds
Started Jul 04 07:00:50 PM PDT 24
Finished Jul 04 07:09:40 PM PDT 24
Peak memory 201904 kb
Host smart-60fd35e8-b501-4f1d-835d-9b85135a5ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050436665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4050436665
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2264105826
Short name T689
Test name
Test status
Simulation time 492576149088 ps
CPU time 1016.84 seconds
Started Jul 04 07:00:52 PM PDT 24
Finished Jul 04 07:17:50 PM PDT 24
Peak memory 201880 kb
Host smart-1f869755-1032-4dff-b2b7-a3bd10141e33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264105826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2264105826
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1306990827
Short name T175
Test name
Test status
Simulation time 164728751609 ps
CPU time 312.69 seconds
Started Jul 04 07:00:52 PM PDT 24
Finished Jul 04 07:06:04 PM PDT 24
Peak memory 201976 kb
Host smart-92db5b8d-ae7a-4a8e-a0a4-4ec0e298786f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306990827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1306990827
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3041891366
Short name T407
Test name
Test status
Simulation time 490100349865 ps
CPU time 1067.39 seconds
Started Jul 04 07:00:52 PM PDT 24
Finished Jul 04 07:18:40 PM PDT 24
Peak memory 201916 kb
Host smart-b3727d7f-5a3a-4578-9824-fb9b8aea8b5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041891366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3041891366
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3483375705
Short name T733
Test name
Test status
Simulation time 195464091389 ps
CPU time 431.3 seconds
Started Jul 04 07:00:51 PM PDT 24
Finished Jul 04 07:08:02 PM PDT 24
Peak memory 201948 kb
Host smart-ccae65c6-379a-408d-8cfc-1c61b1ec42a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483375705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3483375705
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4278482174
Short name T773
Test name
Test status
Simulation time 196346758807 ps
CPU time 46.19 seconds
Started Jul 04 07:00:50 PM PDT 24
Finished Jul 04 07:01:37 PM PDT 24
Peak memory 201920 kb
Host smart-926eeab9-b26e-4865-8c4a-d46cca109f70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278482174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4278482174
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3322121638
Short name T59
Test name
Test status
Simulation time 76990207069 ps
CPU time 417.71 seconds
Started Jul 04 07:01:01 PM PDT 24
Finished Jul 04 07:07:59 PM PDT 24
Peak memory 202260 kb
Host smart-60400b4b-49fe-4129-ae9f-5021a55a9573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322121638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3322121638
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.957594097
Short name T674
Test name
Test status
Simulation time 30807087168 ps
CPU time 7.35 seconds
Started Jul 04 07:01:02 PM PDT 24
Finished Jul 04 07:01:09 PM PDT 24
Peak memory 201708 kb
Host smart-4ba93dbf-47de-4ab7-b353-96f003f2eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957594097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.957594097
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1946437794
Short name T580
Test name
Test status
Simulation time 4426297564 ps
CPU time 1.51 seconds
Started Jul 04 07:00:59 PM PDT 24
Finished Jul 04 07:01:01 PM PDT 24
Peak memory 201704 kb
Host smart-969946ee-6690-4232-aaf9-834d322e2a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946437794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1946437794
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.254674941
Short name T704
Test name
Test status
Simulation time 5973853672 ps
CPU time 12.05 seconds
Started Jul 04 07:00:50 PM PDT 24
Finished Jul 04 07:01:02 PM PDT 24
Peak memory 201736 kb
Host smart-c58b46b6-3c1b-42cb-8786-b3dcd7a7e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254674941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.254674941
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2103001291
Short name T350
Test name
Test status
Simulation time 495424448192 ps
CPU time 307.18 seconds
Started Jul 04 07:00:59 PM PDT 24
Finished Jul 04 07:06:07 PM PDT 24
Peak memory 201932 kb
Host smart-e9b60231-a67c-42f4-8275-d669b2d9cc49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103001291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2103001291
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.109375120
Short name T34
Test name
Test status
Simulation time 18585701539 ps
CPU time 18.08 seconds
Started Jul 04 07:01:02 PM PDT 24
Finished Jul 04 07:01:20 PM PDT 24
Peak memory 210576 kb
Host smart-00714991-f78f-4f3e-a409-324ec95b29dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109375120 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.109375120
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1598633847
Short name T737
Test name
Test status
Simulation time 470693197 ps
CPU time 0.88 seconds
Started Jul 04 07:01:12 PM PDT 24
Finished Jul 04 07:01:13 PM PDT 24
Peak memory 201660 kb
Host smart-1da6d31c-6d86-43da-ad78-ec3b09f60c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598633847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1598633847
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1908044597
Short name T551
Test name
Test status
Simulation time 171438754610 ps
CPU time 66.37 seconds
Started Jul 04 07:01:06 PM PDT 24
Finished Jul 04 07:02:12 PM PDT 24
Peak memory 201932 kb
Host smart-67894f94-b402-4019-8390-03330b5d7c45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908044597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1908044597
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2046498064
Short name T523
Test name
Test status
Simulation time 166425623606 ps
CPU time 343.14 seconds
Started Jul 04 07:01:06 PM PDT 24
Finished Jul 04 07:06:49 PM PDT 24
Peak memory 201888 kb
Host smart-06e9b69d-e0d1-4731-bb06-35700628893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046498064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2046498064
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1649295675
Short name T769
Test name
Test status
Simulation time 491693761372 ps
CPU time 1017.67 seconds
Started Jul 04 07:01:05 PM PDT 24
Finished Jul 04 07:18:03 PM PDT 24
Peak memory 201972 kb
Host smart-2406b612-3f21-43d3-a0bf-e27e36f0b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649295675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1649295675
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.717351380
Short name T496
Test name
Test status
Simulation time 322875691676 ps
CPU time 200.8 seconds
Started Jul 04 07:01:05 PM PDT 24
Finished Jul 04 07:04:26 PM PDT 24
Peak memory 201876 kb
Host smart-004023e7-d7fe-4054-8f1f-fae9d9012bfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=717351380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.717351380
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3370148169
Short name T723
Test name
Test status
Simulation time 157327263939 ps
CPU time 83.95 seconds
Started Jul 04 07:01:07 PM PDT 24
Finished Jul 04 07:02:31 PM PDT 24
Peak memory 201940 kb
Host smart-596977e2-9bd1-488a-9f12-99ffb6f2bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370148169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3370148169
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1053162305
Short name T463
Test name
Test status
Simulation time 322895091096 ps
CPU time 159.87 seconds
Started Jul 04 07:01:03 PM PDT 24
Finished Jul 04 07:03:43 PM PDT 24
Peak memory 201852 kb
Host smart-72ed39d9-ee03-4203-bdf8-acd53d946b31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053162305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1053162305
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2014672692
Short name T295
Test name
Test status
Simulation time 558478888735 ps
CPU time 1313.64 seconds
Started Jul 04 07:01:08 PM PDT 24
Finished Jul 04 07:23:02 PM PDT 24
Peak memory 201960 kb
Host smart-b0560ec1-a5c8-48fb-a42e-668cc46a57da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014672692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2014672692
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2295897847
Short name T213
Test name
Test status
Simulation time 587844908649 ps
CPU time 331.05 seconds
Started Jul 04 07:01:05 PM PDT 24
Finished Jul 04 07:06:36 PM PDT 24
Peak memory 201908 kb
Host smart-75d302af-0f58-43ed-9877-5cd9b7b81380
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295897847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2295897847
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.843265462
Short name T355
Test name
Test status
Simulation time 91496027722 ps
CPU time 457.76 seconds
Started Jul 04 07:01:08 PM PDT 24
Finished Jul 04 07:08:46 PM PDT 24
Peak memory 202200 kb
Host smart-e6346ddc-20df-4ede-ad7a-dde09fae5d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843265462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.843265462
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3514509611
Short name T559
Test name
Test status
Simulation time 35357909853 ps
CPU time 84.86 seconds
Started Jul 04 07:01:06 PM PDT 24
Finished Jul 04 07:02:31 PM PDT 24
Peak memory 201728 kb
Host smart-7ba1ef7a-b451-4fc0-8d91-1d71be8abf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514509611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3514509611
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2273606463
Short name T425
Test name
Test status
Simulation time 4683348652 ps
CPU time 2.3 seconds
Started Jul 04 07:01:11 PM PDT 24
Finished Jul 04 07:01:14 PM PDT 24
Peak memory 201684 kb
Host smart-fdeedf91-0a92-4e58-9619-70267c110233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273606463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2273606463
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.570761903
Short name T663
Test name
Test status
Simulation time 5756624325 ps
CPU time 2.02 seconds
Started Jul 04 07:01:02 PM PDT 24
Finished Jul 04 07:01:04 PM PDT 24
Peak memory 201724 kb
Host smart-b9f977d8-4069-4e4a-9fca-f035b318c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570761903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.570761903
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.278948917
Short name T622
Test name
Test status
Simulation time 353457852717 ps
CPU time 53.64 seconds
Started Jul 04 07:01:11 PM PDT 24
Finished Jul 04 07:02:05 PM PDT 24
Peak memory 201900 kb
Host smart-5ac8c504-7101-4b30-a3ba-67e9ffa32993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278948917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
278948917
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2543787230
Short name T724
Test name
Test status
Simulation time 25989534037 ps
CPU time 94.78 seconds
Started Jul 04 07:01:12 PM PDT 24
Finished Jul 04 07:02:47 PM PDT 24
Peak memory 210568 kb
Host smart-9c84d848-071d-4b5b-91f5-054336094e65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543787230 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2543787230
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3038729214
Short name T787
Test name
Test status
Simulation time 384433131 ps
CPU time 1.52 seconds
Started Jul 04 07:01:18 PM PDT 24
Finished Jul 04 07:01:20 PM PDT 24
Peak memory 201668 kb
Host smart-3958c9be-36f2-401e-97e5-6d7b7b3cceda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038729214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3038729214
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.790483222
Short name T343
Test name
Test status
Simulation time 547581819583 ps
CPU time 288.15 seconds
Started Jul 04 07:01:12 PM PDT 24
Finished Jul 04 07:06:00 PM PDT 24
Peak memory 201908 kb
Host smart-d0abf28c-d8d6-494f-aeb4-cd3fa0b98975
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790483222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.790483222
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1848220652
Short name T738
Test name
Test status
Simulation time 163139923313 ps
CPU time 99.42 seconds
Started Jul 04 07:01:14 PM PDT 24
Finished Jul 04 07:02:54 PM PDT 24
Peak memory 201840 kb
Host smart-9429fea1-1a1d-403c-bb9d-d8e1e9e9108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848220652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1848220652
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1676168275
Short name T145
Test name
Test status
Simulation time 329234776939 ps
CPU time 153.77 seconds
Started Jul 04 07:01:11 PM PDT 24
Finished Jul 04 07:03:45 PM PDT 24
Peak memory 201924 kb
Host smart-b8e8ee5a-0535-4182-b3f1-b393bbe9d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676168275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1676168275
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2471256748
Short name T146
Test name
Test status
Simulation time 325210932637 ps
CPU time 794.43 seconds
Started Jul 04 07:01:12 PM PDT 24
Finished Jul 04 07:14:27 PM PDT 24
Peak memory 201944 kb
Host smart-c3a60dc9-aac9-459d-ac17-c676513327c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471256748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2471256748
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3466421442
Short name T705
Test name
Test status
Simulation time 504109321350 ps
CPU time 164.06 seconds
Started Jul 04 07:01:13 PM PDT 24
Finished Jul 04 07:03:58 PM PDT 24
Peak memory 201956 kb
Host smart-10157611-a56a-4214-827a-569beb475ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466421442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3466421442
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4192655120
Short name T444
Test name
Test status
Simulation time 333404602000 ps
CPU time 192.96 seconds
Started Jul 04 07:01:14 PM PDT 24
Finished Jul 04 07:04:27 PM PDT 24
Peak memory 201904 kb
Host smart-c6ef7366-e6ad-4221-906c-6811b375e58f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192655120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4192655120
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3729320229
Short name T250
Test name
Test status
Simulation time 168950097261 ps
CPU time 172.48 seconds
Started Jul 04 07:01:12 PM PDT 24
Finished Jul 04 07:04:05 PM PDT 24
Peak memory 201980 kb
Host smart-ac725626-1798-46f2-8b67-a314c8edba22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729320229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3729320229
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1096933679
Short name T628
Test name
Test status
Simulation time 196185663766 ps
CPU time 120.77 seconds
Started Jul 04 07:01:12 PM PDT 24
Finished Jul 04 07:03:13 PM PDT 24
Peak memory 201884 kb
Host smart-33078097-d165-403d-877a-0095ab473bd0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096933679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1096933679
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1758346333
Short name T446
Test name
Test status
Simulation time 78821373336 ps
CPU time 307.15 seconds
Started Jul 04 07:01:19 PM PDT 24
Finished Jul 04 07:06:26 PM PDT 24
Peak memory 202212 kb
Host smart-fb978554-f23d-4093-85e8-acb71df565a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758346333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1758346333
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1025076780
Short name T539
Test name
Test status
Simulation time 34280984856 ps
CPU time 74.53 seconds
Started Jul 04 07:01:18 PM PDT 24
Finished Jul 04 07:02:32 PM PDT 24
Peak memory 201708 kb
Host smart-48b166e7-2a8d-4373-9d57-4a32b829603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025076780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1025076780
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2889013646
Short name T457
Test name
Test status
Simulation time 3636513928 ps
CPU time 4.19 seconds
Started Jul 04 07:01:13 PM PDT 24
Finished Jul 04 07:01:17 PM PDT 24
Peak memory 201728 kb
Host smart-f855ef05-f991-41bb-a7fa-ebb8d63cb1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889013646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2889013646
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1070760623
Short name T703
Test name
Test status
Simulation time 5637336735 ps
CPU time 6.83 seconds
Started Jul 04 07:01:13 PM PDT 24
Finished Jul 04 07:01:20 PM PDT 24
Peak memory 201660 kb
Host smart-8679acbe-07f8-47dd-9ea0-e227555a12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070760623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1070760623
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3660289708
Short name T222
Test name
Test status
Simulation time 611994372546 ps
CPU time 552.28 seconds
Started Jul 04 07:01:23 PM PDT 24
Finished Jul 04 07:10:35 PM PDT 24
Peak memory 218656 kb
Host smart-ebaec185-095a-4d04-bb7c-734b283f931c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660289708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3660289708
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3833541876
Short name T534
Test name
Test status
Simulation time 344670903 ps
CPU time 0.8 seconds
Started Jul 04 07:01:26 PM PDT 24
Finished Jul 04 07:01:27 PM PDT 24
Peak memory 201676 kb
Host smart-1359f01b-c54c-4e50-9a0c-5178258ba391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833541876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3833541876
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.190716666
Short name T527
Test name
Test status
Simulation time 500755434145 ps
CPU time 197.87 seconds
Started Jul 04 07:01:26 PM PDT 24
Finished Jul 04 07:04:44 PM PDT 24
Peak memory 201904 kb
Host smart-77867e70-9522-4642-9bcc-c39bb5e95547
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190716666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.190716666
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.736996023
Short name T503
Test name
Test status
Simulation time 349652313972 ps
CPU time 427.65 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:08:36 PM PDT 24
Peak memory 201924 kb
Host smart-6b4f49dc-3c4b-4b31-ae53-ec4821d6e483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736996023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.736996023
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4108007401
Short name T507
Test name
Test status
Simulation time 327162821750 ps
CPU time 282.19 seconds
Started Jul 04 07:01:19 PM PDT 24
Finished Jul 04 07:06:01 PM PDT 24
Peak memory 202000 kb
Host smart-7357d908-1d91-4da5-85eb-a834203ded79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108007401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4108007401
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4198911489
Short name T656
Test name
Test status
Simulation time 490365531719 ps
CPU time 549.94 seconds
Started Jul 04 07:01:18 PM PDT 24
Finished Jul 04 07:10:29 PM PDT 24
Peak memory 201968 kb
Host smart-f5911f79-8714-4302-9484-8bdb39e1b8e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198911489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4198911489
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1748350243
Short name T682
Test name
Test status
Simulation time 161095852448 ps
CPU time 59.93 seconds
Started Jul 04 07:01:19 PM PDT 24
Finished Jul 04 07:02:19 PM PDT 24
Peak memory 201936 kb
Host smart-1d9e2ac1-27ea-473e-8477-7dab399f6454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748350243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1748350243
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1413044481
Short name T579
Test name
Test status
Simulation time 488034673173 ps
CPU time 537.95 seconds
Started Jul 04 07:01:18 PM PDT 24
Finished Jul 04 07:10:16 PM PDT 24
Peak memory 201984 kb
Host smart-00812654-0292-4d1f-8fb7-6b556a05ee69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413044481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1413044481
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3384085348
Short name T602
Test name
Test status
Simulation time 362796650571 ps
CPU time 808.92 seconds
Started Jul 04 07:01:27 PM PDT 24
Finished Jul 04 07:14:56 PM PDT 24
Peak memory 201980 kb
Host smart-16050539-7162-43c3-a26e-a96fb76cad1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384085348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3384085348
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.380830020
Short name T792
Test name
Test status
Simulation time 212772944131 ps
CPU time 412.11 seconds
Started Jul 04 07:01:26 PM PDT 24
Finished Jul 04 07:08:19 PM PDT 24
Peak memory 201896 kb
Host smart-44559f74-1f1b-4f8a-900b-29ba405004d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380830020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.380830020
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.899420297
Short name T776
Test name
Test status
Simulation time 121239165299 ps
CPU time 590.81 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:11:19 PM PDT 24
Peak memory 202232 kb
Host smart-ba2ad4c0-4bab-4924-80c0-eff8da413c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899420297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.899420297
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1827173558
Short name T56
Test name
Test status
Simulation time 43288730846 ps
CPU time 101.86 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:03:10 PM PDT 24
Peak memory 201684 kb
Host smart-b0469506-95a2-45a5-bd5e-ae7e3211517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827173558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1827173558
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1331434022
Short name T646
Test name
Test status
Simulation time 3678930737 ps
CPU time 9.72 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:01:37 PM PDT 24
Peak memory 201716 kb
Host smart-9e0496c5-35da-4c2c-ac3c-af1896b9a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331434022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1331434022
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1927778657
Short name T180
Test name
Test status
Simulation time 5778504354 ps
CPU time 7.44 seconds
Started Jul 04 07:01:17 PM PDT 24
Finished Jul 04 07:01:25 PM PDT 24
Peak memory 201744 kb
Host smart-ce8b68eb-a440-4ee1-8ef3-363566be13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927778657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1927778657
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2971656791
Short name T469
Test name
Test status
Simulation time 453519873445 ps
CPU time 568.62 seconds
Started Jul 04 07:01:26 PM PDT 24
Finished Jul 04 07:10:55 PM PDT 24
Peak memory 202228 kb
Host smart-94b8200b-e175-4408-9349-55450ef064b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971656791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2971656791
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3254713261
Short name T613
Test name
Test status
Simulation time 435327225 ps
CPU time 0.95 seconds
Started Jul 04 07:01:37 PM PDT 24
Finished Jul 04 07:01:38 PM PDT 24
Peak memory 201640 kb
Host smart-0a5a2e6d-0b3a-4822-8729-2c2f5a0433d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254713261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3254713261
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2086423101
Short name T757
Test name
Test status
Simulation time 352480979497 ps
CPU time 710.14 seconds
Started Jul 04 07:01:37 PM PDT 24
Finished Jul 04 07:13:27 PM PDT 24
Peak memory 201908 kb
Host smart-0f36052b-ba80-4c51-9aee-9544fbde87db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086423101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2086423101
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4111970618
Short name T287
Test name
Test status
Simulation time 161905951801 ps
CPU time 241.8 seconds
Started Jul 04 07:01:37 PM PDT 24
Finished Jul 04 07:05:39 PM PDT 24
Peak memory 201900 kb
Host smart-6f426d2a-66e8-402f-be9f-1fb002e506cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111970618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4111970618
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.827180891
Short name T328
Test name
Test status
Simulation time 164169313168 ps
CPU time 100.86 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:03:09 PM PDT 24
Peak memory 201924 kb
Host smart-46285511-09f1-4610-b5d2-d19fecdba7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827180891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.827180891
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1831407049
Short name T632
Test name
Test status
Simulation time 169251393330 ps
CPU time 371.86 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:07:40 PM PDT 24
Peak memory 201912 kb
Host smart-9b8ca7fa-9539-4b0b-b9e0-02a637fea83b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831407049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1831407049
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1377821315
Short name T136
Test name
Test status
Simulation time 323068372597 ps
CPU time 633.26 seconds
Started Jul 04 07:01:26 PM PDT 24
Finished Jul 04 07:11:59 PM PDT 24
Peak memory 201908 kb
Host smart-5dc12bd0-9dd6-4bb6-9b7d-df436dbbf3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377821315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1377821315
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.808465937
Short name T2
Test name
Test status
Simulation time 496746134690 ps
CPU time 1172.34 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:21:01 PM PDT 24
Peak memory 201880 kb
Host smart-b9d8fd76-1aa4-4b65-b14d-e07bec50e26e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=808465937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.808465937
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1992859186
Short name T273
Test name
Test status
Simulation time 192622289280 ps
CPU time 427.94 seconds
Started Jul 04 07:01:38 PM PDT 24
Finished Jul 04 07:08:46 PM PDT 24
Peak memory 201936 kb
Host smart-018417bb-ea00-4d8d-9962-f7274dae4047
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992859186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1992859186
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.224813777
Short name T665
Test name
Test status
Simulation time 215117396423 ps
CPU time 249.61 seconds
Started Jul 04 07:01:38 PM PDT 24
Finished Jul 04 07:05:47 PM PDT 24
Peak memory 201896 kb
Host smart-11ba8d15-d01f-4595-acd5-356e3dd0f9ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224813777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.224813777
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1932764931
Short name T357
Test name
Test status
Simulation time 99248333509 ps
CPU time 325.1 seconds
Started Jul 04 07:01:36 PM PDT 24
Finished Jul 04 07:07:02 PM PDT 24
Peak memory 202228 kb
Host smart-c3de22ee-7eaf-4fc5-add5-2530150cd01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932764931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1932764931
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2610501350
Short name T681
Test name
Test status
Simulation time 35172835833 ps
CPU time 5.29 seconds
Started Jul 04 07:01:38 PM PDT 24
Finished Jul 04 07:01:43 PM PDT 24
Peak memory 201716 kb
Host smart-4e6dbbfa-f5c2-44d5-9acc-e6159e72cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610501350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2610501350
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3355968016
Short name T590
Test name
Test status
Simulation time 3336572395 ps
CPU time 2.52 seconds
Started Jul 04 07:01:37 PM PDT 24
Finished Jul 04 07:01:40 PM PDT 24
Peak memory 201716 kb
Host smart-0c667dfc-5090-4f7e-b1a3-f7a9805be05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355968016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3355968016
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2098314589
Short name T403
Test name
Test status
Simulation time 5893043015 ps
CPU time 3.91 seconds
Started Jul 04 07:01:28 PM PDT 24
Finished Jul 04 07:01:32 PM PDT 24
Peak memory 201716 kb
Host smart-c08f9221-868b-4f5e-9567-6846e77d21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098314589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2098314589
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.157989647
Short name T768
Test name
Test status
Simulation time 165242967563 ps
CPU time 333.44 seconds
Started Jul 04 07:01:37 PM PDT 24
Finished Jul 04 07:07:11 PM PDT 24
Peak memory 201844 kb
Host smart-0b8d55ae-269a-457e-ac80-a390ef74c9a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157989647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
157989647
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3203393462
Short name T23
Test name
Test status
Simulation time 69894097905 ps
CPU time 67.2 seconds
Started Jul 04 07:01:39 PM PDT 24
Finished Jul 04 07:02:46 PM PDT 24
Peak memory 210636 kb
Host smart-1adec607-5e3b-44f7-82a4-15d00e3edbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203393462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3203393462
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3089365454
Short name T725
Test name
Test status
Simulation time 416760361 ps
CPU time 1.52 seconds
Started Jul 04 07:00:11 PM PDT 24
Finished Jul 04 07:00:12 PM PDT 24
Peak memory 201656 kb
Host smart-4965ffee-b2fd-4e71-a0d2-58340b2f36db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089365454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3089365454
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1984468055
Short name T268
Test name
Test status
Simulation time 383773270088 ps
CPU time 178.51 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:03:07 PM PDT 24
Peak memory 201912 kb
Host smart-16a753f5-d6c2-46a3-8f7f-ac19d934135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984468055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1984468055
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3896566936
Short name T750
Test name
Test status
Simulation time 158652664501 ps
CPU time 44.01 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:51 PM PDT 24
Peak memory 201924 kb
Host smart-eaf13c21-7872-40f6-b762-88abe859c7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896566936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3896566936
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.4144034288
Short name T518
Test name
Test status
Simulation time 330807436111 ps
CPU time 90.12 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:01:40 PM PDT 24
Peak memory 201968 kb
Host smart-40c08111-f64c-483d-992b-2a0f924c6047
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144034288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.4144034288
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1936835930
Short name T686
Test name
Test status
Simulation time 331006656827 ps
CPU time 729.9 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:12:20 PM PDT 24
Peak memory 202004 kb
Host smart-aec5568d-ce7c-4759-ab92-5ec0891eb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936835930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1936835930
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.557038123
Short name T524
Test name
Test status
Simulation time 159621398261 ps
CPU time 93.23 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:01:42 PM PDT 24
Peak memory 201904 kb
Host smart-bbf30bd6-3277-461d-a8c7-bbf8eb541c2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=557038123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.557038123
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.256528482
Short name T291
Test name
Test status
Simulation time 339874358228 ps
CPU time 360.61 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:06:09 PM PDT 24
Peak memory 201868 kb
Host smart-56cf1d55-10c1-46fa-a67c-c5a0bbc8d190
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256528482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.256528482
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.978193878
Short name T767
Test name
Test status
Simulation time 400330512774 ps
CPU time 205.29 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:03:35 PM PDT 24
Peak memory 201908 kb
Host smart-7816cc81-9cba-467e-8eac-4337fe0cb729
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978193878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.978193878
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3063888245
Short name T716
Test name
Test status
Simulation time 132420763713 ps
CPU time 615.63 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:10:25 PM PDT 24
Peak memory 202216 kb
Host smart-848d3242-cc2b-4999-a79a-8106026b96f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063888245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3063888245
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2199767143
Short name T428
Test name
Test status
Simulation time 42813012211 ps
CPU time 47.99 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:00:58 PM PDT 24
Peak memory 201708 kb
Host smart-661208c6-46c7-42c3-a413-7e42ef55f2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199767143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2199767143
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.712173770
Short name T374
Test name
Test status
Simulation time 3646009915 ps
CPU time 8.87 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:16 PM PDT 24
Peak memory 201688 kb
Host smart-acc080d9-22b1-4bdb-904d-b2289eb952f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712173770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.712173770
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.435048441
Short name T71
Test name
Test status
Simulation time 7900868832 ps
CPU time 16.61 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:00:25 PM PDT 24
Peak memory 218244 kb
Host smart-e5549eee-6c0c-4086-85e3-f394da610c56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435048441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.435048441
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2757394748
Short name T515
Test name
Test status
Simulation time 5897643392 ps
CPU time 14.15 seconds
Started Jul 04 07:00:07 PM PDT 24
Finished Jul 04 07:00:22 PM PDT 24
Peak memory 201736 kb
Host smart-784d8228-aaef-4e37-9fbc-7193714afd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757394748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2757394748
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.751480313
Short name T188
Test name
Test status
Simulation time 326333568379 ps
CPU time 137.17 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:02:28 PM PDT 24
Peak memory 201916 kb
Host smart-ab4376ec-870f-4e4e-84f5-6b6046923678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751480313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.751480313
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3306493468
Short name T314
Test name
Test status
Simulation time 12941667911 ps
CPU time 43.49 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:00:53 PM PDT 24
Peak memory 210548 kb
Host smart-3907076a-f4b8-450c-82d8-17da56e317a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306493468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3306493468
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.265110676
Short name T368
Test name
Test status
Simulation time 371226857 ps
CPU time 0.84 seconds
Started Jul 04 07:01:50 PM PDT 24
Finished Jul 04 07:01:51 PM PDT 24
Peak memory 201648 kb
Host smart-a09ce57b-75c7-44f1-8889-cb67fd438990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265110676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.265110676
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.62025455
Short name T786
Test name
Test status
Simulation time 164236231585 ps
CPU time 5.14 seconds
Started Jul 04 07:01:42 PM PDT 24
Finished Jul 04 07:01:47 PM PDT 24
Peak memory 201900 kb
Host smart-6284fe07-3331-454f-898b-537bf5f1c9e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62025455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gatin
g.62025455
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.82549292
Short name T320
Test name
Test status
Simulation time 167756969522 ps
CPU time 389.44 seconds
Started Jul 04 07:01:44 PM PDT 24
Finished Jul 04 07:08:14 PM PDT 24
Peak memory 201912 kb
Host smart-0184fbec-2a35-4fb3-a216-2ac02ea19851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82549292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.82549292
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1644929782
Short name T439
Test name
Test status
Simulation time 492707236458 ps
CPU time 164.59 seconds
Started Jul 04 07:01:42 PM PDT 24
Finished Jul 04 07:04:26 PM PDT 24
Peak memory 201884 kb
Host smart-8c6178ac-e7ca-4ae3-a297-91cb756871e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644929782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1644929782
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1853620125
Short name T201
Test name
Test status
Simulation time 327525258646 ps
CPU time 179.16 seconds
Started Jul 04 07:01:42 PM PDT 24
Finished Jul 04 07:04:41 PM PDT 24
Peak memory 201988 kb
Host smart-e29573df-18c3-45c0-ba73-789b29832336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853620125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1853620125
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1717964360
Short name T577
Test name
Test status
Simulation time 327125701153 ps
CPU time 183.11 seconds
Started Jul 04 07:01:43 PM PDT 24
Finished Jul 04 07:04:46 PM PDT 24
Peak memory 201972 kb
Host smart-c9009c3d-35a6-4824-9e36-c6fbccf4bc7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717964360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1717964360
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.974623572
Short name T544
Test name
Test status
Simulation time 198650699324 ps
CPU time 101.6 seconds
Started Jul 04 07:01:43 PM PDT 24
Finished Jul 04 07:03:25 PM PDT 24
Peak memory 201892 kb
Host smart-294bc989-3611-46ba-9b58-cc55005bb53b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974623572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.974623572
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3181095430
Short name T228
Test name
Test status
Simulation time 107031270459 ps
CPU time 431.5 seconds
Started Jul 04 07:01:50 PM PDT 24
Finished Jul 04 07:09:02 PM PDT 24
Peak memory 202208 kb
Host smart-994ee2ed-2c79-4970-9f15-19017df64f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181095430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3181095430
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3801364390
Short name T514
Test name
Test status
Simulation time 42294289428 ps
CPU time 22.82 seconds
Started Jul 04 07:01:43 PM PDT 24
Finished Jul 04 07:02:06 PM PDT 24
Peak memory 201664 kb
Host smart-009e99a5-8677-422f-b20b-2d145ec41db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801364390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3801364390
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.580961521
Short name T198
Test name
Test status
Simulation time 3286278918 ps
CPU time 4.07 seconds
Started Jul 04 07:01:42 PM PDT 24
Finished Jul 04 07:01:46 PM PDT 24
Peak memory 201696 kb
Host smart-42511c02-89e4-47e9-ab7d-6b7a7121b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580961521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.580961521
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3397318103
Short name T493
Test name
Test status
Simulation time 5699148239 ps
CPU time 13.64 seconds
Started Jul 04 07:01:37 PM PDT 24
Finished Jul 04 07:01:51 PM PDT 24
Peak memory 201720 kb
Host smart-e1e1e674-26e8-4d8a-b01c-1a8c989d5bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397318103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3397318103
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3556073295
Short name T701
Test name
Test status
Simulation time 121209300900 ps
CPU time 81.36 seconds
Started Jul 04 07:01:56 PM PDT 24
Finished Jul 04 07:03:17 PM PDT 24
Peak memory 210248 kb
Host smart-04dbf36f-3c4e-4020-98c8-117f1af8cc02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556073295 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3556073295
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4131727473
Short name T713
Test name
Test status
Simulation time 345096276 ps
CPU time 0.8 seconds
Started Jul 04 07:02:12 PM PDT 24
Finished Jul 04 07:02:13 PM PDT 24
Peak memory 201664 kb
Host smart-3d121839-ebf7-4d2e-9eb3-25b7204b953a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131727473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4131727473
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2524243048
Short name T575
Test name
Test status
Simulation time 160992642702 ps
CPU time 218.89 seconds
Started Jul 04 07:02:03 PM PDT 24
Finished Jul 04 07:05:42 PM PDT 24
Peak memory 202000 kb
Host smart-c4bb2b28-3f7e-447e-8789-168b9a526b83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524243048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2524243048
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.295960171
Short name T687
Test name
Test status
Simulation time 318574800176 ps
CPU time 698.85 seconds
Started Jul 04 07:02:01 PM PDT 24
Finished Jul 04 07:13:40 PM PDT 24
Peak memory 201928 kb
Host smart-1b1966a4-e3f8-4512-98e6-025cbc63cdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295960171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.295960171
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4065465255
Short name T405
Test name
Test status
Simulation time 323774776880 ps
CPU time 669.94 seconds
Started Jul 04 07:01:59 PM PDT 24
Finished Jul 04 07:13:09 PM PDT 24
Peak memory 201928 kb
Host smart-1acb37fa-b1ad-45ba-b289-00ff1e873cd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065465255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4065465255
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1497754135
Short name T206
Test name
Test status
Simulation time 330193778603 ps
CPU time 185.72 seconds
Started Jul 04 07:01:57 PM PDT 24
Finished Jul 04 07:05:03 PM PDT 24
Peak memory 201920 kb
Host smart-56a0979e-51ec-49cd-ab04-8ba378e086fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497754135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1497754135
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3535041399
Short name T401
Test name
Test status
Simulation time 501094698697 ps
CPU time 532.39 seconds
Started Jul 04 07:01:57 PM PDT 24
Finished Jul 04 07:10:49 PM PDT 24
Peak memory 201912 kb
Host smart-e1775af4-64f4-482b-acb0-95804c940b2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535041399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3535041399
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2288221816
Short name T791
Test name
Test status
Simulation time 365964171702 ps
CPU time 785.61 seconds
Started Jul 04 07:01:56 PM PDT 24
Finished Jul 04 07:15:02 PM PDT 24
Peak memory 201908 kb
Host smart-8eec9e01-a778-41d6-9e65-19340a5b36b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288221816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2288221816
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1070038529
Short name T432
Test name
Test status
Simulation time 199979387004 ps
CPU time 104.56 seconds
Started Jul 04 07:02:02 PM PDT 24
Finished Jul 04 07:03:47 PM PDT 24
Peak memory 201916 kb
Host smart-ce998c8f-c92d-46ad-890b-020fe8088c50
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070038529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1070038529
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2475985858
Short name T483
Test name
Test status
Simulation time 43871143354 ps
CPU time 25.51 seconds
Started Jul 04 07:02:03 PM PDT 24
Finished Jul 04 07:02:29 PM PDT 24
Peak memory 201724 kb
Host smart-de099936-c132-4848-b8a9-de43c2a256c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475985858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2475985858
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1588040859
Short name T133
Test name
Test status
Simulation time 2950256364 ps
CPU time 2.4 seconds
Started Jul 04 07:02:04 PM PDT 24
Finished Jul 04 07:02:06 PM PDT 24
Peak memory 201716 kb
Host smart-b86f8c80-aa8e-4804-ac2a-001abeb81413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588040859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1588040859
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3831789127
Short name T375
Test name
Test status
Simulation time 5941729501 ps
CPU time 13.49 seconds
Started Jul 04 07:02:00 PM PDT 24
Finished Jul 04 07:02:13 PM PDT 24
Peak memory 201724 kb
Host smart-9872b873-8ff0-486c-9650-e55d84a45168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831789127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3831789127
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2362264860
Short name T639
Test name
Test status
Simulation time 97981102024 ps
CPU time 199.45 seconds
Started Jul 04 07:02:10 PM PDT 24
Finished Jul 04 07:05:30 PM PDT 24
Peak memory 201704 kb
Host smart-41217c7d-f471-4a5a-859a-0c55a219e850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362264860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2362264860
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3301549892
Short name T688
Test name
Test status
Simulation time 553210561 ps
CPU time 0.95 seconds
Started Jul 04 07:02:17 PM PDT 24
Finished Jul 04 07:02:18 PM PDT 24
Peak memory 201652 kb
Host smart-9d0742d3-d594-45ac-bcee-708070261fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301549892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3301549892
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2162026962
Short name T766
Test name
Test status
Simulation time 163858665005 ps
CPU time 349.74 seconds
Started Jul 04 07:02:23 PM PDT 24
Finished Jul 04 07:08:13 PM PDT 24
Peak memory 201988 kb
Host smart-841d1f97-319e-415b-b125-2be314b4c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162026962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2162026962
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3190694173
Short name T528
Test name
Test status
Simulation time 482466638749 ps
CPU time 1042.93 seconds
Started Jul 04 07:02:11 PM PDT 24
Finished Jul 04 07:19:34 PM PDT 24
Peak memory 201980 kb
Host smart-75ae2dc3-52c2-4a83-b666-e0cad4c6e849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190694173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3190694173
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3700114787
Short name T694
Test name
Test status
Simulation time 161345533086 ps
CPU time 87.56 seconds
Started Jul 04 07:02:19 PM PDT 24
Finished Jul 04 07:03:47 PM PDT 24
Peak memory 201888 kb
Host smart-33eb6a1a-b682-4ea9-92a8-1df385f85e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700114787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3700114787
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3835199554
Short name T698
Test name
Test status
Simulation time 484054895162 ps
CPU time 172.73 seconds
Started Jul 04 07:02:11 PM PDT 24
Finished Jul 04 07:05:04 PM PDT 24
Peak memory 201992 kb
Host smart-0a4f9cdb-5847-4a60-8664-dd637d7dd80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835199554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3835199554
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1245452857
Short name T586
Test name
Test status
Simulation time 327874009052 ps
CPU time 753.46 seconds
Started Jul 04 07:02:10 PM PDT 24
Finished Jul 04 07:14:44 PM PDT 24
Peak memory 201964 kb
Host smart-701cb641-d533-4ddc-b2c8-a4a612287698
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245452857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1245452857
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3666281470
Short name T784
Test name
Test status
Simulation time 611600272948 ps
CPU time 1254.56 seconds
Started Jul 04 07:02:18 PM PDT 24
Finished Jul 04 07:23:13 PM PDT 24
Peak memory 201908 kb
Host smart-73c51a7e-6e9a-47f9-bed0-817af8afc7c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666281470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3666281470
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1540783980
Short name T219
Test name
Test status
Simulation time 134806968919 ps
CPU time 515.4 seconds
Started Jul 04 07:02:22 PM PDT 24
Finished Jul 04 07:10:57 PM PDT 24
Peak memory 202284 kb
Host smart-ac24079e-810d-44aa-824b-84b302814c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540783980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1540783980
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3872746188
Short name T460
Test name
Test status
Simulation time 41195725440 ps
CPU time 18.53 seconds
Started Jul 04 07:02:18 PM PDT 24
Finished Jul 04 07:02:37 PM PDT 24
Peak memory 201728 kb
Host smart-71802cf2-81d3-4b75-bb34-5ad550ccf8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872746188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3872746188
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1869780771
Short name T404
Test name
Test status
Simulation time 2593991480 ps
CPU time 3.51 seconds
Started Jul 04 07:02:23 PM PDT 24
Finished Jul 04 07:02:27 PM PDT 24
Peak memory 201704 kb
Host smart-d7702ba9-a1ff-4ec4-9a07-fb1809ed2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869780771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1869780771
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3028394040
Short name T134
Test name
Test status
Simulation time 5726549124 ps
CPU time 7.58 seconds
Started Jul 04 07:02:12 PM PDT 24
Finished Jul 04 07:02:20 PM PDT 24
Peak memory 201728 kb
Host smart-c3faa373-0fd0-458a-a7d6-763cff5e75f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028394040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3028394040
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1173011341
Short name T573
Test name
Test status
Simulation time 49858159726 ps
CPU time 82.35 seconds
Started Jul 04 07:02:22 PM PDT 24
Finished Jul 04 07:03:44 PM PDT 24
Peak memory 218476 kb
Host smart-688c88b3-6e0d-4182-9408-47067e91ea6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173011341 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1173011341
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2412321308
Short name T676
Test name
Test status
Simulation time 426923579 ps
CPU time 0.87 seconds
Started Jul 04 07:02:33 PM PDT 24
Finished Jul 04 07:02:34 PM PDT 24
Peak memory 201656 kb
Host smart-3eb8c453-398f-439c-9742-6ded74b95067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412321308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2412321308
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2286414270
Short name T549
Test name
Test status
Simulation time 167742047053 ps
CPU time 87.33 seconds
Started Jul 04 07:02:24 PM PDT 24
Finished Jul 04 07:03:52 PM PDT 24
Peak memory 201896 kb
Host smart-53a5784e-c999-446d-9a65-2f8392c61cb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286414270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2286414270
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.951736423
Short name T499
Test name
Test status
Simulation time 495158240139 ps
CPU time 314.82 seconds
Started Jul 04 07:02:17 PM PDT 24
Finished Jul 04 07:07:32 PM PDT 24
Peak memory 201992 kb
Host smart-48e1b8e5-1bc9-43ed-af10-a174671ba325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951736423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.951736423
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2300249071
Short name T745
Test name
Test status
Simulation time 164556365351 ps
CPU time 121.22 seconds
Started Jul 04 07:02:24 PM PDT 24
Finished Jul 04 07:04:25 PM PDT 24
Peak memory 201888 kb
Host smart-26c021ef-a6f6-483c-a45b-484096ce2c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300249071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2300249071
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3602212141
Short name T230
Test name
Test status
Simulation time 490923100032 ps
CPU time 547.64 seconds
Started Jul 04 07:02:18 PM PDT 24
Finished Jul 04 07:11:26 PM PDT 24
Peak memory 201976 kb
Host smart-200b172a-4c9e-4d29-afe9-b8f720aff6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602212141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3602212141
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1158692752
Short name T437
Test name
Test status
Simulation time 163591872334 ps
CPU time 336.71 seconds
Started Jul 04 07:02:18 PM PDT 24
Finished Jul 04 07:07:54 PM PDT 24
Peak memory 201920 kb
Host smart-92c95811-39a9-464f-b984-15722d959a78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158692752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1158692752
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1959879896
Short name T289
Test name
Test status
Simulation time 389564746415 ps
CPU time 229.98 seconds
Started Jul 04 07:02:24 PM PDT 24
Finished Jul 04 07:06:14 PM PDT 24
Peak memory 201924 kb
Host smart-563e5ff0-3ef8-4efe-8fcc-5f72a93a4513
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959879896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1959879896
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3459762649
Short name T697
Test name
Test status
Simulation time 589012820536 ps
CPU time 324.5 seconds
Started Jul 04 07:02:25 PM PDT 24
Finished Jul 04 07:07:50 PM PDT 24
Peak memory 201892 kb
Host smart-85ef65cd-1127-4436-9cc8-a32e29d2bb96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459762649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3459762649
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.398669990
Short name T9
Test name
Test status
Simulation time 42075623192 ps
CPU time 44.55 seconds
Started Jul 04 07:02:24 PM PDT 24
Finished Jul 04 07:03:09 PM PDT 24
Peak memory 201716 kb
Host smart-1f4c5018-19d0-4fa8-851e-41545b350732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398669990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.398669990
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2326896043
Short name T478
Test name
Test status
Simulation time 3798905631 ps
CPU time 10.66 seconds
Started Jul 04 07:02:23 PM PDT 24
Finished Jul 04 07:02:33 PM PDT 24
Peak memory 201960 kb
Host smart-0b2f9b7f-0a7e-46cc-a35f-e4ef83038d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326896043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2326896043
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2124765069
Short name T625
Test name
Test status
Simulation time 5732633586 ps
CPU time 7.93 seconds
Started Jul 04 07:02:22 PM PDT 24
Finished Jul 04 07:02:30 PM PDT 24
Peak memory 201752 kb
Host smart-5d4e1c61-3910-4018-9bd7-073eba6b38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124765069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2124765069
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1998107242
Short name T262
Test name
Test status
Simulation time 183058286168 ps
CPU time 413.76 seconds
Started Jul 04 07:02:32 PM PDT 24
Finished Jul 04 07:09:26 PM PDT 24
Peak memory 201964 kb
Host smart-e05272e4-b7d1-4c6f-b4bf-8c891ddf09af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998107242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1998107242
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3804494324
Short name T48
Test name
Test status
Simulation time 368255873360 ps
CPU time 303.82 seconds
Started Jul 04 07:02:32 PM PDT 24
Finished Jul 04 07:07:36 PM PDT 24
Peak memory 218716 kb
Host smart-391d4226-87ba-4a05-b978-a38c90c05324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804494324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3804494324
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1922335682
Short name T79
Test name
Test status
Simulation time 392020196 ps
CPU time 1.04 seconds
Started Jul 04 07:02:45 PM PDT 24
Finished Jul 04 07:02:46 PM PDT 24
Peak memory 201648 kb
Host smart-8bc51cd9-726c-4389-b0fd-c1f760683766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922335682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1922335682
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.627203761
Short name T302
Test name
Test status
Simulation time 162447242373 ps
CPU time 361.24 seconds
Started Jul 04 07:02:37 PM PDT 24
Finished Jul 04 07:08:39 PM PDT 24
Peak memory 201904 kb
Host smart-91614a64-a91b-4e51-8bf5-dd60906a4420
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627203761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.627203761
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.867809700
Short name T621
Test name
Test status
Simulation time 369734353850 ps
CPU time 894.43 seconds
Started Jul 04 07:02:38 PM PDT 24
Finished Jul 04 07:17:33 PM PDT 24
Peak memory 201952 kb
Host smart-cf4b3259-e06d-481b-aae2-c335829781df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867809700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.867809700
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1296004611
Short name T170
Test name
Test status
Simulation time 343468774906 ps
CPU time 238.16 seconds
Started Jul 04 07:02:35 PM PDT 24
Finished Jul 04 07:06:34 PM PDT 24
Peak memory 201996 kb
Host smart-c529a4f8-8ee1-42d0-a737-8186a3ea74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296004611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1296004611
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.740165852
Short name T192
Test name
Test status
Simulation time 328192550844 ps
CPU time 694.35 seconds
Started Jul 04 07:02:37 PM PDT 24
Finished Jul 04 07:14:12 PM PDT 24
Peak memory 201860 kb
Host smart-ee2d37cb-e326-45b1-96e0-345ab3ad8e6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740165852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.740165852
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.397632948
Short name T161
Test name
Test status
Simulation time 496722052522 ps
CPU time 1112.9 seconds
Started Jul 04 07:02:31 PM PDT 24
Finished Jul 04 07:21:04 PM PDT 24
Peak memory 201936 kb
Host smart-5c7e6d2f-a924-44a4-82df-10da6d65fb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397632948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.397632948
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1571827662
Short name T770
Test name
Test status
Simulation time 488661172795 ps
CPU time 276.2 seconds
Started Jul 04 07:02:38 PM PDT 24
Finished Jul 04 07:07:15 PM PDT 24
Peak memory 201912 kb
Host smart-5aa6fc38-904e-4766-b34b-958f72cab4ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571827662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1571827662
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2266803683
Short name T89
Test name
Test status
Simulation time 210451452124 ps
CPU time 133.95 seconds
Started Jul 04 07:02:36 PM PDT 24
Finished Jul 04 07:04:50 PM PDT 24
Peak memory 201896 kb
Host smart-dcccc8b6-f906-447f-8525-15140454f530
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266803683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2266803683
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2159327243
Short name T402
Test name
Test status
Simulation time 27669823573 ps
CPU time 36.35 seconds
Started Jul 04 07:02:44 PM PDT 24
Finished Jul 04 07:03:21 PM PDT 24
Peak memory 201720 kb
Host smart-2af92eff-060c-47a5-9f63-8a67c7f2cc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159327243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2159327243
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.561287385
Short name T563
Test name
Test status
Simulation time 4210534522 ps
CPU time 10.68 seconds
Started Jul 04 07:02:36 PM PDT 24
Finished Jul 04 07:02:47 PM PDT 24
Peak memory 201688 kb
Host smart-380d1960-bd8a-4aff-a35d-ae05e03b7142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561287385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.561287385
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.540393425
Short name T506
Test name
Test status
Simulation time 5729764644 ps
CPU time 4.76 seconds
Started Jul 04 07:02:33 PM PDT 24
Finished Jul 04 07:02:37 PM PDT 24
Peak memory 201736 kb
Host smart-dac4e51a-b501-48a6-a733-810a6ced87d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540393425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.540393425
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2261324713
Short name T729
Test name
Test status
Simulation time 14961209802 ps
CPU time 34.83 seconds
Started Jul 04 07:02:46 PM PDT 24
Finished Jul 04 07:03:21 PM PDT 24
Peak memory 201708 kb
Host smart-68780303-c5d2-423c-9866-6c9fe1f5ab32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261324713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2261324713
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2477477629
Short name T793
Test name
Test status
Simulation time 35578064515 ps
CPU time 69.64 seconds
Started Jul 04 07:02:45 PM PDT 24
Finished Jul 04 07:03:55 PM PDT 24
Peak memory 210288 kb
Host smart-91caa13e-f5fb-4524-97d6-8f7ed0674a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477477629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2477477629
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1043684030
Short name T458
Test name
Test status
Simulation time 303268398 ps
CPU time 1.34 seconds
Started Jul 04 07:03:06 PM PDT 24
Finished Jul 04 07:03:08 PM PDT 24
Peak memory 201656 kb
Host smart-1226bcb8-08fb-4796-8320-02e8359a8ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043684030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1043684030
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3948734215
Short name T748
Test name
Test status
Simulation time 191130578877 ps
CPU time 221.66 seconds
Started Jul 04 07:03:04 PM PDT 24
Finished Jul 04 07:06:46 PM PDT 24
Peak memory 201840 kb
Host smart-048f3a31-ea3f-484f-a55b-7ce95183410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948734215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3948734215
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2338070765
Short name T617
Test name
Test status
Simulation time 317898824453 ps
CPU time 382.65 seconds
Started Jul 04 07:02:53 PM PDT 24
Finished Jul 04 07:09:16 PM PDT 24
Peak memory 201916 kb
Host smart-df2913f3-a07f-40f1-a276-e04ea685c8d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338070765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2338070765
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.228714541
Short name T505
Test name
Test status
Simulation time 487030910559 ps
CPU time 576.13 seconds
Started Jul 04 07:02:54 PM PDT 24
Finished Jul 04 07:12:30 PM PDT 24
Peak memory 201940 kb
Host smart-0f0788af-301c-456c-90e9-41755b340862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228714541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.228714541
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3594860249
Short name T415
Test name
Test status
Simulation time 332499879789 ps
CPU time 207.05 seconds
Started Jul 04 07:02:52 PM PDT 24
Finished Jul 04 07:06:19 PM PDT 24
Peak memory 201924 kb
Host smart-09359785-a2f4-4522-a870-9c2a5d225fb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594860249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3594860249
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3656112738
Short name T42
Test name
Test status
Simulation time 182178653014 ps
CPU time 210.32 seconds
Started Jul 04 07:02:53 PM PDT 24
Finished Jul 04 07:06:23 PM PDT 24
Peak memory 201908 kb
Host smart-ae94c830-f6a7-4958-b4e8-4a550f609e7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656112738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3656112738
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2528316090
Short name T736
Test name
Test status
Simulation time 601808689104 ps
CPU time 325.54 seconds
Started Jul 04 07:02:52 PM PDT 24
Finished Jul 04 07:08:18 PM PDT 24
Peak memory 201888 kb
Host smart-90757fa9-ecce-4039-a773-89ba55d3eb89
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528316090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2528316090
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.407527516
Short name T664
Test name
Test status
Simulation time 118679270408 ps
CPU time 666.9 seconds
Started Jul 04 07:03:04 PM PDT 24
Finished Jul 04 07:14:11 PM PDT 24
Peak memory 202188 kb
Host smart-2495af75-252d-414a-a853-8a4ab1c73d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407527516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.407527516
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3932247399
Short name T378
Test name
Test status
Simulation time 38131853646 ps
CPU time 9.41 seconds
Started Jul 04 07:03:04 PM PDT 24
Finished Jul 04 07:03:13 PM PDT 24
Peak memory 201652 kb
Host smart-5a0e0911-10d6-43d0-bc67-d8c73a6df2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932247399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3932247399
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.627451516
Short name T699
Test name
Test status
Simulation time 4892383882 ps
CPU time 11.77 seconds
Started Jul 04 07:03:02 PM PDT 24
Finished Jul 04 07:03:14 PM PDT 24
Peak memory 201728 kb
Host smart-2932a4f0-c375-4be6-bc98-e20f54045097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627451516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.627451516
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1192473386
Short name T598
Test name
Test status
Simulation time 5922623744 ps
CPU time 14.62 seconds
Started Jul 04 07:02:43 PM PDT 24
Finished Jul 04 07:02:58 PM PDT 24
Peak memory 201720 kb
Host smart-b64ec829-5671-4433-938e-519e28443938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192473386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1192473386
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3279815948
Short name T174
Test name
Test status
Simulation time 364079364042 ps
CPU time 409.41 seconds
Started Jul 04 07:03:08 PM PDT 24
Finished Jul 04 07:09:58 PM PDT 24
Peak memory 201908 kb
Host smart-76d6da9d-759f-458e-93e4-7c15ec13573f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279815948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3279815948
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2185296141
Short name T248
Test name
Test status
Simulation time 435360310156 ps
CPU time 172.46 seconds
Started Jul 04 07:03:01 PM PDT 24
Finished Jul 04 07:05:54 PM PDT 24
Peak memory 210248 kb
Host smart-cfafed85-eab2-43aa-a632-9d2e48090087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185296141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2185296141
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3280925825
Short name T796
Test name
Test status
Simulation time 513766750 ps
CPU time 1.82 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:03:17 PM PDT 24
Peak memory 201596 kb
Host smart-442dd001-dc8a-489a-a11c-f79cff90bd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280925825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3280925825
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2348240858
Short name T265
Test name
Test status
Simulation time 384609402672 ps
CPU time 417.25 seconds
Started Jul 04 07:03:07 PM PDT 24
Finished Jul 04 07:10:05 PM PDT 24
Peak memory 201980 kb
Host smart-ba166b0c-f736-4b67-84ed-2d38f41229d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348240858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2348240858
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2271186744
Short name T176
Test name
Test status
Simulation time 505413691766 ps
CPU time 300.05 seconds
Started Jul 04 07:03:07 PM PDT 24
Finished Jul 04 07:08:07 PM PDT 24
Peak memory 201932 kb
Host smart-6931c672-a8ef-45e2-b899-8ee3d67f329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271186744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2271186744
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1743884261
Short name T532
Test name
Test status
Simulation time 326069861604 ps
CPU time 193.26 seconds
Started Jul 04 07:03:07 PM PDT 24
Finished Jul 04 07:06:21 PM PDT 24
Peak memory 201904 kb
Host smart-f38f4e20-1ea1-4ecf-a3d7-05386e8c32c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743884261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1743884261
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3640584486
Short name T148
Test name
Test status
Simulation time 328355715228 ps
CPU time 198.71 seconds
Started Jul 04 07:03:06 PM PDT 24
Finished Jul 04 07:06:25 PM PDT 24
Peak memory 201936 kb
Host smart-16292d86-f5ed-4e95-a1cc-19224ca6874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640584486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3640584486
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3935671010
Short name T455
Test name
Test status
Simulation time 502488660983 ps
CPU time 287.68 seconds
Started Jul 04 07:03:05 PM PDT 24
Finished Jul 04 07:07:53 PM PDT 24
Peak memory 201948 kb
Host smart-459fcaaa-094a-468e-97f7-46335fdef5dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935671010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3935671010
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2060282065
Short name T296
Test name
Test status
Simulation time 363175439504 ps
CPU time 812.96 seconds
Started Jul 04 07:03:05 PM PDT 24
Finished Jul 04 07:16:39 PM PDT 24
Peak memory 201996 kb
Host smart-d4fb60ca-329e-477b-846e-8a04121587e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060282065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2060282065
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3803046379
Short name T593
Test name
Test status
Simulation time 608166480794 ps
CPU time 714.15 seconds
Started Jul 04 07:03:07 PM PDT 24
Finished Jul 04 07:15:01 PM PDT 24
Peak memory 201888 kb
Host smart-9600e73e-fc3f-493c-a183-069f7ea6dc2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803046379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3803046379
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.826092417
Short name T100
Test name
Test status
Simulation time 127351547983 ps
CPU time 521.41 seconds
Started Jul 04 07:03:06 PM PDT 24
Finished Jul 04 07:11:48 PM PDT 24
Peak memory 202244 kb
Host smart-125e018d-7bde-4324-98b4-b814dec473f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826092417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.826092417
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1304032884
Short name T582
Test name
Test status
Simulation time 38802164918 ps
CPU time 95.26 seconds
Started Jul 04 07:03:07 PM PDT 24
Finished Jul 04 07:04:42 PM PDT 24
Peak memory 201688 kb
Host smart-24176788-caaa-4a4b-9a99-8cc39995f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304032884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1304032884
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2705289870
Short name T7
Test name
Test status
Simulation time 2893738967 ps
CPU time 7.06 seconds
Started Jul 04 07:03:06 PM PDT 24
Finished Jul 04 07:03:14 PM PDT 24
Peak memory 201728 kb
Host smart-b9829b4b-e3ad-448d-989c-fef453f9491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705289870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2705289870
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2676739293
Short name T651
Test name
Test status
Simulation time 5684228011 ps
CPU time 7.4 seconds
Started Jul 04 07:03:05 PM PDT 24
Finished Jul 04 07:03:12 PM PDT 24
Peak memory 201748 kb
Host smart-4ea47436-cfe1-42b3-b736-2f7893abf9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676739293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2676739293
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3913966299
Short name T243
Test name
Test status
Simulation time 211725082555 ps
CPU time 87.9 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:04:43 PM PDT 24
Peak memory 201900 kb
Host smart-c096836c-18c0-4485-b934-ee4941ab81d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913966299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3913966299
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2056683070
Short name T623
Test name
Test status
Simulation time 503650010 ps
CPU time 0.88 seconds
Started Jul 04 07:03:24 PM PDT 24
Finished Jul 04 07:03:25 PM PDT 24
Peak memory 201672 kb
Host smart-29247e63-1584-4446-bc66-ff5a948588e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056683070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2056683070
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2429488812
Short name T25
Test name
Test status
Simulation time 353487861892 ps
CPU time 381.17 seconds
Started Jul 04 07:03:22 PM PDT 24
Finished Jul 04 07:09:43 PM PDT 24
Peak memory 201932 kb
Host smart-a05f0899-3d1c-438d-a0b6-4ba8b791e84a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429488812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2429488812
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1835997825
Short name T666
Test name
Test status
Simulation time 208557546583 ps
CPU time 50.16 seconds
Started Jul 04 07:03:22 PM PDT 24
Finished Jul 04 07:04:13 PM PDT 24
Peak memory 201892 kb
Host smart-3c9dc6e1-45a9-4e27-8237-e476d63e0d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835997825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1835997825
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3958003196
Short name T569
Test name
Test status
Simulation time 160901744679 ps
CPU time 185.45 seconds
Started Jul 04 07:03:14 PM PDT 24
Finished Jul 04 07:06:20 PM PDT 24
Peak memory 201972 kb
Host smart-5a3d6282-d137-4ba1-a7e7-9e7fbf9b1ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958003196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3958003196
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1563020242
Short name T182
Test name
Test status
Simulation time 163986483354 ps
CPU time 89.53 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:04:45 PM PDT 24
Peak memory 201912 kb
Host smart-8aefaf78-aae2-43fb-aa4e-8a637dbe28c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563020242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1563020242
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3576895696
Short name T41
Test name
Test status
Simulation time 482427701610 ps
CPU time 562.44 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:12:38 PM PDT 24
Peak memory 201908 kb
Host smart-d4a1da56-cfa5-49bc-9dad-2d58906948bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576895696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3576895696
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.92862787
Short name T195
Test name
Test status
Simulation time 372440828391 ps
CPU time 885.41 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:18:01 PM PDT 24
Peak memory 201904 kb
Host smart-bfe82c6f-4831-4c46-80e9-fa35905b160c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92862787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_w
akeup.92862787
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1104773579
Short name T398
Test name
Test status
Simulation time 585279738073 ps
CPU time 1256.99 seconds
Started Jul 04 07:03:16 PM PDT 24
Finished Jul 04 07:24:13 PM PDT 24
Peak memory 201892 kb
Host smart-3e17c175-b9e5-4cae-a93c-7f3d4c64abd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104773579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1104773579
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.596521230
Short name T406
Test name
Test status
Simulation time 87533235941 ps
CPU time 271.41 seconds
Started Jul 04 07:03:21 PM PDT 24
Finished Jul 04 07:07:52 PM PDT 24
Peak memory 202288 kb
Host smart-06daaa2f-7248-4c55-8559-fd86b360643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596521230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.596521230
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2760505250
Short name T566
Test name
Test status
Simulation time 38071721328 ps
CPU time 43.56 seconds
Started Jul 04 07:03:20 PM PDT 24
Finished Jul 04 07:04:04 PM PDT 24
Peak memory 201700 kb
Host smart-07bc6592-3ee4-42d9-8a75-b8bfcc413052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760505250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2760505250
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2615782561
Short name T179
Test name
Test status
Simulation time 3828139317 ps
CPU time 8.61 seconds
Started Jul 04 07:03:25 PM PDT 24
Finished Jul 04 07:03:34 PM PDT 24
Peak memory 201724 kb
Host smart-0dd0533f-b697-40ee-9d77-cc0ef03f63b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615782561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2615782561
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.598498516
Short name T448
Test name
Test status
Simulation time 5767645841 ps
CPU time 3.35 seconds
Started Jul 04 07:03:15 PM PDT 24
Finished Jul 04 07:03:19 PM PDT 24
Peak memory 201744 kb
Host smart-119e3bc8-3d43-442e-93ba-25531cc10b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598498516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.598498516
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.124214450
Short name T24
Test name
Test status
Simulation time 12385044907 ps
CPU time 25.74 seconds
Started Jul 04 07:03:25 PM PDT 24
Finished Jul 04 07:03:50 PM PDT 24
Peak memory 210540 kb
Host smart-0c54117d-a76b-4ff8-a085-a3914f48a9fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124214450 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.124214450
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.450936452
Short name T607
Test name
Test status
Simulation time 417694677 ps
CPU time 1.48 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:03:47 PM PDT 24
Peak memory 201672 kb
Host smart-15e21f7f-066d-478a-bd49-788b28d9c88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450936452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.450936452
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1860822279
Short name T732
Test name
Test status
Simulation time 164684684696 ps
CPU time 37.13 seconds
Started Jul 04 07:03:38 PM PDT 24
Finished Jul 04 07:04:15 PM PDT 24
Peak memory 201848 kb
Host smart-63239032-1de4-45fb-890f-4a23e251d4f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860822279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1860822279
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2610962468
Short name T270
Test name
Test status
Simulation time 193642489751 ps
CPU time 108.24 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:05:34 PM PDT 24
Peak memory 201912 kb
Host smart-b344cee0-dbab-4c42-a979-814a88c0a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610962468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2610962468
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2169502983
Short name T714
Test name
Test status
Simulation time 164456967912 ps
CPU time 336.99 seconds
Started Jul 04 07:03:30 PM PDT 24
Finished Jul 04 07:09:07 PM PDT 24
Peak memory 201884 kb
Host smart-e96005d3-f43d-402e-9a53-25157aabfb6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169502983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2169502983
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3084663011
Short name T284
Test name
Test status
Simulation time 327110683224 ps
CPU time 204.55 seconds
Started Jul 04 07:03:27 PM PDT 24
Finished Jul 04 07:06:52 PM PDT 24
Peak memory 201888 kb
Host smart-edfdf0f4-35fd-43aa-ba2e-c8f06adca60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084663011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3084663011
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.4268533984
Short name T396
Test name
Test status
Simulation time 157286920153 ps
CPU time 371.27 seconds
Started Jul 04 07:03:28 PM PDT 24
Finished Jul 04 07:09:40 PM PDT 24
Peak memory 201908 kb
Host smart-28bbd2af-b9d0-448d-ac8a-3c9a820bc886
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268533984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.4268533984
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1298508593
Short name T159
Test name
Test status
Simulation time 366551798222 ps
CPU time 191.63 seconds
Started Jul 04 07:03:38 PM PDT 24
Finished Jul 04 07:06:50 PM PDT 24
Peak memory 201928 kb
Host smart-60ce690e-d864-465d-b0fe-c074d7ff9a3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298508593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1298508593
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2603409187
Short name T418
Test name
Test status
Simulation time 603407771128 ps
CPU time 1492.39 seconds
Started Jul 04 07:03:37 PM PDT 24
Finished Jul 04 07:28:30 PM PDT 24
Peak memory 201856 kb
Host smart-d09078bd-3211-4947-943b-ce2eaa46fd0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603409187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2603409187
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.856021860
Short name T218
Test name
Test status
Simulation time 94715680833 ps
CPU time 521.84 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:12:28 PM PDT 24
Peak memory 202212 kb
Host smart-c5f37399-41f6-41e9-a8c8-812ed71734a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856021860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.856021860
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2757705655
Short name T677
Test name
Test status
Simulation time 33509828541 ps
CPU time 39.29 seconds
Started Jul 04 07:03:45 PM PDT 24
Finished Jul 04 07:04:24 PM PDT 24
Peak memory 201688 kb
Host smart-15dc4664-c164-4688-9e65-9323ac7f8cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757705655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2757705655
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3669613437
Short name T488
Test name
Test status
Simulation time 4944116631 ps
CPU time 3.19 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:03:50 PM PDT 24
Peak memory 201724 kb
Host smart-ada701f6-f634-4a6d-ba0b-57292bfcf659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669613437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3669613437
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1935941681
Short name T762
Test name
Test status
Simulation time 5728980336 ps
CPU time 3.58 seconds
Started Jul 04 07:03:30 PM PDT 24
Finished Jul 04 07:03:34 PM PDT 24
Peak memory 201716 kb
Host smart-9cf011d0-f145-410c-8572-603d15d4572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935941681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1935941681
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.300026028
Short name T653
Test name
Test status
Simulation time 122304150507 ps
CPU time 396.72 seconds
Started Jul 04 07:03:45 PM PDT 24
Finished Jul 04 07:10:22 PM PDT 24
Peak memory 210464 kb
Host smart-0c124dc1-6168-478d-91ad-242fb64ca376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300026028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
300026028
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.106115805
Short name T739
Test name
Test status
Simulation time 633766520 ps
CPU time 0.7 seconds
Started Jul 04 07:03:53 PM PDT 24
Finished Jul 04 07:03:54 PM PDT 24
Peak memory 201632 kb
Host smart-f698d4c1-a055-4a93-b60c-ee0496678b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106115805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.106115805
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3279389605
Short name T326
Test name
Test status
Simulation time 416234912091 ps
CPU time 158.24 seconds
Started Jul 04 07:03:51 PM PDT 24
Finished Jul 04 07:06:30 PM PDT 24
Peak memory 201976 kb
Host smart-d03cd578-9158-41e3-ae80-6e36f8dd54b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279389605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3279389605
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2080587746
Short name T257
Test name
Test status
Simulation time 323636876148 ps
CPU time 102.19 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:05:28 PM PDT 24
Peak memory 201916 kb
Host smart-6515d3b1-bf08-4ce2-87e4-dae7b4e610aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080587746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2080587746
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.212894882
Short name T409
Test name
Test status
Simulation time 337118743238 ps
CPU time 757.53 seconds
Started Jul 04 07:03:53 PM PDT 24
Finished Jul 04 07:16:31 PM PDT 24
Peak memory 201844 kb
Host smart-cf8a2310-c8da-457d-a5fd-a0c7a4570734
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=212894882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.212894882
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.139187462
Short name T298
Test name
Test status
Simulation time 162655835199 ps
CPU time 114.61 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:05:40 PM PDT 24
Peak memory 201920 kb
Host smart-ccc65a6d-e9a8-4cf5-a2fc-2ff63092ad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139187462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.139187462
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1597041794
Short name T548
Test name
Test status
Simulation time 331452971444 ps
CPU time 197.35 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:07:03 PM PDT 24
Peak memory 201888 kb
Host smart-c3570efc-681b-4714-a6a1-c3a5b57c0ad7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597041794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1597041794
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3906276364
Short name T290
Test name
Test status
Simulation time 178906005255 ps
CPU time 398.82 seconds
Started Jul 04 07:03:51 PM PDT 24
Finished Jul 04 07:10:30 PM PDT 24
Peak memory 201988 kb
Host smart-1dc703b7-813c-4c33-a685-d3c6d2e618ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906276364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3906276364
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3030714326
Short name T754
Test name
Test status
Simulation time 391983062566 ps
CPU time 212.52 seconds
Started Jul 04 07:03:51 PM PDT 24
Finished Jul 04 07:07:24 PM PDT 24
Peak memory 201980 kb
Host smart-d5519693-4bac-4d1e-885b-7bdff7d2ed3f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030714326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3030714326
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2529952505
Short name T731
Test name
Test status
Simulation time 128572848779 ps
CPU time 443.27 seconds
Started Jul 04 07:03:53 PM PDT 24
Finished Jul 04 07:11:17 PM PDT 24
Peak memory 202144 kb
Host smart-de1fc8f4-8aec-41e6-84bb-0b4b87b69b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529952505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2529952505
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1444486801
Short name T530
Test name
Test status
Simulation time 35399670563 ps
CPU time 83.89 seconds
Started Jul 04 07:03:51 PM PDT 24
Finished Jul 04 07:05:15 PM PDT 24
Peak memory 201724 kb
Host smart-f59e8181-f784-4a7d-856c-5751e89a0a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444486801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1444486801
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1650958404
Short name T568
Test name
Test status
Simulation time 5026026120 ps
CPU time 11.88 seconds
Started Jul 04 07:03:51 PM PDT 24
Finished Jul 04 07:04:03 PM PDT 24
Peak memory 201732 kb
Host smart-b9f3fdc7-814d-4166-bd8b-0df27496486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650958404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1650958404
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3741538253
Short name T99
Test name
Test status
Simulation time 5830646402 ps
CPU time 7.73 seconds
Started Jul 04 07:03:46 PM PDT 24
Finished Jul 04 07:03:54 PM PDT 24
Peak memory 201748 kb
Host smart-f75e6052-eeaf-48e1-94a3-0da27a7d3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741538253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3741538253
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3906389648
Short name T93
Test name
Test status
Simulation time 329508422128 ps
CPU time 227.68 seconds
Started Jul 04 07:03:52 PM PDT 24
Finished Jul 04 07:07:40 PM PDT 24
Peak memory 201976 kb
Host smart-8b190bf1-004b-4ccf-bca1-766ea295c26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906389648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3906389648
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2376576159
Short name T47
Test name
Test status
Simulation time 54964988500 ps
CPU time 63.68 seconds
Started Jul 04 07:03:53 PM PDT 24
Finished Jul 04 07:04:57 PM PDT 24
Peak memory 218644 kb
Host smart-57118b34-f2b1-4bf1-9794-ca7e9d4c8a26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376576159 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2376576159
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.105217964
Short name T700
Test name
Test status
Simulation time 323467967 ps
CPU time 1.27 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:00:18 PM PDT 24
Peak memory 201624 kb
Host smart-07402ec9-8430-46e6-a38f-f993bb3ae5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105217964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.105217964
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.382090819
Short name T303
Test name
Test status
Simulation time 379061984550 ps
CPU time 496.83 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:08:27 PM PDT 24
Peak memory 201848 kb
Host smart-2899be1e-43ad-4d93-8a48-2364827de2e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382090819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.382090819
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.606190175
Short name T203
Test name
Test status
Simulation time 570843792672 ps
CPU time 89.31 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:01:38 PM PDT 24
Peak memory 201892 kb
Host smart-0021da1c-0725-4d8e-931c-921d8b1fc84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606190175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.606190175
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.4267981023
Short name T163
Test name
Test status
Simulation time 488423266223 ps
CPU time 1017.51 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:17:06 PM PDT 24
Peak memory 201952 kb
Host smart-4bd0f7cd-ad52-41a8-9999-4e8b4f4bfd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267981023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.4267981023
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2721326378
Short name T379
Test name
Test status
Simulation time 330286196671 ps
CPU time 218.81 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:03:48 PM PDT 24
Peak memory 201872 kb
Host smart-24299165-0a15-49c7-a6e0-8678c49311a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721326378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2721326378
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2215666146
Short name T96
Test name
Test status
Simulation time 335214081855 ps
CPU time 742.2 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:12:31 PM PDT 24
Peak memory 201984 kb
Host smart-8580c97a-8d90-413b-b6cc-d59ce919863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215666146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2215666146
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1822028010
Short name T567
Test name
Test status
Simulation time 325813380919 ps
CPU time 347.97 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:05:57 PM PDT 24
Peak memory 201920 kb
Host smart-ee9aaed9-5696-46e1-86cc-130a1954d5e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822028010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1822028010
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.901609430
Short name T342
Test name
Test status
Simulation time 183849565911 ps
CPU time 215.73 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:03:44 PM PDT 24
Peak memory 201932 kb
Host smart-0ec5ce5d-fecf-450a-a2ad-f4168b9e8fcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901609430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.901609430
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.853202212
Short name T612
Test name
Test status
Simulation time 601974886797 ps
CPU time 113.17 seconds
Started Jul 04 07:00:08 PM PDT 24
Finished Jul 04 07:02:01 PM PDT 24
Peak memory 201924 kb
Host smart-0c88f574-fd4d-45fd-9142-1787d0a6e291
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853202212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.853202212
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2594831511
Short name T561
Test name
Test status
Simulation time 90047538664 ps
CPU time 320.07 seconds
Started Jul 04 07:00:11 PM PDT 24
Finished Jul 04 07:05:31 PM PDT 24
Peak memory 202252 kb
Host smart-e2f74fb6-0874-4c95-a036-88ada35f62c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594831511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2594831511
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3231091689
Short name T95
Test name
Test status
Simulation time 31113855308 ps
CPU time 65.6 seconds
Started Jul 04 07:00:09 PM PDT 24
Finished Jul 04 07:01:15 PM PDT 24
Peak memory 201716 kb
Host smart-df99e1ff-c7b7-45ae-b467-076763e04821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231091689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3231091689
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.872036154
Short name T382
Test name
Test status
Simulation time 5533831955 ps
CPU time 3.79 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:00:14 PM PDT 24
Peak memory 201732 kb
Host smart-a05d0dd2-ef1f-4f27-b586-59c51e1542e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872036154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.872036154
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1142835273
Short name T87
Test name
Test status
Simulation time 4150046878 ps
CPU time 9.35 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:00:27 PM PDT 24
Peak memory 217208 kb
Host smart-61c49a4c-040a-4823-94f9-ce3466e9fede
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142835273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1142835273
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3488680233
Short name T37
Test name
Test status
Simulation time 5869496748 ps
CPU time 13.01 seconds
Started Jul 04 07:00:10 PM PDT 24
Finished Jul 04 07:00:23 PM PDT 24
Peak memory 201736 kb
Host smart-58fcdf80-7f74-4df0-82e1-35252d62fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488680233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3488680233
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.253239349
Short name T759
Test name
Test status
Simulation time 207056797308 ps
CPU time 133.44 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:02:32 PM PDT 24
Peak memory 201952 kb
Host smart-47953a5a-5ac1-4e93-aba5-2efa7a70ce8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253239349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.253239349
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2236918472
Short name T385
Test name
Test status
Simulation time 303763363 ps
CPU time 1.31 seconds
Started Jul 04 07:04:08 PM PDT 24
Finished Jul 04 07:04:09 PM PDT 24
Peak memory 201596 kb
Host smart-d1e9ec35-974f-4c58-bf97-f3fdec99ed76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236918472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2236918472
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1489343296
Short name T211
Test name
Test status
Simulation time 322451814703 ps
CPU time 168.6 seconds
Started Jul 04 07:04:00 PM PDT 24
Finished Jul 04 07:06:49 PM PDT 24
Peak memory 201908 kb
Host smart-053a7c60-d38d-49d7-af45-4610edbb8591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489343296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1489343296
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1643576908
Short name T595
Test name
Test status
Simulation time 170860698585 ps
CPU time 96.18 seconds
Started Jul 04 07:04:01 PM PDT 24
Finished Jul 04 07:05:37 PM PDT 24
Peak memory 201960 kb
Host smart-8917cb7f-80fe-4a2a-b710-55f3f2551650
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643576908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1643576908
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3527714118
Short name T187
Test name
Test status
Simulation time 329303172830 ps
CPU time 693.59 seconds
Started Jul 04 07:03:52 PM PDT 24
Finished Jul 04 07:15:25 PM PDT 24
Peak memory 201984 kb
Host smart-aa92efa0-56df-48a8-afee-10faf551bb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527714118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3527714118
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4023784967
Short name T742
Test name
Test status
Simulation time 492930086200 ps
CPU time 272.13 seconds
Started Jul 04 07:04:01 PM PDT 24
Finished Jul 04 07:08:33 PM PDT 24
Peak memory 201916 kb
Host smart-78650228-c746-460a-928c-189c260286fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023784967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4023784967
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.499229865
Short name T280
Test name
Test status
Simulation time 175905682794 ps
CPU time 196.55 seconds
Started Jul 04 07:04:01 PM PDT 24
Finished Jul 04 07:07:18 PM PDT 24
Peak memory 201928 kb
Host smart-785b75d6-c10d-4f30-99c8-4226b3a5d804
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499229865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.499229865
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3335797079
Short name T636
Test name
Test status
Simulation time 605642854021 ps
CPU time 1408.42 seconds
Started Jul 04 07:03:59 PM PDT 24
Finished Jul 04 07:27:28 PM PDT 24
Peak memory 201856 kb
Host smart-3395da12-95df-4aed-8f40-c8fbe62b2782
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335797079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3335797079
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3433984620
Short name T223
Test name
Test status
Simulation time 102069417271 ps
CPU time 356.18 seconds
Started Jul 04 07:04:07 PM PDT 24
Finished Jul 04 07:10:03 PM PDT 24
Peak memory 202232 kb
Host smart-f1560f42-a1ea-4804-a6de-475666fadb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433984620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3433984620
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.751368796
Short name T650
Test name
Test status
Simulation time 36585172166 ps
CPU time 84.2 seconds
Started Jul 04 07:04:00 PM PDT 24
Finished Jul 04 07:05:24 PM PDT 24
Peak memory 201704 kb
Host smart-81d9c4fa-d4fe-4441-83fe-2770a5295eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751368796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.751368796
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1776118684
Short name T572
Test name
Test status
Simulation time 3161759920 ps
CPU time 2.67 seconds
Started Jul 04 07:04:00 PM PDT 24
Finished Jul 04 07:04:03 PM PDT 24
Peak memory 201680 kb
Host smart-2a80dbd8-62b9-41a8-8344-a2fe040ae2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776118684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1776118684
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4256261529
Short name T660
Test name
Test status
Simulation time 6117052834 ps
CPU time 6.65 seconds
Started Jul 04 07:03:52 PM PDT 24
Finished Jul 04 07:03:59 PM PDT 24
Peak memory 201740 kb
Host smart-139e89a5-8cdb-4ff3-91a3-bb3a3ec55800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256261529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4256261529
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2472648858
Short name T592
Test name
Test status
Simulation time 363010466751 ps
CPU time 854.5 seconds
Started Jul 04 07:04:05 PM PDT 24
Finished Jul 04 07:18:20 PM PDT 24
Peak memory 201892 kb
Host smart-86d40e3f-e94b-4df5-8b3e-2577fc2804c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472648858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2472648858
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2164536662
Short name T67
Test name
Test status
Simulation time 172212988347 ps
CPU time 477.6 seconds
Started Jul 04 07:04:05 PM PDT 24
Finished Jul 04 07:12:03 PM PDT 24
Peak memory 210596 kb
Host smart-7255195e-356c-419f-b491-9a5c7dfdaea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164536662 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2164536662
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2681376359
Short name T552
Test name
Test status
Simulation time 435364534 ps
CPU time 0.88 seconds
Started Jul 04 07:04:22 PM PDT 24
Finished Jul 04 07:04:23 PM PDT 24
Peak memory 201672 kb
Host smart-978cd53f-9235-41ee-94e5-82ad7e41e157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681376359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2681376359
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3651840348
Short name T246
Test name
Test status
Simulation time 196807570122 ps
CPU time 107.71 seconds
Started Jul 04 07:04:20 PM PDT 24
Finished Jul 04 07:06:08 PM PDT 24
Peak memory 201884 kb
Host smart-b9daf335-3639-436e-954d-272618f64681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651840348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3651840348
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3380228173
Short name T340
Test name
Test status
Simulation time 487875220183 ps
CPU time 625.45 seconds
Started Jul 04 07:04:14 PM PDT 24
Finished Jul 04 07:14:39 PM PDT 24
Peak memory 201984 kb
Host smart-53050593-88e1-4410-b5e6-398d6960d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380228173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3380228173
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2331951358
Short name T521
Test name
Test status
Simulation time 324635800482 ps
CPU time 286.11 seconds
Started Jul 04 07:04:14 PM PDT 24
Finished Jul 04 07:09:01 PM PDT 24
Peak memory 201908 kb
Host smart-9916f4dc-bb51-49cc-8aad-c19fc96fb972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331951358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2331951358
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3579704520
Short name T497
Test name
Test status
Simulation time 329796265521 ps
CPU time 200.37 seconds
Started Jul 04 07:04:14 PM PDT 24
Finished Jul 04 07:07:35 PM PDT 24
Peak memory 201964 kb
Host smart-e0d0d184-e24a-44b3-b97e-5e0a08529573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579704520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3579704520
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.303348337
Short name T422
Test name
Test status
Simulation time 338552179216 ps
CPU time 804.05 seconds
Started Jul 04 07:04:14 PM PDT 24
Finished Jul 04 07:17:38 PM PDT 24
Peak memory 201840 kb
Host smart-bf1311a0-717c-429a-b48d-c72f90c3f1c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=303348337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.303348337
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.297367162
Short name T324
Test name
Test status
Simulation time 659738824570 ps
CPU time 369.84 seconds
Started Jul 04 07:04:13 PM PDT 24
Finished Jul 04 07:10:23 PM PDT 24
Peak memory 202000 kb
Host smart-ebf121c6-6105-4c71-bb4a-123f707b04af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297367162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.297367162
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.4251714941
Short name T105
Test name
Test status
Simulation time 429975704377 ps
CPU time 987.83 seconds
Started Jul 04 07:04:21 PM PDT 24
Finished Jul 04 07:20:49 PM PDT 24
Peak memory 201896 kb
Host smart-939123b8-8b92-47f1-a344-d7d5f8481d73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251714941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.4251714941
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2770041838
Short name T58
Test name
Test status
Simulation time 97559811934 ps
CPU time 340.33 seconds
Started Jul 04 07:04:20 PM PDT 24
Finished Jul 04 07:10:01 PM PDT 24
Peak memory 202200 kb
Host smart-cbbff618-a348-4efc-982e-3701c134a614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770041838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2770041838
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1884997402
Short name T564
Test name
Test status
Simulation time 39432044541 ps
CPU time 5.03 seconds
Started Jul 04 07:04:20 PM PDT 24
Finished Jul 04 07:04:25 PM PDT 24
Peak memory 201720 kb
Host smart-b52a7bf4-dda4-47a9-81ea-7f7db9ddab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884997402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1884997402
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3912106247
Short name T435
Test name
Test status
Simulation time 2916811867 ps
CPU time 6.38 seconds
Started Jul 04 07:04:22 PM PDT 24
Finished Jul 04 07:04:28 PM PDT 24
Peak memory 201728 kb
Host smart-7fa64309-be45-436e-9634-ea97d4ae094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912106247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3912106247
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2178157274
Short name T693
Test name
Test status
Simulation time 5837876455 ps
CPU time 15.33 seconds
Started Jul 04 07:04:15 PM PDT 24
Finished Jul 04 07:04:30 PM PDT 24
Peak memory 201728 kb
Host smart-f8c10f8a-b668-439f-b9e8-cfca5c670d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178157274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2178157274
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1177416753
Short name T540
Test name
Test status
Simulation time 391785089060 ps
CPU time 1322.85 seconds
Started Jul 04 07:04:19 PM PDT 24
Finished Jul 04 07:26:22 PM PDT 24
Peak memory 218560 kb
Host smart-a2067540-186e-477b-9372-e666273b2872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177416753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1177416753
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2540581514
Short name T214
Test name
Test status
Simulation time 27961659034 ps
CPU time 71.4 seconds
Started Jul 04 07:04:22 PM PDT 24
Finished Jul 04 07:05:33 PM PDT 24
Peak memory 210560 kb
Host smart-f57a54a8-1317-4150-aa29-e48489becec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540581514 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2540581514
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3697175484
Short name T362
Test name
Test status
Simulation time 493230658 ps
CPU time 0.89 seconds
Started Jul 04 07:04:29 PM PDT 24
Finished Jul 04 07:04:30 PM PDT 24
Peak memory 201640 kb
Host smart-8221799c-1152-4e34-84ae-d3379f32acba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697175484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3697175484
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2880179008
Short name T239
Test name
Test status
Simulation time 544208770620 ps
CPU time 841.87 seconds
Started Jul 04 07:04:29 PM PDT 24
Finished Jul 04 07:18:31 PM PDT 24
Peak memory 201992 kb
Host smart-8b037a3c-681c-4edd-b19f-3ab157ddacba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880179008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2880179008
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2897828952
Short name T143
Test name
Test status
Simulation time 165879079749 ps
CPU time 186.42 seconds
Started Jul 04 07:04:26 PM PDT 24
Finished Jul 04 07:07:33 PM PDT 24
Peak memory 201952 kb
Host smart-454b9e75-f8c7-4102-ba46-d769d752d358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897828952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2897828952
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1594798587
Short name T365
Test name
Test status
Simulation time 490200906995 ps
CPU time 1064.89 seconds
Started Jul 04 07:04:27 PM PDT 24
Finished Jul 04 07:22:12 PM PDT 24
Peak memory 201892 kb
Host smart-15997db9-1368-40eb-b01e-99af4fedfd79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594798587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1594798587
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3451797529
Short name T282
Test name
Test status
Simulation time 165986074961 ps
CPU time 58.96 seconds
Started Jul 04 07:04:22 PM PDT 24
Finished Jul 04 07:05:21 PM PDT 24
Peak memory 201916 kb
Host smart-98375986-6db6-4451-8f0d-a8adc7d2a144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451797529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3451797529
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.839543443
Short name T643
Test name
Test status
Simulation time 498498850310 ps
CPU time 1136.43 seconds
Started Jul 04 07:04:20 PM PDT 24
Finished Jul 04 07:23:16 PM PDT 24
Peak memory 201924 kb
Host smart-32491389-6c32-4bf7-b233-b3a4103d4e0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=839543443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.839543443
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1354571647
Short name T452
Test name
Test status
Simulation time 400921325807 ps
CPU time 223.72 seconds
Started Jul 04 07:04:29 PM PDT 24
Finished Jul 04 07:08:13 PM PDT 24
Peak memory 201884 kb
Host smart-e52c42bc-2dbf-4158-8eb3-139a2dcbff2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354571647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1354571647
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2623507176
Short name T584
Test name
Test status
Simulation time 114405872863 ps
CPU time 448.27 seconds
Started Jul 04 07:04:26 PM PDT 24
Finished Jul 04 07:11:55 PM PDT 24
Peak memory 202236 kb
Host smart-ee891955-b49f-42ce-a3ba-97486941b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623507176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2623507176
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.495070352
Short name T795
Test name
Test status
Simulation time 22150675226 ps
CPU time 26.18 seconds
Started Jul 04 07:04:26 PM PDT 24
Finished Jul 04 07:04:52 PM PDT 24
Peak memory 201728 kb
Host smart-0024adcd-95a4-4d15-92b8-9e31f634d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495070352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.495070352
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.329317364
Short name T545
Test name
Test status
Simulation time 4650885569 ps
CPU time 11.2 seconds
Started Jul 04 07:04:28 PM PDT 24
Finished Jul 04 07:04:39 PM PDT 24
Peak memory 201728 kb
Host smart-0057e4d0-075a-4d85-985b-2e32fe4cdf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329317364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.329317364
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2792467706
Short name T166
Test name
Test status
Simulation time 5660778016 ps
CPU time 8.07 seconds
Started Jul 04 07:04:22 PM PDT 24
Finished Jul 04 07:04:30 PM PDT 24
Peak memory 201708 kb
Host smart-ff6a8d97-7a6a-45c6-a953-2458a0e1d663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792467706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2792467706
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1040663820
Short name T338
Test name
Test status
Simulation time 783613511619 ps
CPU time 339.53 seconds
Started Jul 04 07:04:29 PM PDT 24
Finished Jul 04 07:10:09 PM PDT 24
Peak memory 201948 kb
Host smart-4bbd0e5c-e2ce-4b48-8f13-4f4f3a58f6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040663820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1040663820
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3595517286
Short name T341
Test name
Test status
Simulation time 259735432071 ps
CPU time 72.71 seconds
Started Jul 04 07:04:27 PM PDT 24
Finished Jul 04 07:05:40 PM PDT 24
Peak memory 202084 kb
Host smart-13ebcbaa-0a1b-457c-85fd-1e38f0a7e027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595517286 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3595517286
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3491072870
Short name T445
Test name
Test status
Simulation time 533995117 ps
CPU time 1.13 seconds
Started Jul 04 07:04:48 PM PDT 24
Finished Jul 04 07:04:49 PM PDT 24
Peak memory 201660 kb
Host smart-0c46ed0d-4443-43bc-8d54-5b79a592277c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491072870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3491072870
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3578799117
Short name T631
Test name
Test status
Simulation time 346215193022 ps
CPU time 176.2 seconds
Started Jul 04 07:04:33 PM PDT 24
Finished Jul 04 07:07:29 PM PDT 24
Peak memory 201964 kb
Host smart-f50c9366-8f2e-42d5-b76e-fa2b3be3723d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578799117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3578799117
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.582298595
Short name T137
Test name
Test status
Simulation time 354996123498 ps
CPU time 335.7 seconds
Started Jul 04 07:04:41 PM PDT 24
Finished Jul 04 07:10:17 PM PDT 24
Peak memory 201888 kb
Host smart-4fd3cb25-e540-4f8f-8520-100294a21774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582298595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.582298595
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3656464011
Short name T525
Test name
Test status
Simulation time 160876126454 ps
CPU time 180.48 seconds
Started Jul 04 07:04:34 PM PDT 24
Finished Jul 04 07:07:35 PM PDT 24
Peak memory 201944 kb
Host smart-ca15d258-0b68-4369-98e3-b3137582f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656464011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3656464011
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3040729685
Short name T678
Test name
Test status
Simulation time 341334085744 ps
CPU time 398.96 seconds
Started Jul 04 07:04:33 PM PDT 24
Finished Jul 04 07:11:12 PM PDT 24
Peak memory 201884 kb
Host smart-5ab90cd6-c19f-47cd-8a4f-28c036d12aca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040729685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3040729685
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2881590145
Short name T151
Test name
Test status
Simulation time 327200257226 ps
CPU time 772.8 seconds
Started Jul 04 07:04:32 PM PDT 24
Finished Jul 04 07:17:25 PM PDT 24
Peak memory 201972 kb
Host smart-9bce53c6-168a-4cb0-983d-da7a495f1c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881590145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2881590145
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1996999665
Short name T555
Test name
Test status
Simulation time 161870470298 ps
CPU time 340.42 seconds
Started Jul 04 07:04:34 PM PDT 24
Finished Jul 04 07:10:15 PM PDT 24
Peak memory 201920 kb
Host smart-08cdd4df-8087-4573-aad8-76f91be92dcd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996999665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1996999665
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.4237516936
Short name T765
Test name
Test status
Simulation time 204976863402 ps
CPU time 457.05 seconds
Started Jul 04 07:04:34 PM PDT 24
Finished Jul 04 07:12:11 PM PDT 24
Peak memory 201916 kb
Host smart-23caf987-0385-4343-889b-cefa04e399f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237516936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.4237516936
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3689475633
Short name T620
Test name
Test status
Simulation time 85028298836 ps
CPU time 291.2 seconds
Started Jul 04 07:04:39 PM PDT 24
Finished Jul 04 07:09:31 PM PDT 24
Peak memory 202212 kb
Host smart-4aafb5e0-fd18-4b64-b724-62e364c8365e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689475633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3689475633
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2358096544
Short name T28
Test name
Test status
Simulation time 30404518939 ps
CPU time 34.77 seconds
Started Jul 04 07:04:40 PM PDT 24
Finished Jul 04 07:05:15 PM PDT 24
Peak memory 201724 kb
Host smart-69e7f96f-9cfb-480b-9e2d-bd7c48873084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358096544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2358096544
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3805886112
Short name T728
Test name
Test status
Simulation time 3358073816 ps
CPU time 2.11 seconds
Started Jul 04 07:04:41 PM PDT 24
Finished Jul 04 07:04:43 PM PDT 24
Peak memory 201720 kb
Host smart-2a10e425-7a7a-4e71-b4cd-91bb9e17e2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805886112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3805886112
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1683992248
Short name T633
Test name
Test status
Simulation time 5723471501 ps
CPU time 4.24 seconds
Started Jul 04 07:04:26 PM PDT 24
Finished Jul 04 07:04:31 PM PDT 24
Peak memory 201740 kb
Host smart-df1bd88d-35ad-4f4e-8733-231fe80e159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683992248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1683992248
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3938137389
Short name T20
Test name
Test status
Simulation time 85122026437 ps
CPU time 266.22 seconds
Started Jul 04 07:04:39 PM PDT 24
Finished Jul 04 07:09:05 PM PDT 24
Peak memory 218564 kb
Host smart-f576d4c8-a766-4365-93fa-5232c7c1f24a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938137389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3938137389
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2309153399
Short name T430
Test name
Test status
Simulation time 641478814 ps
CPU time 0.74 seconds
Started Jul 04 07:05:03 PM PDT 24
Finished Jul 04 07:05:04 PM PDT 24
Peak memory 201652 kb
Host smart-5e3ebc3e-2969-4588-95e4-f51ee75902a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309153399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2309153399
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3457397953
Short name T323
Test name
Test status
Simulation time 514082283936 ps
CPU time 342.62 seconds
Started Jul 04 07:04:51 PM PDT 24
Finished Jul 04 07:10:34 PM PDT 24
Peak memory 201908 kb
Host smart-aa91a3e9-fb3e-446d-986a-8549981e8bbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457397953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3457397953
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2548346780
Short name T249
Test name
Test status
Simulation time 582919107117 ps
CPU time 397.24 seconds
Started Jul 04 07:04:54 PM PDT 24
Finished Jul 04 07:11:32 PM PDT 24
Peak memory 201920 kb
Host smart-22cfc619-2edf-4d86-ab22-72646871e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548346780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2548346780
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3311138917
Short name T190
Test name
Test status
Simulation time 488689304372 ps
CPU time 274.79 seconds
Started Jul 04 07:04:47 PM PDT 24
Finished Jul 04 07:09:22 PM PDT 24
Peak memory 201928 kb
Host smart-72d458b3-3ff9-4690-bab7-227c60bd557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311138917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3311138917
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3398569081
Short name T517
Test name
Test status
Simulation time 162911280991 ps
CPU time 31.05 seconds
Started Jul 04 07:04:47 PM PDT 24
Finished Jul 04 07:05:18 PM PDT 24
Peak memory 201864 kb
Host smart-b465276a-1c19-4c73-b525-3e0b6f528815
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398569081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3398569081
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3987468406
Short name T647
Test name
Test status
Simulation time 328351539018 ps
CPU time 361.24 seconds
Started Jul 04 07:04:50 PM PDT 24
Finished Jul 04 07:10:52 PM PDT 24
Peak memory 201896 kb
Host smart-b34629d0-544e-4d8e-9d60-88da162f6bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987468406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3987468406
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3926175145
Short name T550
Test name
Test status
Simulation time 164803162336 ps
CPU time 188.69 seconds
Started Jul 04 07:04:50 PM PDT 24
Finished Jul 04 07:07:59 PM PDT 24
Peak memory 201888 kb
Host smart-ecd3ba7a-c82e-4246-a456-dcf6b91e27b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926175145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3926175145
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2330378142
Short name T615
Test name
Test status
Simulation time 172285660970 ps
CPU time 97.83 seconds
Started Jul 04 07:04:45 PM PDT 24
Finished Jul 04 07:06:23 PM PDT 24
Peak memory 201932 kb
Host smart-3252ae51-cdcd-4934-aabc-fe2e72b7858a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330378142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2330378142
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1423665796
Short name T558
Test name
Test status
Simulation time 419075917106 ps
CPU time 233.06 seconds
Started Jul 04 07:04:52 PM PDT 24
Finished Jul 04 07:08:46 PM PDT 24
Peak memory 201928 kb
Host smart-0ff52293-498d-4804-b664-71da67fe4fcd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423665796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1423665796
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1874814525
Short name T226
Test name
Test status
Simulation time 82724143376 ps
CPU time 425.87 seconds
Started Jul 04 07:04:54 PM PDT 24
Finished Jul 04 07:12:00 PM PDT 24
Peak memory 202140 kb
Host smart-b6637541-c255-4528-b499-ba419fe31e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874814525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1874814525
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1402930462
Short name T376
Test name
Test status
Simulation time 40373884939 ps
CPU time 45.68 seconds
Started Jul 04 07:04:52 PM PDT 24
Finished Jul 04 07:05:38 PM PDT 24
Peak memory 201732 kb
Host smart-0a115c79-c9c4-4a91-b7d8-e5ff844f920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402930462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1402930462
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1894478761
Short name T775
Test name
Test status
Simulation time 3891226680 ps
CPU time 2.82 seconds
Started Jul 04 07:04:53 PM PDT 24
Finished Jul 04 07:04:56 PM PDT 24
Peak memory 201708 kb
Host smart-fc241bcd-6d29-417d-b395-3d6ec9d65174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894478761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1894478761
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.4282660694
Short name T464
Test name
Test status
Simulation time 5734279326 ps
CPU time 12.63 seconds
Started Jul 04 07:04:46 PM PDT 24
Finished Jul 04 07:04:59 PM PDT 24
Peak memory 201660 kb
Host smart-10e70059-836b-4392-aafe-838596f43b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282660694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.4282660694
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3138317014
Short name T44
Test name
Test status
Simulation time 180367255829 ps
CPU time 100.67 seconds
Started Jul 04 07:04:59 PM PDT 24
Finished Jul 04 07:06:40 PM PDT 24
Peak memory 201988 kb
Host smart-0a9f4bf5-d701-45c1-92eb-b8e5682f04b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138317014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3138317014
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3445738629
Short name T330
Test name
Test status
Simulation time 279619005733 ps
CPU time 360.38 seconds
Started Jul 04 07:05:02 PM PDT 24
Finished Jul 04 07:11:02 PM PDT 24
Peak memory 210608 kb
Host smart-e9e5b5f1-6495-4601-8f5c-e8a80b0f243c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445738629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3445738629
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3098068738
Short name T467
Test name
Test status
Simulation time 408977915 ps
CPU time 0.86 seconds
Started Jul 04 07:05:07 PM PDT 24
Finished Jul 04 07:05:08 PM PDT 24
Peak memory 201668 kb
Host smart-a02cdb9a-c39d-4a23-a1af-ea50cf63f55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098068738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3098068738
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.666377764
Short name T318
Test name
Test status
Simulation time 342277445473 ps
CPU time 712.6 seconds
Started Jul 04 07:05:08 PM PDT 24
Finished Jul 04 07:17:01 PM PDT 24
Peak memory 201904 kb
Host smart-854f59a9-341c-4252-a1c9-effa093f88d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666377764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.666377764
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.592207492
Short name T196
Test name
Test status
Simulation time 172103035042 ps
CPU time 366.24 seconds
Started Jul 04 07:05:06 PM PDT 24
Finished Jul 04 07:11:13 PM PDT 24
Peak memory 201888 kb
Host smart-0478f4a9-fec7-428a-8d7d-9f1e40cf93e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592207492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.592207492
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3575860086
Short name T321
Test name
Test status
Simulation time 494765821617 ps
CPU time 560.5 seconds
Started Jul 04 07:05:00 PM PDT 24
Finished Jul 04 07:14:21 PM PDT 24
Peak memory 201904 kb
Host smart-463ace8b-2596-4b12-aa17-301f0754bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575860086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3575860086
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.303383921
Short name T102
Test name
Test status
Simulation time 168087786515 ps
CPU time 369.31 seconds
Started Jul 04 07:04:59 PM PDT 24
Finished Jul 04 07:11:09 PM PDT 24
Peak memory 201896 kb
Host smart-eac66d6d-b500-4716-85f4-739c2cc9cbef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=303383921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.303383921
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.974609907
Short name T640
Test name
Test status
Simulation time 327203181877 ps
CPU time 754.84 seconds
Started Jul 04 07:05:03 PM PDT 24
Finished Jul 04 07:17:38 PM PDT 24
Peak memory 201976 kb
Host smart-b03671dc-b6c7-44b1-bc72-5de6e31ba79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974609907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.974609907
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3688301031
Short name T371
Test name
Test status
Simulation time 163342755929 ps
CPU time 380.41 seconds
Started Jul 04 07:05:00 PM PDT 24
Finished Jul 04 07:11:20 PM PDT 24
Peak memory 201888 kb
Host smart-9a2cc316-85a6-4c4c-8d84-afe0901e3090
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688301031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3688301031
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.429065495
Short name T236
Test name
Test status
Simulation time 417929592648 ps
CPU time 142.19 seconds
Started Jul 04 07:05:03 PM PDT 24
Finished Jul 04 07:07:26 PM PDT 24
Peak memory 201908 kb
Host smart-903aef84-fdb3-4595-956f-2e00c4089280
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429065495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.429065495
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3745591025
Short name T601
Test name
Test status
Simulation time 137711394064 ps
CPU time 711.54 seconds
Started Jul 04 07:05:07 PM PDT 24
Finished Jul 04 07:16:59 PM PDT 24
Peak memory 202204 kb
Host smart-3331b37a-d950-4839-82af-4aac263452cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745591025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3745591025
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1504275823
Short name T495
Test name
Test status
Simulation time 23899560179 ps
CPU time 52.6 seconds
Started Jul 04 07:05:07 PM PDT 24
Finished Jul 04 07:06:00 PM PDT 24
Peak memory 201728 kb
Host smart-b26806af-1322-45ce-8f8f-c0288ad68c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504275823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1504275823
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.4069835296
Short name T386
Test name
Test status
Simulation time 4582215578 ps
CPU time 10.56 seconds
Started Jul 04 07:05:07 PM PDT 24
Finished Jul 04 07:05:18 PM PDT 24
Peak memory 201704 kb
Host smart-4dbe7d13-5308-4744-a099-b5452bf62ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069835296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.4069835296
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3321075549
Short name T377
Test name
Test status
Simulation time 5691430294 ps
CPU time 14.1 seconds
Started Jul 04 07:04:59 PM PDT 24
Finished Jul 04 07:05:13 PM PDT 24
Peak memory 201748 kb
Host smart-ab7eb011-fe93-4757-824b-122d2c2f0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321075549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3321075549
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.686258559
Short name T603
Test name
Test status
Simulation time 370779716751 ps
CPU time 52.21 seconds
Started Jul 04 07:05:06 PM PDT 24
Finished Jul 04 07:05:58 PM PDT 24
Peak memory 201924 kb
Host smart-fa1d272a-7454-4422-aa34-45d84d97f7e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686258559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
686258559
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1191091268
Short name T500
Test name
Test status
Simulation time 26902638885 ps
CPU time 55.89 seconds
Started Jul 04 07:05:08 PM PDT 24
Finished Jul 04 07:06:04 PM PDT 24
Peak memory 210228 kb
Host smart-f57303fd-83b5-4306-8e52-184669edfc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191091268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1191091268
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2722176129
Short name T752
Test name
Test status
Simulation time 376270079 ps
CPU time 1.49 seconds
Started Jul 04 07:05:23 PM PDT 24
Finished Jul 04 07:05:24 PM PDT 24
Peak memory 201616 kb
Host smart-4dc02b19-4169-4591-ae77-5e82992a05e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722176129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2722176129
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4230455476
Short name T199
Test name
Test status
Simulation time 526153612959 ps
CPU time 326.56 seconds
Started Jul 04 07:05:14 PM PDT 24
Finished Jul 04 07:10:41 PM PDT 24
Peak memory 201984 kb
Host smart-3b5fe6aa-fff8-4108-bad0-9ed1b6fb5db6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230455476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4230455476
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1855297736
Short name T707
Test name
Test status
Simulation time 172717173156 ps
CPU time 276.67 seconds
Started Jul 04 07:05:14 PM PDT 24
Finished Jul 04 07:09:51 PM PDT 24
Peak memory 201952 kb
Host smart-ad279a11-c4c4-45a7-b49b-5cc0d65d2de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855297736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1855297736
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3554619953
Short name T696
Test name
Test status
Simulation time 496067790019 ps
CPU time 1006.61 seconds
Started Jul 04 07:05:15 PM PDT 24
Finished Jul 04 07:22:02 PM PDT 24
Peak memory 201892 kb
Host smart-b4e7642f-8229-47dd-bdc9-4d36a9b0f171
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554619953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3554619953
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1140950824
Short name T756
Test name
Test status
Simulation time 156175415889 ps
CPU time 174.61 seconds
Started Jul 04 07:05:06 PM PDT 24
Finished Jul 04 07:08:01 PM PDT 24
Peak memory 201920 kb
Host smart-f407e7d9-34e2-4349-ba4d-2a903d49b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140950824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1140950824
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.744038503
Short name T644
Test name
Test status
Simulation time 329180734327 ps
CPU time 95.36 seconds
Started Jul 04 07:05:08 PM PDT 24
Finished Jul 04 07:06:44 PM PDT 24
Peak memory 201908 kb
Host smart-ffca3035-285a-42f1-bfad-432d2e3415f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=744038503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.744038503
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1204333989
Short name T494
Test name
Test status
Simulation time 589265483917 ps
CPU time 1338.5 seconds
Started Jul 04 07:05:14 PM PDT 24
Finished Jul 04 07:27:32 PM PDT 24
Peak memory 201912 kb
Host smart-ac82c836-5fb7-4871-bd8d-506ccb6b410e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204333989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1204333989
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.168501036
Short name T587
Test name
Test status
Simulation time 102943745503 ps
CPU time 357.75 seconds
Started Jul 04 07:05:22 PM PDT 24
Finished Jul 04 07:11:20 PM PDT 24
Peak memory 202188 kb
Host smart-017885b1-3046-4bb9-99dd-aac3180284d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168501036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.168501036
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1530477596
Short name T535
Test name
Test status
Simulation time 37077076541 ps
CPU time 41.86 seconds
Started Jul 04 07:05:22 PM PDT 24
Finished Jul 04 07:06:04 PM PDT 24
Peak memory 201724 kb
Host smart-af3724c0-714a-4c97-ad81-b09560869d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530477596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1530477596
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3083391602
Short name T777
Test name
Test status
Simulation time 4055550197 ps
CPU time 2.73 seconds
Started Jul 04 07:05:21 PM PDT 24
Finished Jul 04 07:05:24 PM PDT 24
Peak memory 201720 kb
Host smart-7760b61e-a290-43d9-86d4-df2a915df03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083391602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3083391602
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3075145367
Short name T456
Test name
Test status
Simulation time 5920611559 ps
CPU time 7.12 seconds
Started Jul 04 07:05:07 PM PDT 24
Finished Jul 04 07:05:14 PM PDT 24
Peak memory 201728 kb
Host smart-b5306851-4ae3-4b4b-b5a4-4c4efb6b8ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075145367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3075145367
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2684298799
Short name T710
Test name
Test status
Simulation time 353190128277 ps
CPU time 414.92 seconds
Started Jul 04 07:05:24 PM PDT 24
Finished Jul 04 07:12:19 PM PDT 24
Peak memory 201968 kb
Host smart-2fec3831-2e18-4a01-aa80-424b8b52d898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684298799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2684298799
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1597729618
Short name T772
Test name
Test status
Simulation time 423746748 ps
CPU time 1.48 seconds
Started Jul 04 07:05:35 PM PDT 24
Finished Jul 04 07:05:37 PM PDT 24
Peak memory 201608 kb
Host smart-1255d64f-e092-404d-8551-b575fce95e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597729618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1597729618
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.843352753
Short name T581
Test name
Test status
Simulation time 177305141769 ps
CPU time 97.83 seconds
Started Jul 04 07:05:26 PM PDT 24
Finished Jul 04 07:07:04 PM PDT 24
Peak memory 201852 kb
Host smart-a9d93614-cac6-43fd-8e0a-e03dd036c717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843352753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.843352753
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3009223827
Short name T157
Test name
Test status
Simulation time 490045312758 ps
CPU time 212.85 seconds
Started Jul 04 07:05:24 PM PDT 24
Finished Jul 04 07:08:58 PM PDT 24
Peak memory 201968 kb
Host smart-4956a648-93f6-4a1d-acd6-7d8593d9b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009223827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3009223827
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2382829488
Short name T104
Test name
Test status
Simulation time 332580827353 ps
CPU time 269.7 seconds
Started Jul 04 07:05:24 PM PDT 24
Finished Jul 04 07:09:54 PM PDT 24
Peak memory 201900 kb
Host smart-bb1f8d70-4c2d-4163-b228-00b59904b874
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382829488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2382829488
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2902634332
Short name T141
Test name
Test status
Simulation time 320859743317 ps
CPU time 78.13 seconds
Started Jul 04 07:05:22 PM PDT 24
Finished Jul 04 07:06:40 PM PDT 24
Peak memory 201896 kb
Host smart-eb07f8a9-75a8-4935-808a-d0bcfa64d6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902634332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2902634332
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3657880775
Short name T410
Test name
Test status
Simulation time 325062917213 ps
CPU time 194.7 seconds
Started Jul 04 07:05:22 PM PDT 24
Finished Jul 04 07:08:36 PM PDT 24
Peak memory 201904 kb
Host smart-954f830d-5bdb-4c89-912c-df8509985589
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657880775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3657880775
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2227606370
Short name T727
Test name
Test status
Simulation time 373918550948 ps
CPU time 217.61 seconds
Started Jul 04 07:05:20 PM PDT 24
Finished Jul 04 07:08:58 PM PDT 24
Peak memory 201916 kb
Host smart-7f9bc753-f4ba-4a24-aa59-52d06461ba37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227606370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2227606370
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.775719865
Short name T627
Test name
Test status
Simulation time 599984347071 ps
CPU time 1363.11 seconds
Started Jul 04 07:05:27 PM PDT 24
Finished Jul 04 07:28:10 PM PDT 24
Peak memory 201896 kb
Host smart-3d440fc8-ed0c-4ae7-b5b6-7ea5117636db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775719865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.775719865
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1142467988
Short name T764
Test name
Test status
Simulation time 96494697644 ps
CPU time 303.63 seconds
Started Jul 04 07:05:27 PM PDT 24
Finished Jul 04 07:10:31 PM PDT 24
Peak memory 202288 kb
Host smart-1a9aaa65-3baf-44a4-b8d8-72dfeef2f961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142467988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1142467988
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2339871979
Short name T706
Test name
Test status
Simulation time 26578951181 ps
CPU time 60.34 seconds
Started Jul 04 07:05:27 PM PDT 24
Finished Jul 04 07:06:28 PM PDT 24
Peak memory 201728 kb
Host smart-932fca80-37f1-4326-ab74-47218867092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339871979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2339871979
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.114847179
Short name T363
Test name
Test status
Simulation time 3546312228 ps
CPU time 8.64 seconds
Started Jul 04 07:05:29 PM PDT 24
Finished Jul 04 07:05:37 PM PDT 24
Peak memory 201716 kb
Host smart-11410861-39ef-4651-bd3e-f2e03ae757bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114847179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.114847179
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2942012194
Short name T747
Test name
Test status
Simulation time 5806128238 ps
CPU time 15.67 seconds
Started Jul 04 07:05:21 PM PDT 24
Finished Jul 04 07:05:37 PM PDT 24
Peak memory 201704 kb
Host smart-142ee0b2-c499-4e6b-9d03-8703ee91dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942012194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2942012194
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.924480084
Short name T441
Test name
Test status
Simulation time 440749210301 ps
CPU time 261.13 seconds
Started Jul 04 07:05:34 PM PDT 24
Finished Jul 04 07:09:56 PM PDT 24
Peak memory 201844 kb
Host smart-308145c2-3d76-491f-84b1-f7ad127d3fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924480084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
924480084
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2228356726
Short name T15
Test name
Test status
Simulation time 79069830737 ps
CPU time 47.19 seconds
Started Jul 04 07:05:35 PM PDT 24
Finished Jul 04 07:06:22 PM PDT 24
Peak memory 202020 kb
Host smart-8d7a5723-b7f4-4db6-b6a6-f68a6e853ed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228356726 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2228356726
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2107181549
Short name T605
Test name
Test status
Simulation time 350098573 ps
CPU time 1.06 seconds
Started Jul 04 07:05:50 PM PDT 24
Finished Jul 04 07:05:52 PM PDT 24
Peak memory 201672 kb
Host smart-88d9aaac-7e29-4a8e-a358-9c7684b2b748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107181549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2107181549
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2934254024
Short name T344
Test name
Test status
Simulation time 163215349208 ps
CPU time 107.04 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:07:31 PM PDT 24
Peak memory 201988 kb
Host smart-94e3dcac-6c27-411d-9642-63865d6c4e00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934254024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2934254024
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2409479549
Short name T4
Test name
Test status
Simulation time 323432664639 ps
CPU time 190.24 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:08:55 PM PDT 24
Peak memory 201924 kb
Host smart-7434c8fc-57ac-4baf-8f23-d2de346b596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409479549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2409479549
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3543601339
Short name T789
Test name
Test status
Simulation time 166354050311 ps
CPU time 382.39 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:12:07 PM PDT 24
Peak memory 201892 kb
Host smart-229cac4d-9cae-4b18-9c58-ab15b2abc53f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543601339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3543601339
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3583220798
Short name T760
Test name
Test status
Simulation time 324184192520 ps
CPU time 90.49 seconds
Started Jul 04 07:05:35 PM PDT 24
Finished Jul 04 07:07:06 PM PDT 24
Peak memory 201888 kb
Host smart-222230db-4c44-4a83-b47f-1388867ee458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583220798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3583220798
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1349908696
Short name T30
Test name
Test status
Simulation time 163709675158 ps
CPU time 172.46 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:08:37 PM PDT 24
Peak memory 201968 kb
Host smart-61e4c452-7f76-482b-b836-3eede80b6a24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349908696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1349908696
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2498353809
Short name T746
Test name
Test status
Simulation time 512393805403 ps
CPU time 309.04 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:10:53 PM PDT 24
Peak memory 201972 kb
Host smart-a1bbb9ba-c485-431a-a792-96217a230f1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498353809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2498353809
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.601707727
Short name T614
Test name
Test status
Simulation time 597424820292 ps
CPU time 1424.47 seconds
Started Jul 04 07:05:45 PM PDT 24
Finished Jul 04 07:29:30 PM PDT 24
Peak memory 201956 kb
Host smart-b531a576-025d-4d23-b271-e74fac97bffb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601707727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.601707727
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.154493851
Short name T216
Test name
Test status
Simulation time 115838730583 ps
CPU time 421.39 seconds
Started Jul 04 07:05:44 PM PDT 24
Finished Jul 04 07:12:45 PM PDT 24
Peak memory 202220 kb
Host smart-fe3c6c98-7776-4fe6-b93f-bd391062bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154493851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.154493851
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.91010683
Short name T510
Test name
Test status
Simulation time 41629508492 ps
CPU time 48.93 seconds
Started Jul 04 07:05:45 PM PDT 24
Finished Jul 04 07:06:34 PM PDT 24
Peak memory 201728 kb
Host smart-9cf0b927-07a1-46b5-b873-1522b90e923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91010683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.91010683
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2824921847
Short name T1
Test name
Test status
Simulation time 3300347857 ps
CPU time 9.17 seconds
Started Jul 04 07:05:45 PM PDT 24
Finished Jul 04 07:05:54 PM PDT 24
Peak memory 201732 kb
Host smart-c9a032fc-1ebb-42b5-83b9-4475eb2c9fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824921847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2824921847
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.60430511
Short name T394
Test name
Test status
Simulation time 6082987349 ps
CPU time 4.63 seconds
Started Jul 04 07:05:35 PM PDT 24
Finished Jul 04 07:05:40 PM PDT 24
Peak memory 201712 kb
Host smart-168fcbcf-90ef-4967-a03c-6e959b0e9aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60430511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.60430511
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1786985038
Short name T744
Test name
Test status
Simulation time 49639829812 ps
CPU time 67.74 seconds
Started Jul 04 07:05:45 PM PDT 24
Finished Jul 04 07:06:52 PM PDT 24
Peak memory 210508 kb
Host smart-296a7d4a-91d4-4747-be9b-2a63c87ec586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786985038 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1786985038
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2463580831
Short name T462
Test name
Test status
Simulation time 288822448 ps
CPU time 1.26 seconds
Started Jul 04 07:06:04 PM PDT 24
Finished Jul 04 07:06:05 PM PDT 24
Peak memory 201664 kb
Host smart-5c067e7b-4ae7-4bf1-b4b2-e95cf7db8b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463580831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2463580831
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3654511800
Short name T600
Test name
Test status
Simulation time 180579192892 ps
CPU time 386.04 seconds
Started Jul 04 07:05:56 PM PDT 24
Finished Jul 04 07:12:22 PM PDT 24
Peak memory 201912 kb
Host smart-06ccc55e-6dc2-4176-9d8d-297b82b332ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654511800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3654511800
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3837772551
Short name T308
Test name
Test status
Simulation time 592779096319 ps
CPU time 356.55 seconds
Started Jul 04 07:05:57 PM PDT 24
Finished Jul 04 07:11:54 PM PDT 24
Peak memory 201956 kb
Host smart-ba4e7c19-72db-4729-a0e0-9d0f7f178703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837772551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3837772551
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1875292278
Short name T191
Test name
Test status
Simulation time 492478846222 ps
CPU time 1078.99 seconds
Started Jul 04 07:05:51 PM PDT 24
Finished Jul 04 07:23:50 PM PDT 24
Peak memory 201916 kb
Host smart-43c990f8-16ba-4136-a3c1-bc4f71401722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875292278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1875292278
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.133739077
Short name T642
Test name
Test status
Simulation time 487345594359 ps
CPU time 658.71 seconds
Started Jul 04 07:05:50 PM PDT 24
Finished Jul 04 07:16:49 PM PDT 24
Peak memory 201884 kb
Host smart-9a9b0500-d8f7-4b4e-b30e-8c8b4d8f839b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=133739077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.133739077
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2214985492
Short name T492
Test name
Test status
Simulation time 162704389136 ps
CPU time 199.28 seconds
Started Jul 04 07:05:53 PM PDT 24
Finished Jul 04 07:09:12 PM PDT 24
Peak memory 201920 kb
Host smart-b74ca3b9-c1f3-4632-bd37-0e50853bc6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214985492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2214985492
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3628530039
Short name T88
Test name
Test status
Simulation time 323583977108 ps
CPU time 363.87 seconds
Started Jul 04 07:05:53 PM PDT 24
Finished Jul 04 07:11:57 PM PDT 24
Peak memory 201920 kb
Host smart-9e7faaed-6739-40f8-b808-7d7bd78a5e51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628530039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3628530039
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2606849699
Short name T33
Test name
Test status
Simulation time 364769062207 ps
CPU time 422.73 seconds
Started Jul 04 07:05:51 PM PDT 24
Finished Jul 04 07:12:54 PM PDT 24
Peak memory 201960 kb
Host smart-ae4b4193-5884-438c-b0ee-1aed732e83dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606849699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2606849699
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1670808369
Short name T397
Test name
Test status
Simulation time 596173808804 ps
CPU time 1265.84 seconds
Started Jul 04 07:05:56 PM PDT 24
Finished Jul 04 07:27:02 PM PDT 24
Peak memory 201968 kb
Host smart-db642654-d07c-49bc-bf31-63e53cbedad2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670808369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1670808369
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.614420353
Short name T715
Test name
Test status
Simulation time 93516378254 ps
CPU time 295.74 seconds
Started Jul 04 07:05:58 PM PDT 24
Finished Jul 04 07:10:54 PM PDT 24
Peak memory 202180 kb
Host smart-96782bc8-fe4b-4b70-af3c-a60225845cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614420353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.614420353
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3035834690
Short name T183
Test name
Test status
Simulation time 29601956825 ps
CPU time 14.13 seconds
Started Jul 04 07:05:57 PM PDT 24
Finished Jul 04 07:06:12 PM PDT 24
Peak memory 201704 kb
Host smart-a9bfaf71-b41a-4fc1-a116-0e0786544d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035834690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3035834690
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1774644922
Short name T450
Test name
Test status
Simulation time 4101433691 ps
CPU time 1.45 seconds
Started Jul 04 07:05:59 PM PDT 24
Finished Jul 04 07:06:00 PM PDT 24
Peak memory 201724 kb
Host smart-d3eee9f1-8d04-4940-92d3-2de73abf3636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774644922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1774644922
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2169122778
Short name T459
Test name
Test status
Simulation time 5945394367 ps
CPU time 7.21 seconds
Started Jul 04 07:05:49 PM PDT 24
Finished Jul 04 07:05:56 PM PDT 24
Peak memory 201748 kb
Host smart-e735fe87-7d0f-4068-a793-fdc5a010ac51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169122778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2169122778
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.497206543
Short name T708
Test name
Test status
Simulation time 171247086853 ps
CPU time 359.64 seconds
Started Jul 04 07:06:03 PM PDT 24
Finished Jul 04 07:12:03 PM PDT 24
Peak memory 201892 kb
Host smart-ff0c0d3b-5579-49dd-94c2-ebd7240beafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497206543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
497206543
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.147784974
Short name T670
Test name
Test status
Simulation time 407676672 ps
CPU time 1.13 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:00:21 PM PDT 24
Peak memory 201660 kb
Host smart-6e44d25b-67dd-4a74-90a2-fb669fda6602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147784974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.147784974
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2191548160
Short name T197
Test name
Test status
Simulation time 498640183360 ps
CPU time 632.86 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:10:50 PM PDT 24
Peak memory 201924 kb
Host smart-6ed4e04b-6bc9-4181-b38e-d42bdea77f3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191548160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2191548160
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2862130720
Short name T720
Test name
Test status
Simulation time 166958444427 ps
CPU time 92.16 seconds
Started Jul 04 07:00:16 PM PDT 24
Finished Jul 04 07:01:49 PM PDT 24
Peak memory 201908 kb
Host smart-e6cad7b2-2c4c-4939-a678-ba5c8e6c8a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862130720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2862130720
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2446855349
Short name T366
Test name
Test status
Simulation time 494424463047 ps
CPU time 1122.63 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:19:00 PM PDT 24
Peak memory 201908 kb
Host smart-cee8819d-e68a-4aee-97b9-e00c559d9250
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446855349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2446855349
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3785615856
Short name T778
Test name
Test status
Simulation time 167421376622 ps
CPU time 371.25 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:06:30 PM PDT 24
Peak memory 202004 kb
Host smart-c7a93d03-9f5f-418b-af51-25f9c4bd9a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785615856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3785615856
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3590912859
Short name T443
Test name
Test status
Simulation time 167804971805 ps
CPU time 83.02 seconds
Started Jul 04 07:00:16 PM PDT 24
Finished Jul 04 07:01:40 PM PDT 24
Peak memory 201968 kb
Host smart-b7d6e9df-5764-403d-8d79-f12b8e82fa16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590912859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3590912859
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.955125344
Short name T695
Test name
Test status
Simulation time 359598706360 ps
CPU time 874.84 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:14:54 PM PDT 24
Peak memory 201776 kb
Host smart-df08f0af-1b80-438a-b70a-75549caf1df0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955125344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.955125344
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1540887642
Short name T169
Test name
Test status
Simulation time 616739255322 ps
CPU time 322.15 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:05:42 PM PDT 24
Peak memory 201940 kb
Host smart-bcd46288-ebad-4aa1-91cb-47ae119071d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540887642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1540887642
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.163557116
Short name T215
Test name
Test status
Simulation time 134929556203 ps
CPU time 715.16 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:12:13 PM PDT 24
Peak memory 202236 kb
Host smart-f41cc7ad-ab23-4cc4-b001-1afe41d8a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163557116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.163557116
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2523686414
Short name T491
Test name
Test status
Simulation time 32268106112 ps
CPU time 17.75 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:00:35 PM PDT 24
Peak memory 201728 kb
Host smart-7233fe69-6efe-460e-8a71-953f04228e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523686414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2523686414
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.196059340
Short name T370
Test name
Test status
Simulation time 5371690120 ps
CPU time 12.43 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:00:31 PM PDT 24
Peak memory 201680 kb
Host smart-de37537c-9f65-46b6-957a-7721a200e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196059340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.196059340
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2107994755
Short name T73
Test name
Test status
Simulation time 8787174784 ps
CPU time 4.16 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:00:23 PM PDT 24
Peak memory 218192 kb
Host smart-bcd48c31-59a0-4979-857d-919f172e97e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107994755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2107994755
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2603698480
Short name T684
Test name
Test status
Simulation time 5879204978 ps
CPU time 15.5 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:00:32 PM PDT 24
Peak memory 201720 kb
Host smart-04aa2d86-052b-4cbc-be90-4253808e3176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603698480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2603698480
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2919085898
Short name T512
Test name
Test status
Simulation time 6694989552 ps
CPU time 14 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:00:32 PM PDT 24
Peak memory 201704 kb
Host smart-d80124c3-bae6-40e3-a018-7b7302a198c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919085898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2919085898
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3156821847
Short name T420
Test name
Test status
Simulation time 529052506 ps
CPU time 1.78 seconds
Started Jul 04 07:06:11 PM PDT 24
Finished Jul 04 07:06:13 PM PDT 24
Peak memory 201620 kb
Host smart-de65c514-e9b1-4997-b8a4-869a5c11950a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156821847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3156821847
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4145594845
Short name T634
Test name
Test status
Simulation time 502676862344 ps
CPU time 1029.23 seconds
Started Jul 04 07:06:09 PM PDT 24
Finished Jul 04 07:23:19 PM PDT 24
Peak memory 201896 kb
Host smart-ac0ffe2a-973f-4215-8d7a-2221f2da0083
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145594845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4145594845
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.310544085
Short name T585
Test name
Test status
Simulation time 177674563764 ps
CPU time 105.16 seconds
Started Jul 04 07:06:09 PM PDT 24
Finished Jul 04 07:07:54 PM PDT 24
Peak memory 202024 kb
Host smart-5c9616c1-d102-4295-8be9-bdde0f172f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310544085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.310544085
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2844847472
Short name T453
Test name
Test status
Simulation time 490871584434 ps
CPU time 1078.47 seconds
Started Jul 04 07:06:04 PM PDT 24
Finished Jul 04 07:24:03 PM PDT 24
Peak memory 201916 kb
Host smart-870de741-e2ac-4057-bc3f-5168a8fc8162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844847472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2844847472
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2287938379
Short name T790
Test name
Test status
Simulation time 478306301884 ps
CPU time 313.35 seconds
Started Jul 04 07:06:11 PM PDT 24
Finished Jul 04 07:11:25 PM PDT 24
Peak memory 201872 kb
Host smart-3ce17f9f-1eb8-404d-8c38-9e567f94428b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287938379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2287938379
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.864357321
Short name T235
Test name
Test status
Simulation time 163560831342 ps
CPU time 46.55 seconds
Started Jul 04 07:06:04 PM PDT 24
Finished Jul 04 07:06:51 PM PDT 24
Peak memory 201904 kb
Host smart-085c9df8-f0dc-43c6-9e94-f337d38e008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864357321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.864357321
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2672221354
Short name T417
Test name
Test status
Simulation time 167037768264 ps
CPU time 26.64 seconds
Started Jul 04 07:06:04 PM PDT 24
Finished Jul 04 07:06:31 PM PDT 24
Peak memory 201912 kb
Host smart-db5c308d-f909-4768-8e58-f26fb4e379f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672221354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2672221354
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2343264097
Short name T304
Test name
Test status
Simulation time 371896700955 ps
CPU time 432.59 seconds
Started Jul 04 07:06:09 PM PDT 24
Finished Jul 04 07:13:22 PM PDT 24
Peak memory 201964 kb
Host smart-5d9b0ada-47ff-4f5c-906f-4070cc3c2192
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343264097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2343264097
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4203136403
Short name T774
Test name
Test status
Simulation time 393533214877 ps
CPU time 461.4 seconds
Started Jul 04 07:06:10 PM PDT 24
Finished Jul 04 07:13:52 PM PDT 24
Peak memory 201920 kb
Host smart-918f3cc0-4cc3-4f31-97f5-d4263d7449ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203136403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4203136403
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2263783117
Short name T629
Test name
Test status
Simulation time 82350363429 ps
CPU time 306.64 seconds
Started Jul 04 07:06:11 PM PDT 24
Finished Jul 04 07:11:18 PM PDT 24
Peak memory 202264 kb
Host smart-50f4f296-9592-4cf2-9fdf-308ac57b11a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263783117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2263783117
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4026828508
Short name T553
Test name
Test status
Simulation time 31788173615 ps
CPU time 18.98 seconds
Started Jul 04 07:06:10 PM PDT 24
Finished Jul 04 07:06:29 PM PDT 24
Peak memory 201696 kb
Host smart-5e0dd304-bdd3-41f9-b57b-b747231d16ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026828508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4026828508
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2731785982
Short name T434
Test name
Test status
Simulation time 5641030668 ps
CPU time 3.89 seconds
Started Jul 04 07:06:10 PM PDT 24
Finished Jul 04 07:06:14 PM PDT 24
Peak memory 201740 kb
Host smart-75fe64b6-2b35-4f4a-bc58-943c61d1d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731785982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2731785982
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2700150912
Short name T717
Test name
Test status
Simulation time 6020770607 ps
CPU time 2.49 seconds
Started Jul 04 07:06:05 PM PDT 24
Finished Jul 04 07:06:07 PM PDT 24
Peak memory 201728 kb
Host smart-a0a76fb9-3692-4e82-9d01-03de299928d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700150912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2700150912
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1714961838
Short name T351
Test name
Test status
Simulation time 58509628304 ps
CPU time 134.19 seconds
Started Jul 04 07:06:10 PM PDT 24
Finished Jul 04 07:08:25 PM PDT 24
Peak memory 202080 kb
Host smart-b6760724-3bc1-48e8-b53e-78c6d57a0564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714961838 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1714961838
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1407949055
Short name T389
Test name
Test status
Simulation time 436457624 ps
CPU time 0.68 seconds
Started Jul 04 07:06:16 PM PDT 24
Finished Jul 04 07:06:17 PM PDT 24
Peak memory 201672 kb
Host smart-fc383137-d449-4fa7-bd84-802a0d2efade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407949055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1407949055
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2904931793
Short name T254
Test name
Test status
Simulation time 531623572386 ps
CPU time 1180.73 seconds
Started Jul 04 07:06:17 PM PDT 24
Finished Jul 04 07:25:58 PM PDT 24
Peak memory 201884 kb
Host smart-870c2e08-2d63-4999-963a-7ee15bc6d092
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904931793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2904931793
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1268936888
Short name T329
Test name
Test status
Simulation time 359454706455 ps
CPU time 396.83 seconds
Started Jul 04 07:06:16 PM PDT 24
Finished Jul 04 07:12:53 PM PDT 24
Peak memory 201932 kb
Host smart-44b0d226-8f4d-474e-9bd0-39415f9cfabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268936888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1268936888
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.596221227
Short name T32
Test name
Test status
Simulation time 336697626656 ps
CPU time 739.15 seconds
Started Jul 04 07:06:19 PM PDT 24
Finished Jul 04 07:18:38 PM PDT 24
Peak memory 201964 kb
Host smart-6ceaef54-d932-4a24-9b55-73016a68cb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596221227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.596221227
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2877239674
Short name T449
Test name
Test status
Simulation time 329904426993 ps
CPU time 813.74 seconds
Started Jul 04 07:06:18 PM PDT 24
Finished Jul 04 07:19:52 PM PDT 24
Peak memory 201880 kb
Host smart-1b72ee8a-07bc-4a79-b3c8-8210c0c36703
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877239674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2877239674
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3530692129
Short name T299
Test name
Test status
Simulation time 485198742117 ps
CPU time 1055.27 seconds
Started Jul 04 07:06:18 PM PDT 24
Finished Jul 04 07:23:53 PM PDT 24
Peak memory 201976 kb
Host smart-83a64562-47b0-451a-aba9-bfc52dd8150e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530692129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3530692129
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.420077331
Short name T156
Test name
Test status
Simulation time 314911543784 ps
CPU time 194.84 seconds
Started Jul 04 07:06:18 PM PDT 24
Finished Jul 04 07:09:33 PM PDT 24
Peak memory 201928 kb
Host smart-b5a9e60d-4fba-47ec-8755-7e35c48830ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=420077331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.420077331
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.261452728
Short name T334
Test name
Test status
Simulation time 528323018171 ps
CPU time 111.03 seconds
Started Jul 04 07:06:18 PM PDT 24
Finished Jul 04 07:08:09 PM PDT 24
Peak memory 202024 kb
Host smart-578189c3-ae85-4cbb-a854-efff011b280f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261452728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.261452728
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1988112441
Short name T606
Test name
Test status
Simulation time 598033522621 ps
CPU time 1407.6 seconds
Started Jul 04 07:06:18 PM PDT 24
Finished Jul 04 07:29:46 PM PDT 24
Peak memory 201904 kb
Host smart-48b2a8f2-ef07-4fc1-aba0-2fb3c2895e36
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988112441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1988112441
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1385098992
Short name T221
Test name
Test status
Simulation time 80902223894 ps
CPU time 419.26 seconds
Started Jul 04 07:06:17 PM PDT 24
Finished Jul 04 07:13:16 PM PDT 24
Peak memory 202204 kb
Host smart-4608899f-8bdd-4c8e-bd9e-63888874b9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385098992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1385098992
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.818026596
Short name T412
Test name
Test status
Simulation time 40039457675 ps
CPU time 21.68 seconds
Started Jul 04 07:06:15 PM PDT 24
Finished Jul 04 07:06:37 PM PDT 24
Peak memory 201732 kb
Host smart-323f5071-9385-4cd0-b9d6-26dc10902e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818026596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.818026596
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1823594651
Short name T155
Test name
Test status
Simulation time 3498214858 ps
CPU time 8.9 seconds
Started Jul 04 07:06:17 PM PDT 24
Finished Jul 04 07:06:26 PM PDT 24
Peak memory 201716 kb
Host smart-5efc2163-7f5f-4006-b0fc-4f5fa38e5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823594651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1823594651
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1698566900
Short name T381
Test name
Test status
Simulation time 5566234504 ps
CPU time 11.68 seconds
Started Jul 04 07:06:17 PM PDT 24
Finished Jul 04 07:06:29 PM PDT 24
Peak memory 201740 kb
Host smart-cf979a4c-34ac-48d5-9e4c-48d262248daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698566900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1698566900
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2939219790
Short name T21
Test name
Test status
Simulation time 87176364165 ps
CPU time 48.46 seconds
Started Jul 04 07:06:18 PM PDT 24
Finished Jul 04 07:07:06 PM PDT 24
Peak memory 202108 kb
Host smart-75e98d54-2c48-49be-bcb7-d9d6b03aac76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939219790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2939219790
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.650857783
Short name T763
Test name
Test status
Simulation time 502611613 ps
CPU time 1.16 seconds
Started Jul 04 07:06:33 PM PDT 24
Finished Jul 04 07:06:49 PM PDT 24
Peak memory 201684 kb
Host smart-2c9ff5c8-5bd8-4ac1-b266-e0bd519c776d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650857783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.650857783
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2343127200
Short name T154
Test name
Test status
Simulation time 330129914338 ps
CPU time 731.77 seconds
Started Jul 04 07:06:32 PM PDT 24
Finished Jul 04 07:18:57 PM PDT 24
Peak memory 201932 kb
Host smart-bf87815b-60f4-4020-9961-c6f2ad486cff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343127200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2343127200
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2578221275
Short name T274
Test name
Test status
Simulation time 335108927056 ps
CPU time 275.91 seconds
Started Jul 04 07:06:33 PM PDT 24
Finished Jul 04 07:11:23 PM PDT 24
Peak memory 201968 kb
Host smart-4132dfbd-51d8-4762-b8f3-f0fc07f23264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578221275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2578221275
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1137110088
Short name T348
Test name
Test status
Simulation time 164814095020 ps
CPU time 179.95 seconds
Started Jul 04 07:06:26 PM PDT 24
Finished Jul 04 07:09:28 PM PDT 24
Peak memory 201908 kb
Host smart-f3a6e435-dd64-4b12-813b-50fdc52cf8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137110088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1137110088
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1076932244
Short name T167
Test name
Test status
Simulation time 500585905703 ps
CPU time 1090.78 seconds
Started Jul 04 07:06:25 PM PDT 24
Finished Jul 04 07:24:37 PM PDT 24
Peak memory 201904 kb
Host smart-33bb5047-e68e-43f0-b5cc-981fb3633142
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076932244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1076932244
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.277061904
Short name T263
Test name
Test status
Simulation time 160176872908 ps
CPU time 189.5 seconds
Started Jul 04 07:06:27 PM PDT 24
Finished Jul 04 07:09:38 PM PDT 24
Peak memory 201916 kb
Host smart-a4bef6e1-35e5-439f-a1ff-4eba8ff253fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277061904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.277061904
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2274231502
Short name T388
Test name
Test status
Simulation time 164183455457 ps
CPU time 193.77 seconds
Started Jul 04 07:06:25 PM PDT 24
Finished Jul 04 07:09:40 PM PDT 24
Peak memory 201980 kb
Host smart-9cdd9260-50f0-4f8a-8f8d-b3f980dc2336
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274231502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2274231502
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3282228835
Short name T431
Test name
Test status
Simulation time 210656378718 ps
CPU time 238.76 seconds
Started Jul 04 07:06:26 PM PDT 24
Finished Jul 04 07:10:26 PM PDT 24
Peak memory 201880 kb
Host smart-3c716d72-f937-41bb-8e9e-83a542413bd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282228835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3282228835
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2057350092
Short name T358
Test name
Test status
Simulation time 99003159522 ps
CPU time 519.1 seconds
Started Jul 04 07:06:33 PM PDT 24
Finished Jul 04 07:15:27 PM PDT 24
Peak memory 202208 kb
Host smart-8da4e31e-9baa-42ae-9a2b-cdebb8433cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057350092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2057350092
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3253675968
Short name T599
Test name
Test status
Simulation time 26485435161 ps
CPU time 55.16 seconds
Started Jul 04 07:06:35 PM PDT 24
Finished Jul 04 07:07:46 PM PDT 24
Peak memory 201732 kb
Host smart-eec73fcb-3c67-4acb-a1d2-f9ef039f3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253675968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3253675968
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1481119605
Short name T481
Test name
Test status
Simulation time 2910254686 ps
CPU time 2.34 seconds
Started Jul 04 07:06:32 PM PDT 24
Finished Jul 04 07:06:47 PM PDT 24
Peak memory 201740 kb
Host smart-fe2cc277-bf05-44f6-9157-feb9216049ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481119605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1481119605
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2378663376
Short name T419
Test name
Test status
Simulation time 5907057415 ps
CPU time 13.67 seconds
Started Jul 04 07:06:17 PM PDT 24
Finished Jul 04 07:06:31 PM PDT 24
Peak memory 201720 kb
Host smart-8015f5f9-f0da-4703-aa8a-88c87e0ea38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378663376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2378663376
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.949436184
Short name T347
Test name
Test status
Simulation time 537031179951 ps
CPU time 189.18 seconds
Started Jul 04 07:06:35 PM PDT 24
Finished Jul 04 07:10:00 PM PDT 24
Peak memory 201972 kb
Host smart-1b70a1e7-bd55-4540-b925-5f521788b833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949436184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
949436184
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1165165019
Short name T18
Test name
Test status
Simulation time 197393063492 ps
CPU time 149.95 seconds
Started Jul 04 07:06:32 PM PDT 24
Finished Jul 04 07:09:15 PM PDT 24
Peak memory 210596 kb
Host smart-218c4026-ef9e-4f46-a7c3-9cefcba34186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165165019 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1165165019
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2058414003
Short name T691
Test name
Test status
Simulation time 533124774 ps
CPU time 1.2 seconds
Started Jul 04 07:06:40 PM PDT 24
Finished Jul 04 07:06:58 PM PDT 24
Peak memory 201528 kb
Host smart-717f5613-61ef-435e-aada-8ca80337b6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058414003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2058414003
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.441053331
Short name T349
Test name
Test status
Simulation time 495246180680 ps
CPU time 295.47 seconds
Started Jul 04 07:06:36 PM PDT 24
Finished Jul 04 07:11:47 PM PDT 24
Peak memory 201992 kb
Host smart-13f6341a-ded6-4689-978b-62405c509361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441053331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.441053331
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.4145138106
Short name T14
Test name
Test status
Simulation time 161694851035 ps
CPU time 106.45 seconds
Started Jul 04 07:06:38 PM PDT 24
Finished Jul 04 07:08:40 PM PDT 24
Peak memory 201912 kb
Host smart-96aa6cd6-58d6-4675-a6c2-f52c615a2d4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145138106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.4145138106
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3161535618
Short name T470
Test name
Test status
Simulation time 164340871941 ps
CPU time 362.73 seconds
Started Jul 04 07:06:32 PM PDT 24
Finished Jul 04 07:12:48 PM PDT 24
Peak memory 201984 kb
Host smart-2cb0bb7e-0164-4193-9d7e-ec8a053b86bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161535618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3161535618
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.88718869
Short name T702
Test name
Test status
Simulation time 493246295437 ps
CPU time 138.96 seconds
Started Jul 04 07:06:33 PM PDT 24
Finished Jul 04 07:09:07 PM PDT 24
Peak memory 201900 kb
Host smart-6454950a-765e-4627-ba5a-0768e84403c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=88718869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed
.88718869
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.700711974
Short name T588
Test name
Test status
Simulation time 635824491094 ps
CPU time 719.94 seconds
Started Jul 04 07:06:38 PM PDT 24
Finished Jul 04 07:18:54 PM PDT 24
Peak memory 201924 kb
Host smart-f2afe8c8-fe1b-4ea5-ba10-7d19bc6b9dc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700711974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.700711974
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.91784485
Short name T399
Test name
Test status
Simulation time 611844723669 ps
CPU time 353.24 seconds
Started Jul 04 07:06:37 PM PDT 24
Finished Jul 04 07:12:47 PM PDT 24
Peak memory 201920 kb
Host smart-97c90fab-e2cc-4ff7-bd11-cc8fce9d2c14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91784485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
dc_ctrl_filters_wakeup_fixed.91784485
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.122813503
Short name T217
Test name
Test status
Simulation time 79336107591 ps
CPU time 343.89 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:12:38 PM PDT 24
Peak memory 202220 kb
Host smart-727c5c9c-094a-4595-b694-5fe588d6e0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122813503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.122813503
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.669225305
Short name T589
Test name
Test status
Simulation time 22667075468 ps
CPU time 25.5 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:07:20 PM PDT 24
Peak memory 201728 kb
Host smart-23723215-4d55-4cf1-9f2d-22b3506d2115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669225305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.669225305
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1952046768
Short name T194
Test name
Test status
Simulation time 3528298298 ps
CPU time 8.54 seconds
Started Jul 04 07:06:40 PM PDT 24
Finished Jul 04 07:07:05 PM PDT 24
Peak memory 201536 kb
Host smart-19eb9a65-2a84-4752-893b-90e0c3aadce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952046768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1952046768
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3099694728
Short name T474
Test name
Test status
Simulation time 5971018301 ps
CPU time 14.88 seconds
Started Jul 04 07:06:33 PM PDT 24
Finished Jul 04 07:07:01 PM PDT 24
Peak memory 201744 kb
Host smart-5ca28029-3f00-49b2-8648-bdaa96e274ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099694728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3099694728
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3740753619
Short name T751
Test name
Test status
Simulation time 489439704289 ps
CPU time 1066.89 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:24:41 PM PDT 24
Peak memory 201888 kb
Host smart-6865508c-632a-4363-92b0-875f539e5e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740753619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3740753619
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3478041911
Short name T277
Test name
Test status
Simulation time 55770160158 ps
CPU time 35.15 seconds
Started Jul 04 07:06:40 PM PDT 24
Finished Jul 04 07:07:31 PM PDT 24
Peak memory 202024 kb
Host smart-a264d7fa-e0d6-4e3a-8562-384162e1c1d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478041911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3478041911
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.388721846
Short name T779
Test name
Test status
Simulation time 339588314 ps
CPU time 0.82 seconds
Started Jul 04 07:06:53 PM PDT 24
Finished Jul 04 07:07:01 PM PDT 24
Peak memory 201632 kb
Host smart-302ad56d-8737-4d45-9a7f-2aedd82b674c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388721846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.388721846
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3450806897
Short name T529
Test name
Test status
Simulation time 162195699177 ps
CPU time 80.71 seconds
Started Jul 04 07:06:46 PM PDT 24
Finished Jul 04 07:08:20 PM PDT 24
Peak memory 201928 kb
Host smart-69af2f99-9076-4a84-aa87-e91899e49b65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450806897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3450806897
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2207729616
Short name T286
Test name
Test status
Simulation time 345497689418 ps
CPU time 474.66 seconds
Started Jul 04 07:06:47 PM PDT 24
Finished Jul 04 07:14:54 PM PDT 24
Peak memory 201900 kb
Host smart-fadce9e6-7865-475c-ab47-85dd3b188aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207729616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2207729616
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.642085006
Short name T780
Test name
Test status
Simulation time 156978333877 ps
CPU time 29.28 seconds
Started Jul 04 07:06:41 PM PDT 24
Finished Jul 04 07:07:27 PM PDT 24
Peak memory 201936 kb
Host smart-cef65476-a895-410d-8a3e-98ae8e40ba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642085006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.642085006
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4175395165
Short name T502
Test name
Test status
Simulation time 492299937843 ps
CPU time 288.14 seconds
Started Jul 04 07:06:45 PM PDT 24
Finished Jul 04 07:11:47 PM PDT 24
Peak memory 201892 kb
Host smart-a63a7a39-6799-4c9a-80e7-e2d591e6cdd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175395165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.4175395165
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2155978499
Short name T258
Test name
Test status
Simulation time 329825918950 ps
CPU time 220.07 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:10:35 PM PDT 24
Peak memory 201904 kb
Host smart-734ace62-76e8-4940-8ef5-c1cba611244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155978499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2155978499
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3695994623
Short name T27
Test name
Test status
Simulation time 325443761904 ps
CPU time 61.06 seconds
Started Jul 04 07:06:39 PM PDT 24
Finished Jul 04 07:07:56 PM PDT 24
Peak memory 201980 kb
Host smart-6d4cc86b-c92c-4e0f-99d7-17cf6bf6b43a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695994623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3695994623
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3211293979
Short name T278
Test name
Test status
Simulation time 172300767386 ps
CPU time 347.35 seconds
Started Jul 04 07:06:45 PM PDT 24
Finished Jul 04 07:12:46 PM PDT 24
Peak memory 201948 kb
Host smart-5dbb4dfb-94c0-494d-8bca-3311cfea76ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211293979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3211293979
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2107181306
Short name T52
Test name
Test status
Simulation time 205484164668 ps
CPU time 491.69 seconds
Started Jul 04 07:06:45 PM PDT 24
Finished Jul 04 07:15:11 PM PDT 24
Peak memory 201900 kb
Host smart-b65b9219-1284-431b-afc5-ff5e9da71078
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107181306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2107181306
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.775069627
Short name T709
Test name
Test status
Simulation time 132945022509 ps
CPU time 725.69 seconds
Started Jul 04 07:06:52 PM PDT 24
Finished Jul 04 07:19:06 PM PDT 24
Peak memory 202208 kb
Host smart-7cb3db93-168e-434d-99a9-6a99d49e4f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775069627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.775069627
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3242077891
Short name T735
Test name
Test status
Simulation time 35456774735 ps
CPU time 29.86 seconds
Started Jul 04 07:06:45 PM PDT 24
Finished Jul 04 07:07:29 PM PDT 24
Peak memory 201672 kb
Host smart-d82e07c1-1757-4ae2-a189-e6464960ad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242077891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3242077891
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2564824802
Short name T560
Test name
Test status
Simulation time 4828423548 ps
CPU time 3.33 seconds
Started Jul 04 07:06:45 PM PDT 24
Finished Jul 04 07:07:02 PM PDT 24
Peak memory 201740 kb
Host smart-99a668f6-4ad5-4f31-ba83-3a6dd07762ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564824802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2564824802
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1439741346
Short name T596
Test name
Test status
Simulation time 5760433094 ps
CPU time 3.22 seconds
Started Jul 04 07:06:40 PM PDT 24
Finished Jul 04 07:06:59 PM PDT 24
Peak memory 201660 kb
Host smart-384a62e2-2460-4650-a77a-99ccde0d305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439741346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1439741346
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1497878585
Short name T60
Test name
Test status
Simulation time 288758260961 ps
CPU time 538.82 seconds
Started Jul 04 07:06:53 PM PDT 24
Finished Jul 04 07:15:59 PM PDT 24
Peak memory 202284 kb
Host smart-77afa76a-f6e3-433d-9fb2-64090918f3d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497878585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1497878585
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3220289254
Short name T16
Test name
Test status
Simulation time 32397601547 ps
CPU time 56.9 seconds
Started Jul 04 07:06:53 PM PDT 24
Finished Jul 04 07:07:57 PM PDT 24
Peak memory 210600 kb
Host smart-6f479cf8-984a-4e59-a92a-617d71a0cf02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220289254 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3220289254
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2819350484
Short name T638
Test name
Test status
Simulation time 442072340 ps
CPU time 1.18 seconds
Started Jul 04 07:07:10 PM PDT 24
Finished Jul 04 07:07:11 PM PDT 24
Peak memory 201688 kb
Host smart-6a176dd1-eb44-4b63-a5a0-6efdb61af628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819350484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2819350484
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2220863926
Short name T264
Test name
Test status
Simulation time 331152803149 ps
CPU time 727.94 seconds
Started Jul 04 07:07:00 PM PDT 24
Finished Jul 04 07:19:09 PM PDT 24
Peak memory 201888 kb
Host smart-c6f482a8-65c6-4d56-8fd0-d1622d291b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220863926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2220863926
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3752874565
Short name T477
Test name
Test status
Simulation time 490327390250 ps
CPU time 1061.31 seconds
Started Jul 04 07:07:02 PM PDT 24
Finished Jul 04 07:24:44 PM PDT 24
Peak memory 201912 kb
Host smart-7bbccd56-56a8-43b7-96be-c63cea0fe86a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752874565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3752874565
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3070632984
Short name T313
Test name
Test status
Simulation time 162875338975 ps
CPU time 33.01 seconds
Started Jul 04 07:07:02 PM PDT 24
Finished Jul 04 07:07:35 PM PDT 24
Peak memory 201912 kb
Host smart-91dff409-90d1-4494-8a74-75fbc048a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070632984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3070632984
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2167390448
Short name T393
Test name
Test status
Simulation time 499634662618 ps
CPU time 288.73 seconds
Started Jul 04 07:07:00 PM PDT 24
Finished Jul 04 07:11:49 PM PDT 24
Peak memory 201916 kb
Host smart-4479791a-eca7-4cfc-8520-4f983866bd5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167390448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2167390448
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1909598112
Short name T202
Test name
Test status
Simulation time 534621323425 ps
CPU time 330.86 seconds
Started Jul 04 07:07:02 PM PDT 24
Finished Jul 04 07:12:33 PM PDT 24
Peak memory 201932 kb
Host smart-1ef84e28-5af1-4b9d-9a3a-18f8b5583cd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909598112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1909598112
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2740990288
Short name T758
Test name
Test status
Simulation time 194856981968 ps
CPU time 109.93 seconds
Started Jul 04 07:07:01 PM PDT 24
Finished Jul 04 07:08:51 PM PDT 24
Peak memory 201896 kb
Host smart-ff9dc2eb-fa58-4239-84c8-33b5cf37a63d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740990288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2740990288
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1602000585
Short name T193
Test name
Test status
Simulation time 125251388549 ps
CPU time 673.95 seconds
Started Jul 04 07:07:00 PM PDT 24
Finished Jul 04 07:18:15 PM PDT 24
Peak memory 202288 kb
Host smart-04bca39d-b4ce-410c-af04-e238d91983a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602000585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1602000585
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1143735889
Short name T490
Test name
Test status
Simulation time 38616875008 ps
CPU time 44.38 seconds
Started Jul 04 07:07:03 PM PDT 24
Finished Jul 04 07:07:48 PM PDT 24
Peak memory 201708 kb
Host smart-644d9244-3749-4d80-958a-b6547efee386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143735889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1143735889
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.397700549
Short name T680
Test name
Test status
Simulation time 3827983168 ps
CPU time 9.09 seconds
Started Jul 04 07:07:03 PM PDT 24
Finished Jul 04 07:07:12 PM PDT 24
Peak memory 201704 kb
Host smart-03d56849-67b0-4f2c-b250-ad7f346a9787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397700549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.397700549
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.833884276
Short name T484
Test name
Test status
Simulation time 5948724136 ps
CPU time 4.06 seconds
Started Jul 04 07:06:53 PM PDT 24
Finished Jul 04 07:07:04 PM PDT 24
Peak memory 201728 kb
Host smart-2109e629-e29e-4864-ad54-f552fee07b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833884276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.833884276
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3833440321
Short name T571
Test name
Test status
Simulation time 361315339187 ps
CPU time 307.02 seconds
Started Jul 04 07:07:08 PM PDT 24
Finished Jul 04 07:12:16 PM PDT 24
Peak memory 201852 kb
Host smart-ae7c82c3-4569-498d-8d13-ce61f1f99d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833440321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3833440321
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2110394309
Short name T655
Test name
Test status
Simulation time 55668436414 ps
CPU time 120.64 seconds
Started Jul 04 07:07:02 PM PDT 24
Finished Jul 04 07:09:02 PM PDT 24
Peak memory 210552 kb
Host smart-942f0c69-42a8-40ec-a52b-88dba4e150ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110394309 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2110394309
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1101133620
Short name T387
Test name
Test status
Simulation time 460236061 ps
CPU time 0.86 seconds
Started Jul 04 07:07:17 PM PDT 24
Finished Jul 04 07:07:18 PM PDT 24
Peak memory 201672 kb
Host smart-cecdef7d-628f-4670-a30a-6209e3d534a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101133620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1101133620
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1620124279
Short name T654
Test name
Test status
Simulation time 178434792905 ps
CPU time 192.1 seconds
Started Jul 04 07:07:09 PM PDT 24
Finished Jul 04 07:10:21 PM PDT 24
Peak memory 201984 kb
Host smart-0f1ffb82-9305-4b03-aad7-b3440e95e0da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620124279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1620124279
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1944177432
Short name T238
Test name
Test status
Simulation time 502861651732 ps
CPU time 334.46 seconds
Started Jul 04 07:07:10 PM PDT 24
Finished Jul 04 07:12:44 PM PDT 24
Peak memory 201948 kb
Host smart-bddca0bb-ab60-4402-8d67-c8e333e29736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944177432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1944177432
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3848427313
Short name T285
Test name
Test status
Simulation time 161610633369 ps
CPU time 63.32 seconds
Started Jul 04 07:07:11 PM PDT 24
Finished Jul 04 07:08:15 PM PDT 24
Peak memory 201964 kb
Host smart-d448efda-ab70-40b9-9f4b-54f229e320f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848427313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3848427313
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4055222166
Short name T482
Test name
Test status
Simulation time 163071727669 ps
CPU time 396.14 seconds
Started Jul 04 07:07:12 PM PDT 24
Finished Jul 04 07:13:48 PM PDT 24
Peak memory 201888 kb
Host smart-65f845ba-cd68-4a5a-90e8-03b6e80521e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055222166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4055222166
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3004571089
Short name T310
Test name
Test status
Simulation time 501698236789 ps
CPU time 441.09 seconds
Started Jul 04 07:07:11 PM PDT 24
Finished Jul 04 07:14:33 PM PDT 24
Peak memory 201908 kb
Host smart-0b7809e1-40a8-4db9-9e51-3d55a3cd6723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004571089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3004571089
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.683350478
Short name T743
Test name
Test status
Simulation time 488502472572 ps
CPU time 1114.52 seconds
Started Jul 04 07:07:10 PM PDT 24
Finished Jul 04 07:25:45 PM PDT 24
Peak memory 201980 kb
Host smart-2b5862f3-44c7-47dc-b9c9-07d1ac410ec9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=683350478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.683350478
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3867909679
Short name T316
Test name
Test status
Simulation time 643308859826 ps
CPU time 1437.33 seconds
Started Jul 04 07:07:09 PM PDT 24
Finished Jul 04 07:31:07 PM PDT 24
Peak memory 201956 kb
Host smart-06076e9d-b05f-45c6-a2e1-829085f154d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867909679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3867909679
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1077052231
Short name T391
Test name
Test status
Simulation time 610361776979 ps
CPU time 690.18 seconds
Started Jul 04 07:07:09 PM PDT 24
Finished Jul 04 07:18:40 PM PDT 24
Peak memory 201916 kb
Host smart-baa603d0-39e0-4e61-a17b-3b90e58e15a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077052231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1077052231
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1082828224
Short name T726
Test name
Test status
Simulation time 129116501115 ps
CPU time 505.18 seconds
Started Jul 04 07:07:18 PM PDT 24
Finished Jul 04 07:15:43 PM PDT 24
Peak memory 202220 kb
Host smart-f42c292d-36b6-48fc-b4f3-3e7a4347f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082828224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1082828224
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2677246686
Short name T361
Test name
Test status
Simulation time 25329008030 ps
CPU time 56 seconds
Started Jul 04 07:07:10 PM PDT 24
Finished Jul 04 07:08:06 PM PDT 24
Peak memory 201732 kb
Host smart-fb96ff72-e529-44eb-9f28-38089d508b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677246686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2677246686
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2467577375
Short name T390
Test name
Test status
Simulation time 3492957533 ps
CPU time 9.4 seconds
Started Jul 04 07:07:10 PM PDT 24
Finished Jul 04 07:07:20 PM PDT 24
Peak memory 201728 kb
Host smart-efdd3ca8-a13c-49c9-9179-029259664968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467577375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2467577375
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3129949291
Short name T546
Test name
Test status
Simulation time 5567794968 ps
CPU time 4.05 seconds
Started Jul 04 07:07:11 PM PDT 24
Finished Jul 04 07:07:15 PM PDT 24
Peak memory 201732 kb
Host smart-82fdc015-a5c7-4b35-a73c-6ddddedbf726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129949291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3129949291
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2729645652
Short name T354
Test name
Test status
Simulation time 389870552129 ps
CPU time 888.43 seconds
Started Jul 04 07:07:18 PM PDT 24
Finished Jul 04 07:22:06 PM PDT 24
Peak memory 202208 kb
Host smart-adf100ea-b9c3-49b2-82f7-b2765ff75005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729645652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2729645652
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2748904974
Short name T22
Test name
Test status
Simulation time 102972453260 ps
CPU time 207.47 seconds
Started Jul 04 07:07:18 PM PDT 24
Finished Jul 04 07:10:46 PM PDT 24
Peak memory 202144 kb
Host smart-2e41f96b-329d-48e3-8730-ca2f1d6cdb50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748904974 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2748904974
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2018229545
Short name T761
Test name
Test status
Simulation time 437690408 ps
CPU time 0.86 seconds
Started Jul 04 07:07:25 PM PDT 24
Finished Jul 04 07:07:27 PM PDT 24
Peak memory 201596 kb
Host smart-33aeb97e-7d26-4955-add5-43b33fe58bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018229545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2018229545
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.482539082
Short name T240
Test name
Test status
Simulation time 522958692549 ps
CPU time 245.59 seconds
Started Jul 04 07:07:17 PM PDT 24
Finished Jul 04 07:11:23 PM PDT 24
Peak memory 201916 kb
Host smart-58f2e979-8a3c-4527-85d3-94b5017ad4e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482539082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.482539082
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2918739625
Short name T276
Test name
Test status
Simulation time 173040293413 ps
CPU time 433.42 seconds
Started Jul 04 07:07:18 PM PDT 24
Finished Jul 04 07:14:32 PM PDT 24
Peak memory 201920 kb
Host smart-3a5e3b0a-9421-4cf4-9440-44dfadc99ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918739625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2918739625
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4126661872
Short name T618
Test name
Test status
Simulation time 163898069985 ps
CPU time 354.62 seconds
Started Jul 04 07:07:17 PM PDT 24
Finished Jul 04 07:13:12 PM PDT 24
Peak memory 201860 kb
Host smart-f9b4f0e5-b5dc-43fe-be81-15444283b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126661872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4126661872
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1669039284
Short name T359
Test name
Test status
Simulation time 166979981914 ps
CPU time 107.32 seconds
Started Jul 04 07:07:20 PM PDT 24
Finished Jul 04 07:09:08 PM PDT 24
Peak memory 201848 kb
Host smart-c3a4706c-6cc4-41b5-9be0-507ee3d48614
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669039284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1669039284
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2219424907
Short name T673
Test name
Test status
Simulation time 164436094037 ps
CPU time 117.01 seconds
Started Jul 04 07:07:17 PM PDT 24
Finished Jul 04 07:09:14 PM PDT 24
Peak memory 202000 kb
Host smart-050a9f0e-7e46-414e-b54d-ec24b1455c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219424907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2219424907
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2200003717
Short name T369
Test name
Test status
Simulation time 486555034754 ps
CPU time 1159.26 seconds
Started Jul 04 07:07:17 PM PDT 24
Finished Jul 04 07:26:37 PM PDT 24
Peak memory 201860 kb
Host smart-5c529bb8-c64e-4b25-913f-9e00e8862941
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200003717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2200003717
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.48015542
Short name T317
Test name
Test status
Simulation time 542984031271 ps
CPU time 626.31 seconds
Started Jul 04 07:07:18 PM PDT 24
Finished Jul 04 07:17:45 PM PDT 24
Peak memory 201900 kb
Host smart-9db822c8-50f6-4315-8a2f-2b24baf3427c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48015542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_w
akeup.48015542
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3685736120
Short name T657
Test name
Test status
Simulation time 201471685412 ps
CPU time 457.18 seconds
Started Jul 04 07:07:17 PM PDT 24
Finished Jul 04 07:14:54 PM PDT 24
Peak memory 201896 kb
Host smart-26713903-38b1-429e-935f-5c56d301debe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685736120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3685736120
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.500767719
Short name T53
Test name
Test status
Simulation time 104946708169 ps
CPU time 522.59 seconds
Started Jul 04 07:07:25 PM PDT 24
Finished Jul 04 07:16:08 PM PDT 24
Peak memory 202256 kb
Host smart-2fac9f52-c8be-48f0-9e2a-7211fc1cc611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500767719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.500767719
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2941429405
Short name T712
Test name
Test status
Simulation time 27695546638 ps
CPU time 29.99 seconds
Started Jul 04 07:07:25 PM PDT 24
Finished Jul 04 07:07:56 PM PDT 24
Peak memory 201716 kb
Host smart-8a2a87cb-16ce-4200-848f-8f70a7a72b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941429405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2941429405
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1584010554
Short name T597
Test name
Test status
Simulation time 3921138542 ps
CPU time 5.31 seconds
Started Jul 04 07:07:26 PM PDT 24
Finished Jul 04 07:07:31 PM PDT 24
Peak memory 201708 kb
Host smart-bc83abc1-11cd-4e9c-9160-0196d1dd63a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584010554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1584010554
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3474768355
Short name T109
Test name
Test status
Simulation time 5764902533 ps
CPU time 7.95 seconds
Started Jul 04 07:07:18 PM PDT 24
Finished Jul 04 07:07:26 PM PDT 24
Peak memory 201708 kb
Host smart-61061d12-125b-4b02-942b-a365681f5139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474768355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3474768355
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2006758464
Short name T513
Test name
Test status
Simulation time 360469772283 ps
CPU time 1076.82 seconds
Started Jul 04 07:07:25 PM PDT 24
Finished Jul 04 07:25:22 PM PDT 24
Peak memory 202160 kb
Host smart-0406cf63-4105-44da-bb84-a2b0d1c54258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006758464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2006758464
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2348573207
Short name T543
Test name
Test status
Simulation time 43291698504 ps
CPU time 92.74 seconds
Started Jul 04 07:07:26 PM PDT 24
Finished Jul 04 07:08:59 PM PDT 24
Peak memory 218700 kb
Host smart-0e382b29-1849-4c38-a567-a22a8b66c895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348573207 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2348573207
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3051032939
Short name T26
Test name
Test status
Simulation time 456088914 ps
CPU time 1.63 seconds
Started Jul 04 07:07:39 PM PDT 24
Finished Jul 04 07:07:41 PM PDT 24
Peak memory 201652 kb
Host smart-4c21b97f-e685-477b-8b15-1af42fa05058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051032939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3051032939
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4014614621
Short name T158
Test name
Test status
Simulation time 337548669331 ps
CPU time 797.27 seconds
Started Jul 04 07:07:33 PM PDT 24
Finished Jul 04 07:20:50 PM PDT 24
Peak memory 201904 kb
Host smart-e5a8c551-4880-4df2-b642-8565baceaedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014614621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4014614621
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3772893778
Short name T438
Test name
Test status
Simulation time 324901168217 ps
CPU time 759.57 seconds
Started Jul 04 07:07:25 PM PDT 24
Finished Jul 04 07:20:05 PM PDT 24
Peak memory 201960 kb
Host smart-4b18505c-3994-4ed4-be01-b71d6456b506
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772893778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3772893778
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3288019064
Short name T153
Test name
Test status
Simulation time 326429231767 ps
CPU time 747.33 seconds
Started Jul 04 07:07:26 PM PDT 24
Finished Jul 04 07:19:53 PM PDT 24
Peak memory 201904 kb
Host smart-2e6e485d-6c7d-4ab9-bf0c-4adc3a9f2d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288019064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3288019064
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.884931623
Short name T423
Test name
Test status
Simulation time 161765859329 ps
CPU time 43.72 seconds
Started Jul 04 07:07:26 PM PDT 24
Finished Jul 04 07:08:10 PM PDT 24
Peak memory 201892 kb
Host smart-c28a270d-b3d9-44c1-8232-fd81e95bb28e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=884931623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.884931623
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3348907578
Short name T252
Test name
Test status
Simulation time 165262924955 ps
CPU time 403.28 seconds
Started Jul 04 07:07:32 PM PDT 24
Finished Jul 04 07:14:15 PM PDT 24
Peak memory 202004 kb
Host smart-9e1004e2-74f8-4535-860e-d3140574fc5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348907578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3348907578
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4225769285
Short name T473
Test name
Test status
Simulation time 217321352481 ps
CPU time 88.73 seconds
Started Jul 04 07:07:33 PM PDT 24
Finished Jul 04 07:09:02 PM PDT 24
Peak memory 201908 kb
Host smart-aaa9ec22-702e-4736-b467-20b82b5df16e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225769285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4225769285
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1819414573
Short name T537
Test name
Test status
Simulation time 42774023978 ps
CPU time 46.37 seconds
Started Jul 04 07:07:31 PM PDT 24
Finished Jul 04 07:08:18 PM PDT 24
Peak memory 201732 kb
Host smart-e4e25825-137b-4586-8640-0964fbc8778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819414573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1819414573
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3241812795
Short name T466
Test name
Test status
Simulation time 4516328184 ps
CPU time 3.27 seconds
Started Jul 04 07:07:36 PM PDT 24
Finished Jul 04 07:07:39 PM PDT 24
Peak memory 201744 kb
Host smart-968c4da4-7f45-400c-b422-d2f930de7377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241812795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3241812795
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1541274489
Short name T675
Test name
Test status
Simulation time 5547744250 ps
CPU time 6.71 seconds
Started Jul 04 07:07:24 PM PDT 24
Finished Jul 04 07:07:31 PM PDT 24
Peak memory 201736 kb
Host smart-9174b6b0-4764-499b-a992-946e28240cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541274489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1541274489
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.445614853
Short name T436
Test name
Test status
Simulation time 480813863356 ps
CPU time 537.73 seconds
Started Jul 04 07:07:32 PM PDT 24
Finished Jul 04 07:16:30 PM PDT 24
Peak memory 201948 kb
Host smart-f8f71fbf-7d6b-472f-8723-8d0c8b42638b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445614853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
445614853
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4054055836
Short name T516
Test name
Test status
Simulation time 14438629759 ps
CPU time 29.02 seconds
Started Jul 04 07:07:36 PM PDT 24
Finished Jul 04 07:08:05 PM PDT 24
Peak memory 210592 kb
Host smart-0be41c20-f3b9-46ae-a973-33cee3658e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054055836 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4054055836
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3517312223
Short name T570
Test name
Test status
Simulation time 535139577 ps
CPU time 1.29 seconds
Started Jul 04 07:07:47 PM PDT 24
Finished Jul 04 07:07:48 PM PDT 24
Peak memory 201628 kb
Host smart-ec5fbb01-00f1-4671-84a7-0a408ca52d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517312223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3517312223
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3522959204
Short name T233
Test name
Test status
Simulation time 169363111591 ps
CPU time 92.19 seconds
Started Jul 04 07:07:40 PM PDT 24
Finished Jul 04 07:09:12 PM PDT 24
Peak memory 201916 kb
Host smart-1c66193b-2925-445e-8f8d-5799a3db9689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522959204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3522959204
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3038422659
Short name T683
Test name
Test status
Simulation time 163928745407 ps
CPU time 391.69 seconds
Started Jul 04 07:07:39 PM PDT 24
Finished Jul 04 07:14:11 PM PDT 24
Peak memory 201940 kb
Host smart-20c47989-8bf8-47f7-bbf2-488357a297fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038422659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3038422659
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2958650447
Short name T408
Test name
Test status
Simulation time 328476248620 ps
CPU time 718.24 seconds
Started Jul 04 07:07:41 PM PDT 24
Finished Jul 04 07:19:40 PM PDT 24
Peak memory 201844 kb
Host smart-c371fd1b-0869-43bc-a8bf-0960e79882a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958650447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2958650447
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1768906068
Short name T721
Test name
Test status
Simulation time 165102389842 ps
CPU time 371.89 seconds
Started Jul 04 07:07:39 PM PDT 24
Finished Jul 04 07:13:52 PM PDT 24
Peak memory 201840 kb
Host smart-1675abcc-093b-4aa6-86e1-1799a6142f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768906068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1768906068
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2529451991
Short name T442
Test name
Test status
Simulation time 491502486340 ps
CPU time 152.24 seconds
Started Jul 04 07:07:42 PM PDT 24
Finished Jul 04 07:10:14 PM PDT 24
Peak memory 201876 kb
Host smart-fecee765-748c-4571-bf1a-d3e356be6753
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529451991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2529451991
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1843651978
Short name T498
Test name
Test status
Simulation time 366758389489 ps
CPU time 195.96 seconds
Started Jul 04 07:07:40 PM PDT 24
Finished Jul 04 07:10:56 PM PDT 24
Peak memory 201900 kb
Host smart-34f31704-7ed2-4d15-b26f-8b3dac73fa01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843651978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1843651978
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.127484721
Short name T608
Test name
Test status
Simulation time 593685127835 ps
CPU time 336.03 seconds
Started Jul 04 07:07:39 PM PDT 24
Finished Jul 04 07:13:16 PM PDT 24
Peak memory 201908 kb
Host smart-5ea17204-698b-4700-84bd-855d00e851c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127484721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.127484721
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.507442506
Short name T480
Test name
Test status
Simulation time 115562973102 ps
CPU time 606.12 seconds
Started Jul 04 07:07:40 PM PDT 24
Finished Jul 04 07:17:47 PM PDT 24
Peak memory 202152 kb
Host smart-d49e64d4-dbb7-49fb-bc92-5f7cda8a3c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507442506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.507442506
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3668193607
Short name T637
Test name
Test status
Simulation time 40675622673 ps
CPU time 24.08 seconds
Started Jul 04 07:07:38 PM PDT 24
Finished Jul 04 07:08:02 PM PDT 24
Peak memory 201704 kb
Host smart-21c67b8e-037b-4c71-8c04-0cd55a325f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668193607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3668193607
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1576657482
Short name T522
Test name
Test status
Simulation time 3533797268 ps
CPU time 2.53 seconds
Started Jul 04 07:07:40 PM PDT 24
Finished Jul 04 07:07:43 PM PDT 24
Peak memory 201728 kb
Host smart-9991c61f-c529-4d26-a236-eb78b754356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576657482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1576657482
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.779350007
Short name T667
Test name
Test status
Simulation time 5661157518 ps
CPU time 4.11 seconds
Started Jul 04 07:07:41 PM PDT 24
Finished Jul 04 07:07:46 PM PDT 24
Peak memory 201696 kb
Host smart-841f1202-890f-4c14-b6a9-2229ca1030e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779350007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.779350007
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.162613425
Short name T101
Test name
Test status
Simulation time 446205049176 ps
CPU time 431.72 seconds
Started Jul 04 07:07:46 PM PDT 24
Finished Jul 04 07:14:58 PM PDT 24
Peak memory 201952 kb
Host smart-404b5a20-039e-496e-82ff-23733b4a8c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162613425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
162613425
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3422407964
Short name T333
Test name
Test status
Simulation time 753289562244 ps
CPU time 608.95 seconds
Started Jul 04 07:07:47 PM PDT 24
Finished Jul 04 07:17:57 PM PDT 24
Peak memory 210624 kb
Host smart-c077103f-305f-4f85-a74e-9dfaf6ca8764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422407964 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3422407964
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4004430677
Short name T578
Test name
Test status
Simulation time 325638155 ps
CPU time 0.8 seconds
Started Jul 04 07:00:22 PM PDT 24
Finished Jul 04 07:00:23 PM PDT 24
Peak memory 201664 kb
Host smart-c92fabd9-283e-4e13-ae70-35213dccf7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004430677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4004430677
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.4277017143
Short name T212
Test name
Test status
Simulation time 502406861928 ps
CPU time 1115.27 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:18:54 PM PDT 24
Peak memory 201980 kb
Host smart-34556dab-b7b1-4063-9d34-9d6066976a38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277017143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.4277017143
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1717633667
Short name T311
Test name
Test status
Simulation time 406223732617 ps
CPU time 897.58 seconds
Started Jul 04 07:00:25 PM PDT 24
Finished Jul 04 07:15:22 PM PDT 24
Peak memory 201888 kb
Host smart-34e7d386-0c0c-4bf0-81de-8bee892612c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717633667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1717633667
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4153436697
Short name T209
Test name
Test status
Simulation time 331471123109 ps
CPU time 197.81 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:03:35 PM PDT 24
Peak memory 201960 kb
Host smart-e8f28346-d9d7-477e-9a8c-9832d823ae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153436697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4153436697
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2265928560
Short name T511
Test name
Test status
Simulation time 167202359330 ps
CPU time 192.83 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:03:31 PM PDT 24
Peak memory 201908 kb
Host smart-ad47f749-aae6-4e85-a729-dba0f565778b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265928560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2265928560
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.322626092
Short name T531
Test name
Test status
Simulation time 165051397063 ps
CPU time 178.26 seconds
Started Jul 04 07:00:19 PM PDT 24
Finished Jul 04 07:03:18 PM PDT 24
Peak memory 201932 kb
Host smart-622b86b1-b60c-488e-9f26-c762a65c196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322626092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.322626092
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3930988312
Short name T384
Test name
Test status
Simulation time 493492736103 ps
CPU time 285.82 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:05:05 PM PDT 24
Peak memory 201884 kb
Host smart-aaecebab-7a58-4d2a-a809-37693ecd593f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930988312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3930988312
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1549227929
Short name T8
Test name
Test status
Simulation time 183267846061 ps
CPU time 103.51 seconds
Started Jul 04 07:00:17 PM PDT 24
Finished Jul 04 07:02:00 PM PDT 24
Peak memory 201992 kb
Host smart-79440736-30f8-4909-8506-1b640f65a675
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549227929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1549227929
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2438509634
Short name T373
Test name
Test status
Simulation time 392418760345 ps
CPU time 236.32 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:04:15 PM PDT 24
Peak memory 201872 kb
Host smart-803d3bbd-9a72-41f9-9702-6b4e96ff4b91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438509634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2438509634
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1077071761
Short name T168
Test name
Test status
Simulation time 86520981371 ps
CPU time 337.65 seconds
Started Jul 04 07:00:27 PM PDT 24
Finished Jul 04 07:06:05 PM PDT 24
Peak memory 202200 kb
Host smart-82872ec6-56d1-42a6-ab74-bb45edee87ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077071761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1077071761
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3586321697
Short name T39
Test name
Test status
Simulation time 27307922883 ps
CPU time 13.4 seconds
Started Jul 04 07:00:23 PM PDT 24
Finished Jul 04 07:00:36 PM PDT 24
Peak memory 201724 kb
Host smart-11c55ed7-e281-45b5-97ed-40e4dbfbdfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586321697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3586321697
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3857341356
Short name T380
Test name
Test status
Simulation time 3304309603 ps
CPU time 7.44 seconds
Started Jul 04 07:00:25 PM PDT 24
Finished Jul 04 07:00:32 PM PDT 24
Peak memory 201688 kb
Host smart-5732c239-41e6-4085-819f-ea12fba70b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857341356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3857341356
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1724769723
Short name T132
Test name
Test status
Simulation time 5639313223 ps
CPU time 13.42 seconds
Started Jul 04 07:00:18 PM PDT 24
Finished Jul 04 07:00:32 PM PDT 24
Peak memory 201708 kb
Host smart-214d8a56-936f-442e-a79f-cda2c291e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724769723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1724769723
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1871818758
Short name T610
Test name
Test status
Simulation time 239181657623 ps
CPU time 534.33 seconds
Started Jul 04 07:00:28 PM PDT 24
Finished Jul 04 07:09:22 PM PDT 24
Peak memory 218576 kb
Host smart-4db7aa02-3db6-4d35-9c4d-b1863fcb26d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871818758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1871818758
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2339866981
Short name T476
Test name
Test status
Simulation time 321652554871 ps
CPU time 59.65 seconds
Started Jul 04 07:00:26 PM PDT 24
Finished Jul 04 07:01:26 PM PDT 24
Peak memory 210328 kb
Host smart-fb63593b-07bb-49e1-b448-9e7ec649f551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339866981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2339866981
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2481598608
Short name T411
Test name
Test status
Simulation time 332171154 ps
CPU time 1.26 seconds
Started Jul 04 07:00:27 PM PDT 24
Finished Jul 04 07:00:28 PM PDT 24
Peak memory 201892 kb
Host smart-5a21a469-25e7-4dac-83c3-44ab0f3e2e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481598608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2481598608
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.26447553
Short name T3
Test name
Test status
Simulation time 330275408892 ps
CPU time 783.41 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:13:27 PM PDT 24
Peak memory 201952 kb
Host smart-2fd5c01d-fa55-4919-80f4-e39e653f814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26447553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.26447553
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.587474831
Short name T147
Test name
Test status
Simulation time 164649410480 ps
CPU time 391.46 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:06:56 PM PDT 24
Peak memory 201904 kb
Host smart-9d2009b9-bccc-4336-bccb-000257b8f882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587474831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.587474831
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.617335116
Short name T501
Test name
Test status
Simulation time 490367565057 ps
CPU time 1134.85 seconds
Started Jul 04 07:00:28 PM PDT 24
Finished Jul 04 07:19:23 PM PDT 24
Peak memory 201864 kb
Host smart-d054a7e9-1540-4558-a79c-9b0ad4840723
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=617335116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.617335116
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.278976444
Short name T312
Test name
Test status
Simulation time 326772145851 ps
CPU time 674.12 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:11:38 PM PDT 24
Peak memory 201940 kb
Host smart-b6da5bfa-2716-4090-9c81-0558e98a00fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278976444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.278976444
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1828915807
Short name T414
Test name
Test status
Simulation time 165012822025 ps
CPU time 203.2 seconds
Started Jul 04 07:00:22 PM PDT 24
Finished Jul 04 07:03:45 PM PDT 24
Peak memory 201916 kb
Host smart-48af7f3b-d355-4d28-90e5-f886eb6f5485
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828915807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1828915807
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3174685006
Short name T538
Test name
Test status
Simulation time 179279300332 ps
CPU time 117.62 seconds
Started Jul 04 07:00:25 PM PDT 24
Finished Jul 04 07:02:23 PM PDT 24
Peak memory 201932 kb
Host smart-fd4aa257-c8ad-46b3-a332-ba61396f0109
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174685006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3174685006
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1988686630
Short name T43
Test name
Test status
Simulation time 397918227790 ps
CPU time 248.97 seconds
Started Jul 04 07:00:25 PM PDT 24
Finished Jul 04 07:04:34 PM PDT 24
Peak memory 201872 kb
Host smart-c4e6ad7f-58f2-4d30-86a4-26b38723b16b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988686630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1988686630
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2522947080
Short name T611
Test name
Test status
Simulation time 85356373327 ps
CPU time 259.11 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:04:43 PM PDT 24
Peak memory 202280 kb
Host smart-ce7a78af-4e1e-4af0-95ee-3f76cb1a36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522947080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2522947080
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.6582640
Short name T360
Test name
Test status
Simulation time 32016370732 ps
CPU time 19.14 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:00:43 PM PDT 24
Peak memory 201728 kb
Host smart-42e66052-bed6-43c8-bcab-3fbd591d69be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6582640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.6582640
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2376322903
Short name T489
Test name
Test status
Simulation time 4306265339 ps
CPU time 5.42 seconds
Started Jul 04 07:00:27 PM PDT 24
Finished Jul 04 07:00:33 PM PDT 24
Peak memory 201720 kb
Host smart-80ab9f92-37a1-4c94-90d1-124d54c55ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376322903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2376322903
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3435337083
Short name T413
Test name
Test status
Simulation time 5654309738 ps
CPU time 6.85 seconds
Started Jul 04 07:00:22 PM PDT 24
Finished Jul 04 07:00:29 PM PDT 24
Peak memory 201728 kb
Host smart-0ac3ffbe-0482-4ad5-96dc-78c9697c3832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435337083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3435337083
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.953187552
Short name T519
Test name
Test status
Simulation time 44154474772 ps
CPU time 68.32 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:01:32 PM PDT 24
Peak memory 210292 kb
Host smart-44eeb2b2-102e-4ead-a651-2bd44b279535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953187552 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.953187552
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1908930556
Short name T547
Test name
Test status
Simulation time 531977074 ps
CPU time 0.99 seconds
Started Jul 04 07:00:27 PM PDT 24
Finished Jul 04 07:00:28 PM PDT 24
Peak memory 201624 kb
Host smart-fc598b13-a330-4d97-9447-48d11cac79f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908930556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1908930556
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1909295127
Short name T245
Test name
Test status
Simulation time 600225528422 ps
CPU time 1174.24 seconds
Started Jul 04 07:00:28 PM PDT 24
Finished Jul 04 07:20:02 PM PDT 24
Peak memory 201892 kb
Host smart-687cbf8e-24f8-49f1-a0fa-ba63d90ab988
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909295127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1909295127
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1536068655
Short name T794
Test name
Test status
Simulation time 493565680317 ps
CPU time 550.42 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:09:35 PM PDT 24
Peak memory 201992 kb
Host smart-25976dce-fe42-4619-b65c-7f271f7c75a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536068655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1536068655
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1873095486
Short name T533
Test name
Test status
Simulation time 160035944067 ps
CPU time 197.31 seconds
Started Jul 04 07:00:25 PM PDT 24
Finished Jul 04 07:03:43 PM PDT 24
Peak memory 202104 kb
Host smart-37f6132d-e906-4abf-b8cd-0ba1baf3ea6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873095486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1873095486
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.4073764789
Short name T679
Test name
Test status
Simulation time 164051104754 ps
CPU time 386.43 seconds
Started Jul 04 07:00:24 PM PDT 24
Finished Jul 04 07:06:51 PM PDT 24
Peak memory 201936 kb
Host smart-3feab4ff-3095-4de5-8bef-8c9b13725426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073764789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4073764789
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4006644230
Short name T433
Test name
Test status
Simulation time 162303173600 ps
CPU time 367.54 seconds
Started Jul 04 07:00:26 PM PDT 24
Finished Jul 04 07:06:34 PM PDT 24
Peak memory 201920 kb
Host smart-14262d0f-b994-4e77-88a5-6ad01f512a77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006644230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4006644230
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1857646490
Short name T788
Test name
Test status
Simulation time 164116103711 ps
CPU time 95.67 seconds
Started Jul 04 07:00:22 PM PDT 24
Finished Jul 04 07:01:58 PM PDT 24
Peak memory 201820 kb
Host smart-d93b04c5-f299-4c52-b5c3-c64c8e4b3a50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857646490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1857646490
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.813455168
Short name T471
Test name
Test status
Simulation time 202984139855 ps
CPU time 419.91 seconds
Started Jul 04 07:00:26 PM PDT 24
Finished Jul 04 07:07:26 PM PDT 24
Peak memory 202112 kb
Host smart-71a1e72b-24e9-4c1b-9dd0-6aa59f67b616
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813455168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.813455168
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2159531874
Short name T227
Test name
Test status
Simulation time 117179030717 ps
CPU time 576.05 seconds
Started Jul 04 07:00:29 PM PDT 24
Finished Jul 04 07:10:05 PM PDT 24
Peak memory 202228 kb
Host smart-e05f35a5-c9db-473e-b406-a81df6f692de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159531874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2159531874
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2549953688
Short name T454
Test name
Test status
Simulation time 37204230688 ps
CPU time 22.46 seconds
Started Jul 04 07:00:27 PM PDT 24
Finished Jul 04 07:00:50 PM PDT 24
Peak memory 201664 kb
Host smart-64bf84f0-23b7-4ea6-bb0a-eb4ca728489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549953688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2549953688
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1378240816
Short name T556
Test name
Test status
Simulation time 2903437577 ps
CPU time 7.17 seconds
Started Jul 04 07:00:27 PM PDT 24
Finished Jul 04 07:00:34 PM PDT 24
Peak memory 201952 kb
Host smart-e416f9ef-bcad-4d4b-b356-331da5a2b80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378240816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1378240816
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1990509746
Short name T10
Test name
Test status
Simulation time 6097238336 ps
CPU time 4.8 seconds
Started Jul 04 07:00:28 PM PDT 24
Finished Jul 04 07:00:33 PM PDT 24
Peak memory 201752 kb
Host smart-9910d368-29af-4c01-9ca0-eda2da818a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990509746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1990509746
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1010423125
Short name T648
Test name
Test status
Simulation time 171077421700 ps
CPU time 24.93 seconds
Started Jul 04 07:00:28 PM PDT 24
Finished Jul 04 07:00:53 PM PDT 24
Peak memory 201924 kb
Host smart-aae5f8dd-b856-4b3f-9590-fac11d18a682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010423125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1010423125
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1058006152
Short name T740
Test name
Test status
Simulation time 359428397536 ps
CPU time 327.97 seconds
Started Jul 04 07:00:23 PM PDT 24
Finished Jul 04 07:05:51 PM PDT 24
Peak memory 210792 kb
Host smart-53347a61-0151-4251-a9dc-ee379c1765fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058006152 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1058006152
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1526501076
Short name T594
Test name
Test status
Simulation time 428458450 ps
CPU time 0.75 seconds
Started Jul 04 07:00:36 PM PDT 24
Finished Jul 04 07:00:37 PM PDT 24
Peak memory 201660 kb
Host smart-644b1b10-4822-48bb-aa70-57cb08f2e877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526501076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1526501076
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.806913362
Short name T730
Test name
Test status
Simulation time 350232932919 ps
CPU time 408.72 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:07:20 PM PDT 24
Peak memory 201892 kb
Host smart-39c8c6d6-51ef-45bd-b610-ee5f5f9d1597
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806913362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.806913362
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2048196765
Short name T337
Test name
Test status
Simulation time 491876361816 ps
CPU time 1021.09 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:17:32 PM PDT 24
Peak memory 201928 kb
Host smart-b90f6592-bd4e-4f28-95a4-72b57a1f11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048196765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2048196765
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1127585491
Short name T509
Test name
Test status
Simulation time 161409177873 ps
CPU time 366.63 seconds
Started Jul 04 07:00:35 PM PDT 24
Finished Jul 04 07:06:42 PM PDT 24
Peak memory 201924 kb
Host smart-5c82b69f-9004-4823-a1d9-1fc75969c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127585491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1127585491
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4256110763
Short name T184
Test name
Test status
Simulation time 164541519601 ps
CPU time 63.94 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:01:35 PM PDT 24
Peak memory 201904 kb
Host smart-46595dad-31fa-4719-8b66-f5abe9f276bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256110763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.4256110763
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.76833367
Short name T659
Test name
Test status
Simulation time 162057485916 ps
CPU time 101.03 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:02:12 PM PDT 24
Peak memory 201892 kb
Host smart-e1a6ffed-d430-49fc-8e4a-e36ba73a3dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76833367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.76833367
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3932917622
Short name T616
Test name
Test status
Simulation time 492984031450 ps
CPU time 1176.8 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:20:08 PM PDT 24
Peak memory 201888 kb
Host smart-a4db4ac9-10e5-4652-a9b8-cf945cda723e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932917622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3932917622
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3644204105
Short name T619
Test name
Test status
Simulation time 401266080054 ps
CPU time 939.72 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:16:13 PM PDT 24
Peak memory 201888 kb
Host smart-ff513221-ff3d-40bb-9941-3fe5a3db6569
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644204105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3644204105
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1887898779
Short name T668
Test name
Test status
Simulation time 88611830291 ps
CPU time 422.1 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:07:33 PM PDT 24
Peak memory 202308 kb
Host smart-9c1ce140-08ab-4317-9cfe-3fed613b572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887898779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1887898779
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1537418546
Short name T479
Test name
Test status
Simulation time 29098575523 ps
CPU time 15.72 seconds
Started Jul 04 07:00:36 PM PDT 24
Finished Jul 04 07:00:51 PM PDT 24
Peak memory 201704 kb
Host smart-a07d6684-c731-458b-ba25-4df467f872de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537418546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1537418546
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.49671193
Short name T554
Test name
Test status
Simulation time 4790032262 ps
CPU time 10.88 seconds
Started Jul 04 07:00:34 PM PDT 24
Finished Jul 04 07:00:46 PM PDT 24
Peak memory 201728 kb
Host smart-1fdfeba0-e9f3-4335-9907-537a3b8462b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49671193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.49671193
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1150252654
Short name T624
Test name
Test status
Simulation time 5775148799 ps
CPU time 4.03 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:00:38 PM PDT 24
Peak memory 201720 kb
Host smart-ba94f7ca-17b7-4231-bc37-9c97a4953503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150252654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1150252654
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2317583089
Short name T261
Test name
Test status
Simulation time 546715556481 ps
CPU time 669.78 seconds
Started Jul 04 07:00:34 PM PDT 24
Finished Jul 04 07:11:45 PM PDT 24
Peak memory 201908 kb
Host smart-1458c779-0ba3-4843-a772-15bbe88b4a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317583089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2317583089
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3359883468
Short name T45
Test name
Test status
Simulation time 88944981503 ps
CPU time 265.61 seconds
Started Jul 04 07:00:30 PM PDT 24
Finished Jul 04 07:04:55 PM PDT 24
Peak memory 210584 kb
Host smart-5f9d9632-33a3-45ec-9450-c25d1154b481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359883468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3359883468
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3637588040
Short name T38
Test name
Test status
Simulation time 333800697 ps
CPU time 0.99 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:00:33 PM PDT 24
Peak memory 201656 kb
Host smart-cd264a5c-2ec3-4a2d-9d57-cf8d7c0b1f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637588040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3637588040
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2070407349
Short name T346
Test name
Test status
Simulation time 341871367399 ps
CPU time 96.24 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:02:10 PM PDT 24
Peak memory 201908 kb
Host smart-fc696e19-1f41-46a9-b2c7-02726b689522
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070407349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2070407349
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.561251175
Short name T232
Test name
Test status
Simulation time 533073814312 ps
CPU time 1087.59 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:18:39 PM PDT 24
Peak memory 201916 kb
Host smart-0b4d7216-c3b1-49fc-9d59-5fceaf34c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561251175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.561251175
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1595036324
Short name T658
Test name
Test status
Simulation time 494086407100 ps
CPU time 1126.09 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:19:20 PM PDT 24
Peak memory 201916 kb
Host smart-d77c225f-e5fa-4d22-adb1-961448599d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595036324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1595036324
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1320595447
Short name T11
Test name
Test status
Simulation time 324049636493 ps
CPU time 192.49 seconds
Started Jul 04 07:00:34 PM PDT 24
Finished Jul 04 07:03:47 PM PDT 24
Peak memory 201888 kb
Host smart-b34a5f22-90d0-4cf5-ae28-fe169c4cf25b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320595447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1320595447
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1829417169
Short name T208
Test name
Test status
Simulation time 490046645596 ps
CPU time 980.55 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:16:53 PM PDT 24
Peak memory 201856 kb
Host smart-a7f27b49-d35f-4adb-ad6c-ba07c4812495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829417169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1829417169
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2934877551
Short name T29
Test name
Test status
Simulation time 161460367590 ps
CPU time 79.53 seconds
Started Jul 04 07:00:30 PM PDT 24
Finished Jul 04 07:01:50 PM PDT 24
Peak memory 201900 kb
Host smart-0c219f83-d16f-4c9a-93ae-ba7ab220b489
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934877551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2934877551
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2366427765
Short name T508
Test name
Test status
Simulation time 190406306330 ps
CPU time 455.42 seconds
Started Jul 04 07:00:30 PM PDT 24
Finished Jul 04 07:08:05 PM PDT 24
Peak memory 201952 kb
Host smart-8ca71644-f106-44dc-8351-b9227b98012b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366427765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2366427765
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.873764039
Short name T367
Test name
Test status
Simulation time 597704385218 ps
CPU time 1308.59 seconds
Started Jul 04 07:00:32 PM PDT 24
Finished Jul 04 07:22:21 PM PDT 24
Peak memory 201896 kb
Host smart-16591e5e-634f-4308-8cc0-5751851eab9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873764039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.873764039
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3566105790
Short name T55
Test name
Test status
Simulation time 77962297817 ps
CPU time 286.33 seconds
Started Jul 04 07:00:34 PM PDT 24
Finished Jul 04 07:05:21 PM PDT 24
Peak memory 202200 kb
Host smart-6f442514-b8e0-4b8c-ba8d-01dd25cbb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566105790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3566105790
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3264614725
Short name T472
Test name
Test status
Simulation time 34345239086 ps
CPU time 11.76 seconds
Started Jul 04 07:00:31 PM PDT 24
Finished Jul 04 07:00:43 PM PDT 24
Peak memory 201720 kb
Host smart-2d7adb5f-2827-4d04-bcb5-8704738e5c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264614725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3264614725
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.276925843
Short name T641
Test name
Test status
Simulation time 2886689448 ps
CPU time 7.53 seconds
Started Jul 04 07:00:35 PM PDT 24
Finished Jul 04 07:00:43 PM PDT 24
Peak memory 201716 kb
Host smart-e57dac71-c125-4e29-93ea-9e07b1dfcb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276925843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.276925843
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1630586070
Short name T692
Test name
Test status
Simulation time 5660187840 ps
CPU time 13.1 seconds
Started Jul 04 07:00:33 PM PDT 24
Finished Jul 04 07:00:46 PM PDT 24
Peak memory 201740 kb
Host smart-554c9be6-93fa-4f75-95a9-bf6e30e424b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630586070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1630586070
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4261122912
Short name T649
Test name
Test status
Simulation time 165110007451 ps
CPU time 190.24 seconds
Started Jul 04 07:00:35 PM PDT 24
Finished Jul 04 07:03:45 PM PDT 24
Peak memory 201940 kb
Host smart-b1ad8e38-9370-4ede-b574-cf45ee5c6ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261122912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4261122912
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3079115497
Short name T256
Test name
Test status
Simulation time 467595219496 ps
CPU time 373.1 seconds
Started Jul 04 07:00:35 PM PDT 24
Finished Jul 04 07:06:48 PM PDT 24
Peak memory 218088 kb
Host smart-e15ca139-3db8-4537-a7f1-7cb0cf0dd410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079115497 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3079115497
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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