Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv



Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
testmode_cp 12 0 12 100.00 100 1 1 0


Summary for Variable testmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for testmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
testmodes[AdcCtrlTestmodeOneShot] 7520 1 T1 22 T4 61 T5 20
testmodes[AdcCtrlTestmodeNormal] 5708 1 T1 18 T2 1 T4 50
testmodes[AdcCtrlTestmodeLowpower] 6216 1 T1 1 T3 2 T4 63
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot] 4024 1 T1 9 T4 22 T5 19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal] 1851 1 T1 12 T4 19 T48 2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower] 1532 1 T1 1 T4 19 T45 22
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot] 1884 1 T1 12 T4 19 T48 3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal] 2052 1 T1 5 T4 12 T7 2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower] 1440 1 T4 19 T45 10 T35 1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot] 1490 1 T4 19 T45 15 T37 5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal] 1477 1 T1 1 T4 19 T13 1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower] 2995 1 T3 1 T4 25 T10 11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%