Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24042

1

T1

42

T3

6

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3536

1

T1

3

T2

22

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21160

1

T1

44

T2

22

T3

11

auto[1]

6418

1

T1

1

T4

1

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	482	1			T4	1		T45	2		T36	1
values[0]	12	1			T216	1		T168	1		T109	10
values[1]	658	1			T7	1		T113	11		T45	1
values[2]	2973	1			T8	13		T9	9		T11	13
values[3]	705	1			T1	1		T14	3		T134	1
values[4]	692	1			T12	1		T181	1		T43	24
values[5]	658	1			T1	3		T35	5		T131	12
values[6]	695	1			T3	5		T7	1		T13	18
values[7]	600	1			T3	6		T36	8		T133	25
values[8]	772	1			T112	1		T45	1		T42	50
values[9]	1301	1			T2	22		T7	1		T112	1
minimum	18030	1			T1	41		T4	173		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	829	1			T7	1		T45	1		T131	1
values[1]	2944	1			T8	13		T9	9		T11	13
values[2]	750	1			T14	3		T134	1		T132	1
values[3]	600	1			T1	1		T12	1		T181	1
values[4]	778	1			T1	3		T35	5		T131	12
values[5]	668	1			T3	5		T7	1		T13	18
values[6]	648	1			T3	6		T36	8		T42	18
values[7]	585	1			T2	22		T112	1		T45	1
values[8]	1034	1			T7	1		T112	1		T113	7
values[9]	227	1			T37	9		T31	7		T217	1
minimum	18515	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	1		T131	1		T38	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T45	1		T132	2		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T8	1		T11	2		T13	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T12	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T134	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T132	1		T26	14		T32	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T181	1		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T198	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T131	1		T28	5		T29	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	2		T35	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T181	1		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	5		T13	9		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	6		T42	9		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	6		T133	14		T86	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T112	1		T45	1		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T2	12		T27	11		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T113	1		T134	1		T162	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T112	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T37	6		T31	7		T221	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T217	1		T222	17		T223	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T209	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	4		T160	5		T175	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T87	4		T40	1		T195	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T8	12		T11	11		T13	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	8		T131	6		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	2		T218	14		T224	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T26	3		T32	11		T135	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T43	12		T38	5		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T175	8		T20	13		T225	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T131	11		T28	3		T17	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T35	3		T138	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	11		T142	12		T226	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	9		T113	11		T133	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T42	9		T85	1		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T36	2		T133	11		T86	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T43	10		T163	2		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	10		T27	2		T227	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T113	6		T162	13		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T42	15		T137	12		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T37	3		T221	10		T169	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T222	12		T223	2		T229	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T209	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	482	1			T4	1		T45	2		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T168	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T216	1		T109	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T113	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T45	1		T132	1		T87	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1624	1			T8	1		T11	2		T13	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	1		T12	3		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T14	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T131	1		T132	1		T15	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T181	1		T43	12		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	1		T198	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T131	1		T29	15		T17	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	2		T35	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T181	1		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	5		T13	9		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	6		T85	1		T86	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	6		T133	14		T86	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T112	1		T45	1		T42	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T42	17		T86	3		T27	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T113	1		T134	1		T37	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T2	12		T7	1		T112	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17884	1			T1	39		T4	173		T5	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T113	10		T38	4		T160	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T87	4		T225	12		T230	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T8	12		T11	11		T13	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	8		T40	1		T231	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	2		T218	14		T224	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T131	6		T15	2		T26	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T43	12		T38	5		T27	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T232	9		T175	8		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T131	11		T17	6		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T35	3		T138	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T28	3		T142	12		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	9		T113	11		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T85	1		T39	1		T87	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	2		T133	11		T86	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T42	9		T43	10		T87	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	15		T86	11		T27	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T113	6		T37	3		T162	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	10		T137	12		T138	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T131	1		T38	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T45	1		T132	2		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T8	13		T11	13		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	9		T12	1		T131	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	3		T134	1		T218	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T132	1		T26	5		T32	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T181	1		T43	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T198	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	12		T28	5		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	2		T35	5		T138	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T181	1		T15	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T13	10		T113	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	1		T42	10		T85	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	5		T133	12		T86	27
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T112	1		T45	1		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	11		T27	3		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T113	7		T134	1		T162	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	1		T112	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T37	7		T31	1		T221	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T217	1		T222	13		T223	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T209	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T160	5		T175	12		T200	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T87	8		T235	4		T195	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T13	1		T41	13		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	2		T15	3		T212	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	6		T29	11		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	12		T32	13		T135	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T43	11		T38	6		T27	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T175	8		T20	14		T225	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	3		T29	14		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	1		T145	9		T146	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	1		T142	13		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	4		T13	8		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	5		T42	8		T86	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T36	3		T133	13		T86	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	10		T166	13		T142	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	11		T27	10		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T162	21		T228	16		T238	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T42	16		T31	9		T130	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T37	2		T31	6		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T222	16		T223	12		T182	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	482	1			T4	1		T45	2		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T168	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T216	1		T109	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T113	11		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	1		T132	1		T87	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T8	13		T11	13		T13	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	9		T12	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T14	3		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T131	7		T132	1		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T181	1		T43	13		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T198	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T131	12		T29	1		T17	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	2		T35	5		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T181	1		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	1		T13	10		T113	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T85	2		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	5		T133	12		T86	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T112	1		T45	1		T42	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T42	16		T86	12		T27	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T113	7		T134	1		T37	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T2	11		T7	1		T112	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	41		T4	173		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T109	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T160	5		T175	12		T200	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T87	8		T235	4		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T13	1		T41	13		T239	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	2		T195	11		T212	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T166	5		T16	6		T29	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	3		T26	12		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T43	11		T38	6		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T175	8		T233	5		T20	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T29	14		T17	4		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T145	9		T146	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T28	3		T142	13		T160	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	4		T13	8		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	5		T86	4		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T36	3		T133	13		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T42	8		T43	10		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T42	16		T86	2		T27	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T37	2		T31	6		T162	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T2	11		T31	9		T130	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21748

1

T1

41

T3

5

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

5830

1

T1

4

T2

22

T3

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21696

1

T1

42

T3

11

T4

174

auto[1]

5882

1

T1

3

T2

22

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T240	11		T183	24		T111	1
values[0]	37	1			T241	12		T242	23		T243	2
values[1]	800	1			T42	32		T15	7		T27	12
values[2]	819	1			T3	6		T7	1		T13	5
values[3]	731	1			T12	1		T13	18		T134	1
values[4]	662	1			T9	9		T12	3		T112	1
values[5]	526	1			T113	19		T137	1		T26	10
values[6]	541	1			T1	1		T2	22		T35	5
values[7]	610	1			T3	5		T7	1		T14	3
values[8]	761	1			T7	1		T45	2		T38	5
values[9]	3543	1			T1	3		T8	13		T11	13
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1026	1			T3	6		T7	1		T13	5
values[1]	3011	1			T8	13		T11	13		T12	1
values[2]	776	1			T13	18		T134	1		T45	1
values[3]	574	1			T9	9		T12	3		T112	1
values[4]	587	1			T1	1		T113	19		T43	21
values[5]	644	1			T2	22		T14	3		T35	5
values[6]	632	1			T3	5		T7	1		T45	1
values[7]	704	1			T7	1		T45	1		T38	5
values[8]	919	1			T1	3		T37	9		T132	1
values[9]	167	1			T112	1		T135	21		T19	9
minimum	18538	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T13	2		T42	17		T15	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T3	6		T7	1		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T181	1		T85	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1620	1			T8	1		T11	2		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	9		T131	1		T42	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T134	1		T45	1		T36	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T112	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	3		T43	12		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T113	1		T136	1		T142	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T113	1		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T131	1		T16	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	12		T35	2		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	5		T45	1		T87	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T136	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T218	1		T31	7		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	1		T45	1		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T37	6		T224	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	2		T132	1		T166	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T112	1		T135	12		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T150	1		T183	12		T244	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18367	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T163	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	3		T42	15		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T113	10		T234	6		T175	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T85	1		T245	10		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	975	1			T8	12		T11	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	9		T131	11		T42	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	2		T133	11		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T9	8		T131	6		T38	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	12		T15	11		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T113	11		T234	13		T248	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T113	6		T43	10		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	2		T16	5		T249	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	10		T35	3		T26	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T87	7		T40	1		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T138	11		T87	4		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T218	14		T163	10		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T38	4		T133	9		T26	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	3		T224	3		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	1		T86	11		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T135	9		T19	7		T250	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T183	12		T251	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T163	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T240	11		T183	12		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T241	1		T242	13		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T42	17		T15	5		T27	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T163	1		T234	7		T175	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	2		T234	10		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	6		T7	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	1		T13	9		T42	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T134	1		T36	6		T133	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T112	1		T131	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	3		T45	1		T43	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	1		T142	5		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T113	1		T137	1		T26	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T136	1		T16	9		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T2	12		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	5		T14	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T136	1		T87	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	1		T40	3		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	1		T45	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T112	1		T37	6		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1864	1			T1	2		T8	1		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T183	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T241	11		T242	10		T243	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	15		T15	2		T27	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T163	12		T234	6		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	3		T234	13		T153	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T113	10		T86	14		T162	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	9		T42	9		T137	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T36	2		T133	11		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	8		T131	17		T38	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T43	12		T15	11		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T113	11		T234	13		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T113	6		T163	2		T253	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	5		T248	1		T254	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	10		T35	3		T43	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	2		T87	7		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T87	4		T160	5		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	1		T163	10		T238	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	4		T133	9		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T37	3		T218	14		T224	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1166	1			T1	1		T8	12		T11	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3