Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24044

1

T1

45

T3

6

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3534

1

T2

22

T3

5

T7

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21711

1

T1

42

T2

22

T3

5

auto[1]

5867

1

T1

3

T3

6

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T225	35		T270	10		-	-
values[0]	49	1			T259	2		T291	19		T295	12
values[1]	820	1			T7	1		T112	1		T113	12
values[2]	785	1			T3	5		T12	3		T37	9
values[3]	535	1			T9	9		T45	2		T136	1
values[4]	760	1			T2	22		T13	5		T134	1
values[5]	2864	1			T1	3		T8	13		T11	13
values[6]	605	1			T1	1		T3	6		T113	7
values[7]	788	1			T45	1		T132	1		T135	21
values[8]	623	1			T7	1		T112	1		T134	1
values[9]	1192	1			T7	1		T12	1		T13	18
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	970	1			T7	1		T112	1		T35	5
values[1]	765	1			T3	5		T9	9		T12	3
values[2]	671	1			T13	5		T134	1		T45	1
values[3]	2945	1			T1	3		T2	22		T8	13
values[4]	533	1			T3	6		T181	1		T87	20
values[5]	719	1			T42	32		T132	3		T26	7
values[6]	632	1			T1	1		T113	7		T45	1
values[7]	692	1			T7	2		T12	1		T112	1
values[8]	929	1			T13	18		T131	20		T42	18
values[9]	177	1			T40	4		T217	1		T228	2
minimum	18545	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T112	1		T35	2		T86	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T7	1		T181	1		T38	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	1		T45	1		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	5		T12	3		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T134	1		T136	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	2		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T1	2		T8	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	12		T113	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	6		T194	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T181	1		T87	13		T31	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	4		T163	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T42	17		T132	3		T162	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	1		T36	6		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T113	1		T45	1		T135	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T112	1		T134	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	2		T12	1		T133	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T131	2		T42	9		T166	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	9		T131	1		T43	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T217	1		T228	1		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T40	3		T150	1		T197	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18385	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T275	1		T295	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	3		T16	5		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T38	5		T137	12		T87	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	8		T37	3		T26	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T113	11		T224	3		T86	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	2		T28	3		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	3		T218	14		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T1	1		T8	12		T11	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	10		T113	10		T138	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T144	2		T160	5		T196	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T87	7		T234	6		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	3		T163	12		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T42	15		T162	12		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T36	2		T142	12		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T113	6		T135	9		T17	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T85	1		T87	4		T15	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	11		T27	2		T135	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T131	6		T42	9		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	9		T131	11		T43	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T228	1		T170	11		T299	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T40	1		T197	10		T270	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T225	15		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T259	1		T291	19		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T295	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T112	1		T35	2		T86	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	1		T113	1		T181	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T37	6		T198	1		T235	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	5		T12	3		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	1		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T45	1		T218	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T134	1		T137	1		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	12		T13	2		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T1	2		T8	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T113	1		T181	1		T87	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	1		T3	6		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T113	1		T42	17		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T142	14		T194	1		T238	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T45	1		T132	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T112	1		T134	1		T36	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T27	11		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T131	2		T42	9		T166	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T7	1		T12	1		T13	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T225	20		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T270	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T259	1		T300	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T35	3		T16	5		T130	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T113	11		T137	12		T87	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	3		T226	6		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	5		T224	3		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T9	8		T15	2		T26	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T218	14		T138	11		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T133	9		T138	2		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	10		T13	3		T86	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T1	1		T8	12		T11	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T113	10		T87	7		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T26	3		T163	12		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T113	6		T42	15		T149	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T142	12		T238	8		T253	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T135	9		T162	12		T163	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T36	2		T87	4		T15	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T27	2		T135	17		T17	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T131	6		T42	9		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	9		T131	11		T43	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T112	1		T35	5		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T7	1		T181	1		T38	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	9		T45	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T12	1		T113	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T134	1		T136	1		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	4		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T1	2		T8	13		T11	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	11		T113	11		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	1		T194	1		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T181	1		T87	8		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T26	4		T163	13		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T42	16		T132	3		T162	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T36	5		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T113	7		T45	1		T135	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T112	1		T134	1		T85	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	2		T12	1		T133	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T131	8		T42	10		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T13	10		T131	12		T43	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T217	1		T228	2		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T40	4		T150	1		T197	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18513	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T275	2		T295	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T86	4		T16	6		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T38	6		T87	5		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	2		T26	13		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	4		T12	2		T86	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	3		T28	3		T234	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	1		T31	9		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T1	1		T41	13		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	11		T86	13		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	5		T160	5		T189	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T87	12		T31	6		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T26	3		T144	11		T236	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	16		T162	8		T236	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	3		T142	13		T238	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T135	11		T17	4		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T87	8		T15	1		T27	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	13		T27	10		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T42	8		T166	13		T26	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	8		T43	21		T142	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T170	10		T296	8		T301	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T197	6		T171	2		T266	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T291	18		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T295	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T225	21		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T270	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T259	2		T291	1		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T112	1		T35	5		T86	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T7	1		T113	12		T181	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T37	7		T198	1		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T3	1		T12	1		T38	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	9		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T45	1		T218	15		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T134	1		T137	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	11		T13	4		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T1	2		T8	13		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T113	11		T181	1		T87	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T3	1		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T113	7		T42	16		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T142	13		T194	1		T238	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	1		T132	1		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T112	1		T134	1		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T27	3		T135	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T131	8		T42	10		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T7	1		T12	1		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T225	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T291	18		T300	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T295	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T86	4		T16	6		T130	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T87	5		T89	12		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	2		T235	4		T148	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	4		T12	2		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T166	5		T15	3		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T86	2		T31	9		T162	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T133	10		T28	3		T29	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	11		T13	1		T86	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T1	1		T41	13		T239	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T87	12		T31	6		T160	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	5		T26	3		T144	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T42	16		T144	2		T236	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T142	13		T238	7		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T135	11		T162	8		T290	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T36	3		T87	8		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T27	10		T135	13		T17	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T42	8		T166	13		T26	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	8		T43	21		T133	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9