Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23983

1

T1

45

T3

6

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3595

1

T2

22

T3

5

T7

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21601

1

T1

42

T2

22

T3

5

auto[1]

5977

1

T1

3

T3

6

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T166	14		T26	10		T40	4
values[0]	34	1			T137	13		T268	1		T300	15
values[1]	829	1			T7	1		T112	1		T35	5
values[2]	730	1			T3	5		T12	3		T113	12
values[3]	619	1			T9	9		T45	2		T136	1
values[4]	701	1			T13	5		T134	1		T136	1
values[5]	2886	1			T1	3		T2	22		T8	13
values[6]	616	1			T3	6		T113	7		T42	32
values[7]	772	1			T1	1		T45	1		T132	1
values[8]	624	1			T7	1		T112	1		T134	1
values[9]	1018	1			T7	1		T12	1		T13	18
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	827	1			T7	1		T112	1		T35	5
values[1]	751	1			T3	5		T9	9		T12	3
values[2]	681	1			T13	5		T134	1		T45	1
values[3]	2899	1			T1	3		T2	22		T8	13
values[4]	620	1			T3	6		T14	3		T113	11
values[5]	684	1			T113	7		T42	32		T132	3
values[6]	631	1			T1	1		T45	1		T36	8
values[7]	671	1			T7	2		T12	1		T112	1
values[8]	943	1			T13	18		T131	20		T42	18
values[9]	170	1			T40	4		T228	2		T150	1
minimum	18701	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T112	1		T35	2		T86	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	1		T181	1		T38	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T45	1		T37	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	5		T12	3		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T134	1		T136	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	2		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T1	2		T8	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	12		T86	14		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	6		T14	1		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T113	1		T181	1		T87	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T42	17		T132	1		T26	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T113	1		T132	2		T162	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T36	6		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	1		T135	12		T17	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T112	1		T85	1		T87	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	2		T12	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T131	3		T42	9		T166	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	9		T43	23		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T228	1		T108	13		T170	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T40	3		T150	1		T197	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18440	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T137	1		T302	1		T219	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T35	3		T16	5		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	5		T87	8		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	8		T37	3		T226	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T113	11		T224	3		T86	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	2		T26	14		T234	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	3		T218	14		T28	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T1	1		T8	12		T11	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	10		T86	14		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	2		T144	2		T160	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T113	10		T87	7		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T42	15		T26	3		T163	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T113	6		T162	12		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	2		T142	12		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T135	9		T17	6		T163	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T85	1		T87	4		T15	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T133	11		T27	7		T135	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T131	17		T42	9		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	9		T43	22		T38	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T228	1		T108	8		T170	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T40	1		T197	10		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T137	12		T153	15		T303	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T166	14		T26	10		T217	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T40	3		T197	7		T304	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T268	1		T300	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T137	1		T305	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T112	1		T35	2		T86	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	1		T181	1		T87	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T37	6		T147	1		T235	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	5		T12	3		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	1		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T45	1		T218	1		T86	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T134	1		T137	1		T133	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	2		T136	1		T86	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T1	2		T8	1		T11	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	12		T113	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	6		T42	17		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T113	1		T132	1		T144	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T142	14		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	1		T132	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T112	1		T36	6		T87	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	1		T134	1		T27	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T131	3		T42	9		T85	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	1		T12	1		T13	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T175	20		T248	1		T108	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T40	1		T197	10		T171	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T300	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T137	12		T305	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T35	3		T16	5		T130	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T87	8		T32	11		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	3		T226	6		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T113	11		T38	5		T224	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T9	8		T15	2		T26	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T218	14		T86	11		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T133	9		T138	13		T272	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	3		T86	14		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T1	1		T8	12		T11	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	10		T113	10		T87	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T42	15		T26	3		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T113	6		T149	12		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T142	12		T238	8		T253	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T135	9		T162	12		T163	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T36	2		T87	4		T15	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T27	7		T135	17		T17	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T131	17		T42	9		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T13	9		T43	22		T38	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T112	1		T35	5		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T181	1		T38	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	9		T45	1		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	1		T12	1		T113	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T134	1		T136	1		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	4		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T1	2		T8	13		T11	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	11		T86	15		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T14	3		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T113	11		T181	1		T87	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T42	16		T132	1		T26	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T113	7		T132	2		T162	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T36	5		T142	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T45	1		T135	10		T17	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T112	1		T85	2		T87	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	2		T12	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T131	20		T42	10		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	10		T43	24		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T228	2		T108	9		T170	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T40	4		T150	1		T197	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18561	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T137	13		T302	1		T219	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T86	4		T16	6		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	6		T87	5		T89	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	2		T31	9		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	4		T12	2		T86	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	3		T26	13		T234	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	1		T28	3		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	1		T41	13		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	11		T86	13		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	5		T160	5		T189	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T87	12		T31	6		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T42	16		T26	3		T144	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T162	8		T236	16		T248	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	3		T142	13		T238	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T135	11		T17	4		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T87	8		T15	1		T236	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T133	13		T27	16		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T42	8		T166	13		T26	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	8		T43	21		T142	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T108	12		T170	10		T296	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T197	6		T266	1		T306	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T307	6		T291	18		T300	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T303	9		T266	1		T186	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T166	1		T26	1		T217	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T40	4		T197	11		T304	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T268	1		T300	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T137	13		T305	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T112	1		T35	5		T86	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	1		T181	1		T87	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T37	7		T147	1		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	1		T12	1		T113	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	9		T45	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	1		T218	15		T86	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T134	1		T137	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	4		T136	1		T86	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T1	2		T8	13		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	11		T113	11		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T42	16		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T113	7		T132	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T142	13		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	1		T132	1		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T112	1		T36	5		T87	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T134	1		T27	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T131	20		T42	10		T85	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T7	1		T12	1		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T166	13		T26	9		T175	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T197	6		T304	11		T171	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T300	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T86	4		T16	6		T130	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T87	5		T89	12		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	2		T235	4		T148	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	4		T12	2		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T15	3		T26	13		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T86	2		T28	3		T162	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T133	10		T166	5		T29	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	1		T86	13		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T1	1		T41	13		T239	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	11		T87	12		T31	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T3	5		T42	16		T26	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T144	2		T236	16		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T142	13		T238	7		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T135	11		T162	8		T254	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T36	3		T87	8		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	16		T135	13		T17	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T42	8		T29	11		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	8		T43	21		T133	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9