Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24140

1

T1

45

T3

11

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3438

1

T2

22

T7

1

T9

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21608

1

T1

45

T3

6

T4

174

auto[1]

5970

1

T2

22

T3

5

T8

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T135	31		T217	1		T147	1
values[0]	67	1			T26	10		T194	1		T20	32
values[1]	595	1			T2	22		T12	1		T112	1
values[2]	848	1			T14	3		T113	12		T134	1
values[3]	485	1			T3	6		T45	1		T37	9
values[4]	742	1			T7	1		T131	12		T166	14
values[5]	2955	1			T7	1		T8	13		T9	9
values[6]	608	1			T1	1		T112	1		T45	1
values[7]	656	1			T3	5		T12	3		T13	5
values[8]	706	1			T7	1		T13	18		T113	7
values[9]	1143	1			T1	3		T36	8		T38	5
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	581	1			T112	1		T42	32		T136	1
values[1]	719	1			T14	3		T113	12		T134	1
values[2]	571	1			T3	6		T37	9		T38	15
values[3]	3062	1			T7	1		T8	13		T11	13
values[4]	575	1			T7	1		T9	9		T113	11
values[5]	691	1			T1	1		T112	1		T134	1
values[6]	605	1			T3	5		T7	1		T12	3
values[7]	783	1			T113	7		T45	1		T43	24
values[8]	1011	1			T137	13		T85	2		T86	5
values[9]	168	1			T1	3		T36	8		T38	5
minimum	18812	1			T1	41		T2	22		T4	174

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T112	1		T42	17		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T224	1		T162	22		T236	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T113	1		T134	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T136	1		T15	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	6		T37	6		T38	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T86	3		T26	4		T17	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1709	1			T7	1		T8	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T131	1		T166	14		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T113	1		T131	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	1		T9	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T112	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	1		T181	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	5		T7	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	3		T13	9		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T113	1		T43	12		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	1		T133	11		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T137	1		T86	5		T32	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T85	1		T16	9		T29	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T1	2		T275	1		T265	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T36	6		T38	1		T146	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18419	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	12		T194	1		T20	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T42	15		T238	8		T175	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T224	3		T162	13		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T113	11		T160	2		T228	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	2		T15	2		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T37	3		T38	5		T274	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T86	11		T26	3		T17	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T8	12		T11	11		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T131	11		T222	3		T225	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T113	10		T131	6		T87	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	8		T42	9		T218	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T163	12		T234	13		T254	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T138	13		T39	1		T162	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	3		T26	14		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	9		T35	3		T162	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T113	6		T43	12		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T133	9		T135	9		T142	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T137	12		T32	11		T135	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T85	1		T16	5		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T1	1		T275	1		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T36	2		T38	4		T308	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T2	10		T20	13		T245	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T135	14		T222	17		T57	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T217	1		T147	1		T19	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T26	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T194	1		T20	19		T245	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	1		T112	1		T42	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	12		T236	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T113	1		T134	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	1		T136	1		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	6		T45	1		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T86	3		T26	4		T17	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	1		T163	1		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T131	1		T166	14		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1639	1			T8	1		T11	2		T90	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T9	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	1		T112	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T132	1		T138	1		T162	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	5		T13	2		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	3		T134	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	1		T113	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	9		T45	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	2		T137	1		T86	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T36	6		T38	1		T133	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T135	17		T222	12		T57	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T231	14		T250	15		T308	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T20	13		T245	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	15		T15	11		T238	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	10		T149	2		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T113	11		T160	2		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	2		T224	3		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T37	3		T38	5		T272	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T86	11		T26	3		T17	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T163	10		T130	1		T274	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T131	11		T222	3		T225	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T8	12		T11	11		T113	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	8		T42	9		T218	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	5		T163	12		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T138	2		T162	4		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	3		T43	12		T26	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T138	11		T39	1		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T113	6		T133	11		T87	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	9		T35	3		T135	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T137	12		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T36	2		T38	4		T133	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T112	1		T42	16		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T224	4		T162	14		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T113	12		T134	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	3		T136	1		T15	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T37	7		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T86	12		T26	4		T17	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T7	1		T8	13		T11	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T131	12		T166	1		T222	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T113	11		T131	7		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T9	9		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T112	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T134	1		T181	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T7	1		T13	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T13	10		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T113	7		T43	13		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T45	1		T133	10		T135	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T137	13		T86	1		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T85	2		T16	8		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T1	2		T275	2		T265	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T36	5		T38	5		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18579	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	11		T194	1		T20	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T42	16		T145	9		T238	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T162	21		T236	6		T248	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T160	7		T175	12		T225	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	3		T144	11		T235	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	5		T37	2		T38	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T86	2		T26	3		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T41	13		T43	10		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T166	13		T225	14		T309	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T166	5		T87	5		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T42	8		T86	13		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T234	5		T20	1		T254	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	3		T162	4		T160	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	4		T13	1		T89	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	2		T13	8		T162	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T43	11		T133	13		T87	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T133	10		T135	11		T142	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T86	4		T32	13		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	6		T29	14		T31	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T1	1		T265	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T36	3		T146	15		T308	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T15	1		T26	9		T310	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	11		T20	14		T152	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T135	18		T222	13		T57	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T217	1		T147	1		T19	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T26	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T194	1		T20	18		T245	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T112	1		T42	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	11		T236	1		T149	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T113	12		T134	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	3		T136	1		T224	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	1		T45	1		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T86	12		T26	4		T17	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	1		T163	11		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T131	12		T166	1		T217	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T8	13		T11	13		T90	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T9	9		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T112	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T132	1		T138	3		T162	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	1		T13	4		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T134	1		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	1		T113	7		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	10		T45	1		T35	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T1	2		T137	13		T86	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T36	5		T38	5		T133	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T135	13		T222	16		T57	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T250	10		T308	13		T311	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T26	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T20	14		T245	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T42	16		T15	1		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	11		T236	6		T248	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T160	7		T175	12		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	3		T162	21		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	5		T37	2		T38	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T86	2		T26	3		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T130	1		T237	2		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T166	13		T254	11		T225	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T41	13		T43	10		T166	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T42	8		T86	13		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T27	6		T234	5		T297	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T162	4		T144	2		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	4		T13	1		T43	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	2		T39	3		T162	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T133	13		T87	20		T89	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	8		T135	11		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T86	4		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T36	3		T133	10		T16	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9