Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23751

1

T1

44

T2

22

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3827

1

T1

1

T3

11

T7

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21727

1

T1

44

T2

22

T3

6

auto[1]

5851

1

T1

1

T3

5

T8

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	256	1			T113	19		T86	5		T87	13
values[0]	27	1			T264	21		T251	6		-	-
values[1]	747	1			T2	22		T7	1		T134	1
values[2]	741	1			T181	1		T43	24		T138	12
values[3]	640	1			T3	5		T112	1		T137	1
values[4]	3004	1			T1	3		T8	13		T11	13
values[5]	640	1			T12	1		T36	8		T218	15
values[6]	621	1			T113	11		T137	1		T166	6
values[7]	600	1			T3	6		T7	1		T13	5
values[8]	780	1			T37	9		T132	1		T137	13
values[9]	1010	1			T1	1		T7	1		T9	9
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	689	1			T2	22		T7	1		T134	1
values[1]	832	1			T3	5		T42	18		T181	1
values[2]	579	1			T112	2		T134	1		T43	24
values[3]	2956	1			T1	3		T8	13		T11	13
values[4]	735	1			T12	1		T36	8		T218	15
values[5]	590	1			T113	11		T43	21		T137	1
values[6]	573	1			T3	6		T7	1		T13	5
values[7]	755	1			T37	9		T132	1		T137	13
values[8]	1037	1			T1	1		T7	1		T9	9
values[9]	113	1			T217	1		T274	14		T200	3
minimum	18719	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	12		T134	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T16	9		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T42	9		T181	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T3	5		T135	14		T162	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T112	1		T137	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T112	1		T134	1		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	2		T8	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	1		T42	17		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	1		T36	6		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T218	1		T135	12		T162	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	1		T43	11		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T137	1		T85	1		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	14		T27	7		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	6		T7	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	4		T32	14		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T37	6		T132	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T45	1		T131	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T1	1		T7	1		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T217	1		T200	3		T297	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T274	1		T312	1		T246	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18438	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T143	1		T313	1		T314	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	10		T39	1		T160	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	5		T163	2		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T42	9		T138	11		T86	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T135	17		T162	13		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T224	3		T27	2		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T43	12		T248	1		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	1		T8	12		T11	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T42	15		T38	5		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	2		T162	12		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T218	14		T135	9		T162	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T113	10		T43	10		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T85	1		T26	14		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T133	11		T27	5		T226	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	3		T38	4		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	11		T32	11		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	3		T137	12		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T131	11		T87	4		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	8		T14	2		T113	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T297	2		T281	6		T278	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T274	13		T246	10		T315	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T313	6		T314	12		T264	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T87	9		T40	3		T146	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T113	2		T86	5		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T251	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T264	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	12		T134	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T16	9		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T181	1		T138	1		T86	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T43	12		T135	14		T162	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T112	1		T137	1		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	5		T166	14		T31	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T1	2		T8	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T112	1		T134	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	1		T36	6		T26	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T218	1		T135	12		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T113	1		T166	6		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T137	1		T85	1		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T43	11		T133	14		T27	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	6		T7	1		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	4		T32	14		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T37	6		T132	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T45	1		T131	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T1	1		T7	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T87	4		T40	1		T316	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T113	17		T274	13		T229	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T251	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T264	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	10		T42	9		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	5		T163	2		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T138	11		T86	14		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T43	12		T135	17		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T224	3		T86	11		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T142	12		T151	8		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T1	1		T8	12		T11	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T42	15		T38	5		T162	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T36	2		T162	12		T160	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T218	14		T135	9		T232	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T113	10		T28	3		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T85	1		T26	14		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T43	10		T133	11		T27	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	3		T38	4		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	11		T32	11		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T37	3		T137	12		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T131	11		T163	12		T272	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	8		T14	2		T131	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	11		T134	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T16	8		T163	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T42	10		T181	1		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	1		T135	18		T162	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T112	1		T137	1		T224	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T112	1		T134	1		T43	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T1	2		T8	13		T11	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	1		T42	16		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T36	5		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T218	15		T135	10		T162	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T113	11		T43	11		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T137	1		T85	2		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T133	12		T27	6		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T7	1		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T15	14		T32	12		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T37	7		T132	1		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T45	1		T131	12		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T1	1		T7	1		T9	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T217	1		T200	3		T297	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T274	14		T312	1		T246	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18588	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T143	1		T313	7		T314	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	11		T39	3		T29	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	6		T235	4		T261	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T42	8		T86	15		T89	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	4		T135	13		T162	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T27	10		T20	1		T221	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T43	11		T166	13		T31	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	1		T13	8		T41	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	16		T38	6		T236	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T36	3		T166	5		T26	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T135	11		T162	4		T130	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T43	10		T28	3		T248	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	13		T234	9		T236	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T133	13		T27	6		T148	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	5		T13	1		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	1		T32	13		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T37	2		T26	3		T20	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T87	8		T29	14		T146	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	2		T86	4		T87	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T297	2		T281	5		T278	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T246	10		T291	18		T317	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T144	11		T234	6		T110	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T264	10		T318	1		T319	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T87	5		T40	4		T146	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T113	19		T86	1		T274	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T251	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T264	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	11		T134	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	1		T16	8		T163	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T181	1		T138	12		T86	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T43	13		T135	18		T162	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T112	1		T137	1		T224	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	1		T166	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T1	2		T8	13		T11	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T112	1		T134	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T36	5		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T218	15		T135	10		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T113	11		T166	1		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T137	1		T85	2		T26	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	11		T133	12		T27	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T7	1		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	14		T32	12		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T37	7		T132	1		T137	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	1		T131	12		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T1	1		T7	1		T9	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T87	8		T146	15		T304	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T86	4		T261	3		T229	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T264	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	11		T42	8		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	6		T235	4		T261	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T86	13		T160	7		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T43	11		T135	13		T162	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T86	2		T89	12		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	4		T166	13		T31	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T1	1		T13	8		T41	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T42	16		T38	6		T31	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T36	3		T26	9		T162	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T135	11		T236	8		T248	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T166	5		T28	3		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T26	13		T130	1		T234	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T43	10		T133	13		T27	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	5		T13	1		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	1		T32	13		T263	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	2		T233	13		T222	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T29	14		T272	2		T195	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	2		T87	5		T26	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9