Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24022

1

T1

45

T2

22

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3556

1

T3

11

T7

1

T9

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21501

1

T1

45

T2

22

T3

5

auto[1]

6077

1

T3

6

T7

1

T8

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T197	17		T320	12		T58	2
values[0]	118	1			T20	32		T259	31		T246	21
values[1]	684	1			T3	5		T13	18		T14	3
values[2]	680	1			T45	1		T43	21		T132	1
values[3]	561	1			T1	1		T7	2		T12	3
values[4]	693	1			T2	22		T112	1		T131	7
values[5]	746	1			T9	9		T134	2		T181	1
values[6]	635	1			T132	1		T137	1		T26	7
values[7]	916	1			T3	6		T12	1		T13	5
values[8]	2993	1			T1	3		T8	13		T11	13
values[9]	1009	1			T7	1		T113	7		T35	5
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	827	1			T3	5		T14	3		T113	12
values[1]	671	1			T12	3		T13	18		T43	21
values[2]	589	1			T1	1		T7	2		T112	1
values[3]	793	1			T2	22		T131	7		T37	9
values[4]	671	1			T134	1		T181	1		T218	15
values[5]	805	1			T9	9		T134	1		T45	1
values[6]	3001	1			T3	6		T8	13		T11	13
values[7]	631	1			T1	3		T43	24		T136	1
values[8]	895	1			T7	1		T113	11		T36	8
values[9]	123	1			T113	7		T35	5		T217	1
minimum	18572	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	1		T131	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	5		T113	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	3		T13	9		T43	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T136	1		T86	14		T26	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T7	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T38	1		T31	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	12		T86	3		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T131	1		T37	6		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T181	1		T87	13		T26	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T134	1		T218	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T134	1		T45	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	1		T132	1		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T8	1		T11	2		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	6		T12	1		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	2		T26	14		T236	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	12		T136	1		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	1		T113	1		T42	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T36	6		T42	17		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T113	1		T35	2		T20	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T217	1		T238	8		T274	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18398	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	1		T321	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	2		T131	11		T28	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T113	11		T85	1		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	9		T43	10		T27	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T86	14		T163	2		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T162	4		T248	14		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T38	4		T32	11		T175	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	10		T86	11		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T131	6		T37	3		T38	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T87	7		T26	3		T27	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T218	14		T137	12		T272	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T133	11		T228	2		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	8		T39	1		T87	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T8	12		T11	11		T247	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	3		T15	11		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	1		T26	14		T228	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T43	12		T133	9		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T113	10		T42	9		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	2		T42	15		T224	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T113	6		T35	3		T322	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T238	8		T274	13		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T197	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T320	1		T58	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T20	19		T187	7		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T259	17		T246	11		T300	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	9		T14	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	5		T113	1		T26	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	11		T137	1		T27	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	1		T132	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T7	1		T12	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	1		T136	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	12		T112	1		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T131	1		T37	6		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T134	1		T181	1		T86	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T134	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	1		T26	4		T29	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T132	1		T143	2		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	2		T133	14		T233	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	6		T12	1		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T1	2		T8	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T112	1		T43	12		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	1		T113	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T36	6		T42	17		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T197	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T320	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T20	13		T323	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T259	14		T246	10		T300	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	9		T14	2		T131	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T113	11		T16	5		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	10		T27	2		T28	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T85	1		T86	14		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T40	1		T130	1		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T38	4		T32	11		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	10		T142	12		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T131	6		T37	3		T38	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T86	11		T87	7		T27	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	8		T218	14		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T26	3		T40	1		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T272	3		T226	6		T153	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T133	11		T233	6		T248	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	3		T39	1		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T1	1		T8	12		T11	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	12		T133	9		T15	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T113	6		T35	3		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	2		T42	15		T224	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	3		T131	12		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T113	12		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	1		T13	10		T43	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T136	1		T86	15		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T7	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	1		T38	5		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	11		T86	12		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T131	7		T37	7		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T181	1		T87	8		T26	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T134	1		T218	15		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T134	1		T45	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	9		T132	1		T39	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T8	13		T11	13		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T12	1		T13	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	2		T26	15		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	13		T136	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T7	1		T113	11		T42	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T36	5		T42	16		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T113	7		T35	5		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T217	1		T238	9		T274	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18543	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T275	2		T321	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T89	12		T28	3		T234	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	4		T16	6		T162	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	2		T13	8		T43	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T86	13		T26	9		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T162	4		T148	6		T248	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T31	9		T32	13		T236	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	11		T86	2		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	2		T38	6		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T87	12		T26	3		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T236	10		T272	2		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T133	13		T144	2		T233	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	3		T87	8		T245	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T41	13		T239	33		T164	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	5		T13	1		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	1		T26	13		T236	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	11		T133	10		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T42	8		T166	5		T87	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	3		T42	16		T86	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T20	1		T324	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T238	7		T109	9		T325	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T20	14		T276	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T197	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T320	12		T58	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T20	18		T187	1		T323	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T259	15		T246	11		T300	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	10		T14	3		T131	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	1		T113	12		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T43	11		T137	1		T27	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	1		T132	1		T85	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T7	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	1		T136	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	11		T112	1		T142	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T131	7		T37	7		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T134	1		T181	1		T86	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	9		T134	1		T218	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T137	1		T26	4		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T132	1		T143	2		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T45	2		T133	12		T233	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T12	1		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	2		T8	13		T11	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T112	1		T43	13		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T7	1		T113	7		T35	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T36	5		T42	16		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T197	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T58	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T20	14		T187	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T259	16		T246	10		T300	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T89	12		T234	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	4		T26	9		T16	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T43	10		T27	10		T28	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T86	13		T29	11		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	2		T130	1		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T31	9		T32	13		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	11		T142	13		T309	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	2		T38	6		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T86	2		T87	12		T27	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T87	8		T145	6		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T26	3		T29	14		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T236	10		T272	2		T152	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T133	13		T233	5		T248	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	5		T13	1		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T1	1		T41	13		T42	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	11		T133	10		T166	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T166	5		T87	5		T135	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T36	3		T42	16		T86	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9