Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23691

1

T1

44

T2

22

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3887

1

T1

1

T3

11

T7

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21710

1

T1

44

T2

22

T3

6

auto[1]

5868

1

T1

1

T3

5

T8

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	56	1			T259	20		T246	21		T326	1
values[0]	61	1			T18	3		T264	21		T327	26
values[1]	706	1			T2	22		T7	1		T134	1
values[2]	759	1			T181	1		T138	12		T86	28
values[3]	621	1			T3	5		T112	1		T43	24
values[4]	2952	1			T1	3		T8	13		T11	13
values[5]	696	1			T12	1		T36	8		T181	1
values[6]	619	1			T113	11		T137	1		T166	6
values[7]	592	1			T3	6		T7	1		T13	5
values[8]	793	1			T37	9		T132	1		T137	13
values[9]	1211	1			T1	1		T7	1		T9	9
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T2	22		T7	1		T134	1
values[1]	773	1			T3	5		T181	1		T138	12
values[2]	698	1			T112	2		T134	1		T43	24
values[3]	2938	1			T1	3		T8	13		T11	13
values[4]	701	1			T12	1		T36	8		T181	1
values[5]	596	1			T13	5		T113	11		T43	21
values[6]	548	1			T3	6		T7	1		T38	5
values[7]	732	1			T37	9		T132	1		T137	13
values[8]	1062	1			T1	1		T9	9		T14	3
values[9]	146	1			T7	1		T12	3		T113	7
minimum	18536	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	12		T134	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	1		T16	9		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T181	1		T138	1		T86	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T3	5		T31	7		T142	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T112	1		T137	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T112	1		T134	1		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T1	2		T8	1		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	1		T42	17		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T36	6		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T181	1		T218	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T113	1		T43	11		T302	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	2		T85	1		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T133	14		T27	7		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	6		T7	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	4		T32	14		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T37	6		T132	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T45	1		T131	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T1	1		T9	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T217	1		T297	3		T281	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T7	1		T12	3		T113	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T183	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	10		T42	9		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	5		T163	2		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T138	11		T86	25		T102	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T142	12		T234	13		T228	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T224	3		T15	2		T27	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	12		T135	17		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	1		T8	12		T11	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T42	15		T38	5		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T36	2		T28	3		T162	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T218	14		T162	4		T232	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T113	10		T43	10		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	3		T85	1		T26	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T133	11		T27	5		T229	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	4		T133	9		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	11		T32	11		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	3		T137	12		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T131	11		T87	4		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	8		T14	2		T113	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T297	2		T281	6		T328	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T113	6		T274	13		T246	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T183	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T259	14		T326	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	11		T329	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T327	14		T251	1		T330	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T18	2		T264	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	12		T134	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T16	9		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T181	1		T138	1		T86	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T135	14		T162	22		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T112	1		T137	1		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	5		T43	12		T166	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T1	2		T8	1		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T112	1		T134	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T36	6		T26	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T181	1		T38	10		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T113	1		T166	6		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T137	1		T85	1		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T43	11		T133	14		T27	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	6		T7	1		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	4		T32	14		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T37	6		T132	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T45	1		T131	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T1	1		T7	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T259	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T246	10		T329	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T327	12		T251	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T18	1		T264	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	10		T42	9		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	5		T313	6		T314	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T138	11		T86	14		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T135	17		T162	13		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T224	3		T86	11		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	12		T151	8		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T1	1		T8	12		T11	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T42	15		T162	4		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	2		T162	12		T160	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	5		T218	14		T135	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T113	10		T28	3		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T85	1		T26	14		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	10		T133	11		T27	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	3		T38	4		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	11		T32	11		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T37	3		T137	12		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T131	11		T87	4		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T9	8		T14	2		T113	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T2	11		T134	1		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	1		T16	8		T163	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T181	1		T138	12		T86	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	1		T31	1		T142	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T112	1		T137	1		T224	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T112	1		T134	1		T43	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T1	2		T8	13		T11	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	1		T42	16		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T36	5		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T181	1		T218	15		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T113	11		T43	11		T302	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	4		T85	2		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T133	12		T27	6		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T7	1		T38	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	14		T32	12		T40	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T37	7		T132	1		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T45	1		T131	12		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T1	1		T9	9		T14	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T217	1		T297	3		T281	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T7	1		T12	1		T113	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T183	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	11		T42	8		T39	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	6		T235	4		T261	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T86	15		T309	15		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T3	4		T31	6		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T89	12		T15	3		T27	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	11		T166	13		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T1	1		T13	8		T41	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T42	16		T38	6		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	3		T166	5		T28	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T162	4		T145	9		T248	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T43	10		T238	7		T233	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	1		T26	13		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T133	13		T27	6		T254	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	5		T133	10		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T32	13		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	2		T26	3		T20	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T87	8		T29	14		T146	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T86	4		T87	5		T17	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T297	2		T281	5		T304	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T12	2		T246	10		T291	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T183	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T259	7		T326	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T246	11		T329	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T327	13		T251	6		T330	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T18	3		T264	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	11		T134	1		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T16	8		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T181	1		T138	12		T86	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T135	18		T162	14		T163	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T112	1		T137	1		T224	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T43	13		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	2		T8	13		T11	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T112	1		T134	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	1		T36	5		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T181	1		T38	9		T218	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T113	11		T166	1		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	1		T85	2		T26	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	11		T133	12		T27	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T7	1		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	14		T32	12		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T37	7		T132	1		T137	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T45	1		T131	12		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T1	1		T7	1		T9	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T246	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T327	13		T330	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T264	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	11		T42	8		T39	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T16	6		T235	4		T261	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T86	13		T160	7		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T135	13		T162	21		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T86	2		T89	12		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	4		T43	11		T166	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T1	1		T13	8		T41	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	16		T31	9		T162	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T36	3		T26	9		T162	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	6		T135	11		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T166	5		T28	3		T233	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T26	13		T130	1		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T43	10		T133	13		T27	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	5		T13	1		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T32	13		T263	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T37	2		T233	13		T259	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T87	8		T29	14		T146	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T12	2		T86	4		T87	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9