Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24033

1

T1

45

T2

22

T3

6

auto[ADC_CTRL_FILTER_COND_OUT]

3545

1

T3

5

T7

1

T9

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21441

1

T1

45

T2

22

T3

11

auto[1]

6137

1

T7

1

T8

13

T11

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	185	1			T181	1		T224	4		T86	5
values[0]	80	1			T259	31		T187	7		T331	8
values[1]	662	1			T3	5		T14	3		T113	12
values[2]	721	1			T12	3		T13	18		T43	21
values[3]	600	1			T1	1		T7	2		T112	1
values[4]	638	1			T2	22		T131	7		T37	9
values[5]	790	1			T9	9		T134	2		T181	1
values[6]	615	1			T45	1		T132	1		T137	1
values[7]	859	1			T3	6		T12	1		T13	5
values[8]	3071	1			T1	3		T8	13		T11	13
values[9]	845	1			T7	1		T113	18		T35	5
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	642	1			T113	12		T45	1		T132	1
values[1]	635	1			T12	3		T13	18		T43	21
values[2]	630	1			T1	1		T7	2		T112	1
values[3]	759	1			T2	22		T131	7		T37	9
values[4]	696	1			T9	9		T134	2		T181	1
values[5]	797	1			T45	1		T132	1		T137	1
values[6]	2994	1			T3	6		T8	13		T11	13
values[7]	645	1			T1	3		T42	18		T43	24
values[8]	893	1			T7	1		T113	18		T35	5
values[9]	103	1			T224	4		T274	14		T20	2
minimum	18784	1			T1	41		T3	5		T4	174

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	1		T89	13		T28	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T113	1		T45	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	3		T13	9		T27	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T43	11		T136	1		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	1		T7	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	1		T38	1		T31	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	12		T86	3		T142	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T131	1		T37	6		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T134	1		T181	1		T87	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	1		T134	1		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T45	1		T137	1		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T132	1		T39	9		T87	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T3	6		T8	1		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	1		T13	2		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	2		T42	9		T26	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T43	12		T136	1		T133	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	1		T113	1		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T113	1		T36	6		T42	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T20	2		T332	1		T199	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T224	1		T274	1		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18438	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T3	5		T147	1		T259	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T28	3		T234	13		T232	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T113	11		T16	5		T162	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	9		T27	2		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	10		T85	1		T86	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T40	1		T175	8		T248	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	4		T32	11		T163	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	10		T86	11		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T131	6		T37	3		T38	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T87	7		T26	3		T27	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	8		T218	14		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T133	11		T228	2		T233	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	1		T87	4		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T8	12		T11	11		T247	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	3		T15	11		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	1		T42	9		T26	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T43	12		T133	9		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T113	6		T35	3		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T113	10		T36	2		T42	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T332	14		T199	3		T334	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T224	3		T274	13		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	2		T14	2		T131	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T259	14		T246	10		T275	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T181	1		T87	6		T194	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T224	1		T86	5		T217	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T187	7		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T259	17		T331	1		T335	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T131	1		T89	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	5		T113	1		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	3		T13	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	11		T132	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	1		T7	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T136	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	12		T40	3		T142	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T131	1		T37	6		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T134	1		T181	1		T86	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	1		T134	1		T218	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	1		T137	1		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	1		T143	2		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	6		T45	1		T133	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	1		T13	2		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1646	1			T1	2		T8	1		T11	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T43	12		T136	1		T133	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	1		T113	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T113	1		T36	6		T42	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T87	8		T314	12		T197	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T224	3		T336	9		T264	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T323	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T259	14		T331	7		T335	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	2		T131	11		T234	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T113	11		T16	5		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	9		T27	2		T28	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T43	10		T85	1		T86	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T130	1		T149	2		T248	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T38	4		T32	11		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	10		T40	1		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	6		T37	3		T38	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T86	11		T87	7		T27	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	8		T218	14		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T26	3		T228	2		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T272	3		T226	6		T153	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T133	11		T233	6		T248	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	3		T39	1		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T1	1		T8	12		T11	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T43	12		T133	9		T15	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T113	6		T35	3		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T113	10		T36	2		T42	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	1		T89	1		T28	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T113	12		T45	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T13	10		T27	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T43	11		T136	1		T85	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T7	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	1		T38	5		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	11		T86	12		T142	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T131	7		T37	7		T38	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T134	1		T181	1		T87	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	9		T134	1		T218	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	1		T137	1		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T132	1		T39	7		T87	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T3	1		T8	13		T11	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T13	4		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T42	10		T26	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T43	13		T136	1		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T7	1		T113	7		T35	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T113	11		T36	5		T42	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T20	1		T332	15		T199	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T224	4		T274	14		T333	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18614	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T3	1		T147	1		T259	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T89	12		T28	3		T234	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	6		T162	21		T17	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	2		T13	8		T27	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	10		T86	13		T26	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T236	8		T175	8		T148	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T31	9		T32	13		T146	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	11		T86	2		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T37	2		T38	6		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T87	12		T26	3		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T236	10		T272	2		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T133	13		T144	2		T233	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	3		T87	8		T245	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T3	5		T41	13		T239	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	1		T15	1		T234	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	1		T42	8		T26	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T43	11		T133	10		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T166	5		T87	5		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	3		T42	16		T86	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T20	1		T199	3		T334	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T109	9		T325	5		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T234	6		T246	13		T297	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T3	4		T259	16		T246	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T181	1		T87	9		T194	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T224	4		T86	1		T217	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T187	1		T323	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T259	15		T331	8		T335	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	3		T131	12		T89	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	1		T113	12		T45	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T13	10		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T43	11		T132	1		T85	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T7	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	1		T136	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	11		T40	4		T142	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T131	7		T37	7		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T134	1		T181	1		T86	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	9		T134	1		T218	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T45	1		T137	1		T26	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T132	1		T143	2		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	1		T45	1		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	1		T13	4		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T1	2		T8	13		T11	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T43	13		T136	1		T133	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T7	1		T113	7		T35	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T113	11		T36	5		T42	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T87	5		T197	6		T184	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T86	4		T336	10		T109	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T187	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T259	16		T335	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T89	12		T234	15		T20	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	4		T16	6		T162	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	2		T13	8		T27	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T43	10		T86	13		T26	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T130	1		T236	8		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T31	9		T32	13		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	11		T142	13		T175	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T37	2		T38	6		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T86	2		T87	12		T27	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T87	8		T145	6		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	3		T29	14		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T236	10		T272	2		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	5		T133	13		T233	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	1		T39	3		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T1	1		T41	13		T42	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T43	11		T133	10		T166	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T166	5		T135	13		T160	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T36	3		T42	16		T31	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9