Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T13	4		T42	16		T15	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	1		T7	1		T113	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	1		T181	1		T85	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T8	13		T11	13		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	10		T131	12		T42	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T134	1		T45	1		T36	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	9		T112	1		T131	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T43	13		T15	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T113	12		T136	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T113	7		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	3		T131	1		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	11		T35	5		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T45	1		T87	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	1		T136	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T218	15		T31	1		T163	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	1		T45	1		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T37	7		T224	4		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T1	2		T132	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T112	1		T135	10		T19	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T150	1		T183	13		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18525	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T163	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	1		T42	16		T15	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	5		T234	6		T175	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T245	4		T246	10		T197	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1284	1			T41	13		T86	13		T162	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	8		T42	8		T86	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T36	3		T133	13		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	6		T29	14		T162	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	2		T43	11		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T142	4		T234	5		T254	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T43	10		T32	13		T255	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	6		T249	10		T221	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	11		T26	13		T17	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	4		T87	12		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T87	8		T160	5		T20	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T31	6		T236	10		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T133	10		T166	13		T89	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	2		T160	7		T145	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	1		T166	5		T86	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T135	11		T254	11		T250	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T183	11		T244	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T240	1		T183	13		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T241	12		T242	11		T243	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T42	16		T15	4		T27	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T163	13		T234	7		T175	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	4		T234	14		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	1		T7	1		T113	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T13	10		T42	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	1		T36	5		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	9		T112	1		T131	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T45	1		T43	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T113	12		T142	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T113	7		T137	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	1		T16	8		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T2	11		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T14	3		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	1		T136	1		T87	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T45	1		T40	4		T163	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	1		T45	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T112	1		T37	7		T218	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1578	1			T1	2		T8	13		T11	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T240	10		T183	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T242	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	16		T15	3		T27	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T234	6		T175	8		T200	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T234	9		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	5		T86	13		T162	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	8		T42	8		T86	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	3		T133	13		T31	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T38	6		T29	14		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	2		T43	11		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T142	4		T234	5		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	9		T223	12		T256	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	6		T254	6		T225	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	11		T43	10		T26	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	4		T87	12		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T87	8		T160	5		T228	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T236	18		T145	9		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	10		T166	13		T86	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T37	2		T31	6		T135	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1452	1			T1	1		T41	13		T166	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9