Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21750

1

T1

41

T3

5

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

5828

1

T1

4

T2

22

T3

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21708

1

T1

42

T3

11

T4

174

auto[1]

5870

1

T1

3

T2

22

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	404	1			T112	1		T135	21		T232	12
values[0]	10	1			T257	8		T243	2		-	-
values[1]	805	1			T7	1		T42	32		T27	12
values[2]	900	1			T3	6		T13	5		T113	11
values[3]	716	1			T12	1		T13	18		T134	1
values[4]	589	1			T9	9		T12	3		T112	1
values[5]	550	1			T113	19		T137	1		T26	10
values[6]	546	1			T1	1		T2	22		T35	5
values[7]	595	1			T3	5		T7	1		T14	3
values[8]	867	1			T7	1		T45	2		T136	1
values[9]	3084	1			T1	3		T8	13		T11	13
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	800	1			T7	1		T13	5		T113	11
values[1]	3048	1			T3	6		T8	13		T11	13
values[2]	777	1			T13	18		T134	1		T45	1
values[3]	586	1			T9	9		T12	3		T112	1
values[4]	572	1			T1	1		T113	7		T43	21
values[5]	532	1			T2	22		T14	3		T35	5
values[6]	708	1			T3	5		T7	1		T45	1
values[7]	745	1			T7	1		T45	1		T136	1
values[8]	913	1			T1	3		T37	9		T132	1
values[9]	137	1			T112	1		T135	21		T19	9
minimum	18760	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	2		T42	17		T15	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T113	1		T238	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T85	1		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1650	1			T3	6		T8	1		T11	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	9		T45	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T134	1		T36	6		T133	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T112	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	3		T43	12		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	1		T142	5		T234	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T113	1		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	1		T131	1		T16	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	12		T35	2		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	5		T45	1		T87	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T132	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T218	1		T31	7		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T45	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T37	6		T224	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T1	2		T132	1		T166	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T112	1		T135	12		T19	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T150	1		T183	12		T244	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18435	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T163	1		T234	7		T175	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	3		T42	15		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T113	10		T238	8		T149	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T85	1		T245	10		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1004	1			T8	12		T11	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	9		T131	11		T42	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	2		T133	11		T228	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	8		T113	11		T131	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T43	12		T15	11		T163	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T234	13		T248	1		T254	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T113	6		T43	10		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T14	2		T16	5		T259	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	10		T35	3		T26	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T87	7		T40	1		T233	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T138	11		T87	4		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T218	14		T163	10		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T38	4		T133	9		T26	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	3		T224	3		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T1	1		T86	11		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T135	9		T19	7		T250	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T183	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T163	12		T234	6		T175	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T112	1		T135	12		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T232	1		T226	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T257	1		T243	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T42	17		T27	7		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T163	1		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	2		T15	5		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	6		T113	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	1		T13	9		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T134	1		T36	6		T133	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T112	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	3		T43	12		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T113	1		T142	5		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T113	1		T137	1		T26	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T136	1		T16	9		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	1		T2	12		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T3	5		T14	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T138	1		T87	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	1		T218	1		T31	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T45	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	6		T224	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1716	1			T1	2		T8	1		T11	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T135	9		T232	1		T250	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T232	9		T226	6		T225	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T257	7		T243	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T42	15		T27	5		T144	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T163	12		T234	6		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	3		T15	2		T153	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T113	10		T86	14		T162	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	9		T131	11		T42	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	2		T133	11		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	8		T131	6		T38	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T43	12		T15	11		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T113	11		T234	13		T225	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T113	6		T32	11		T163	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T16	5		T248	1		T254	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	10		T35	3		T43	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	2		T87	7		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	11		T87	4		T160	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T218	14		T40	1		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	4		T133	9		T26	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	3		T224	3		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1029	1			T1	1		T8	12		T11	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	4		T42	16		T15	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T113	11		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T85	2		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1346	1			T3	1		T8	13		T11	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	10		T45	1		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T134	1		T36	5		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	9		T112	1		T113	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T43	13		T15	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T136	1		T142	1		T234	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	1		T113	7		T43	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	3		T131	1		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	11		T35	5		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	1		T45	1		T87	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T132	1		T138	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T218	15		T31	1		T163	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T45	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	7		T224	4		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T1	2		T132	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T112	1		T135	10		T19	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T150	1		T183	13		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18591	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T163	13		T234	7		T175	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T42	16		T15	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T238	7		T200	2		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T245	4		T246	10		T260	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1308	1			T3	5		T41	13		T86	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	8		T42	8		T86	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T36	3		T133	13		T31	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T38	6		T29	14		T162	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	2		T43	11		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T142	4		T234	5		T254	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T43	10		T26	9		T32	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T16	6		T221	11		T261	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	11		T26	13		T17	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	4		T87	12		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T87	8		T160	5		T228	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	6		T236	10		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T133	10		T166	13		T89	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	2		T160	7		T145	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T166	5		T86	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T135	11		T250	10		T262	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T183	11		T244	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T236	6		T189	9		T184	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T234	6		T175	8		T151	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T112	1		T135	10		T232	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T232	10		T226	7		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T257	8		T243	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T42	16		T27	6		T144	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T163	13		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	4		T15	4		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T113	11		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T13	10		T45	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	1		T36	5		T133	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	9		T112	1		T131	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T43	13		T15	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T113	12		T142	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T113	7		T137	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	1		T16	8		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T2	11		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T14	3		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T138	12		T87	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T45	1		T218	15		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	1		T45	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	7		T224	4		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1418	1			T1	2		T8	13		T11	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T135	11		T255	15		T250	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T225	14		T259	13		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T42	16		T27	6		T234	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T234	6		T238	7		T175	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	1		T15	3		T246	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	5		T86	13		T162	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	8		T42	8		T86	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	3		T133	13		T31	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T38	6		T29	14		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	2		T43	11		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T142	4		T234	5		T225	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T26	9		T32	13		T250	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T16	6		T254	6		T261	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	11		T43	10		T26	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	4		T87	12		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T87	8		T160	5		T228	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T31	6		T236	18		T145	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T133	10		T166	13		T26	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T37	2		T160	7		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T1	1		T41	13		T166	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9