Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23928

1

T1

42

T3

5

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3650

1

T1

3

T2

22

T3

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21577

1

T1

45

T3

6

T4

174

auto[1]

6001

1

T2

22

T3

5

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	81	1			T246	29		T196	10		T167	11
values[0]	46	1			T263	11		T110	9		T264	21
values[1]	753	1			T181	1		T43	21		T136	1
values[2]	2823	1			T2	22		T8	13		T11	13
values[3]	557	1			T7	1		T45	1		T36	8
values[4]	692	1			T3	5		T38	15		T40	4
values[5]	637	1			T13	18		T14	3		T112	1
values[6]	745	1			T112	1		T113	12		T136	1
values[7]	813	1			T3	6		T12	1		T113	7
values[8]	639	1			T1	4		T13	5		T113	11
values[9]	1280	1			T7	2		T9	9		T12	3
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	939	1			T181	1		T43	21		T136	1
values[1]	2878	1			T2	22		T8	13		T11	13
values[2]	519	1			T7	1		T131	7		T218	15
values[3]	767	1			T3	5		T13	18		T14	3
values[4]	471	1			T112	1		T134	1		T131	12
values[5]	793	1			T3	6		T12	1		T112	1
values[6]	910	1			T13	5		T35	5		T42	32
values[7]	658	1			T1	1		T7	1		T12	3
values[8]	918	1			T1	3		T7	1		T9	9
values[9]	202	1			T134	1		T86	14		T26	28
minimum	18523	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T43	11		T136	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T181	1		T133	25		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1644	1			T8	1		T11	2		T90	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	12		T36	6		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	9		T32	14		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	1		T131	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	5		T13	9		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	1		T45	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T134	1		T132	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T112	1		T131	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T113	1		T26	4		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	6		T12	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	2		T35	2		T42	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T27	7		T29	12		T31	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	1		T113	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T12	3		T27	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	1		T42	9		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T1	2		T7	1		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T134	1		T86	3		T26	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T20	2		T246	14		T189	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18368	1			T1	39		T4	174		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T43	10		T85	1		T135	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T133	20		T234	13		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T8	12		T11	11		T247	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	10		T36	2		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	1		T32	11		T130	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T131	6		T218	14		T16	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	9		T37	3		T233	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	2		T151	8		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T225	12		T197	10		T265	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T131	11		T38	5		T87	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T113	11		T26	3		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T113	6		T15	11		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	3		T35	3		T42	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	5		T149	10		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T113	10		T38	4		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T27	2		T228	1		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	8		T42	9		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	1		T135	17		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T86	11		T26	14		T162	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T246	15		T189	7		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T37	2		T38	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T227	13		T267	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T246	14		T196	1		T167	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T264	11		T268	1		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T263	11		T110	7		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T43	11		T136	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T181	1		T133	25		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T8	1		T11	2		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	12		T238	8		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T39	9		T87	9		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	1		T45	1		T36	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	5		T147	1		T233	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T38	10		T40	3		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	9		T134	1		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	1		T112	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T113	1		T26	4		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T112	1		T136	1		T166	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T35	2		T138	1		T166	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	6		T12	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T13	2		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	2		T29	12		T31	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T9	1		T134	1		T42	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T7	2		T12	3		T135	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T227	14		T267	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T246	15		T196	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T264	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T110	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	10		T224	3		T85	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	20		T234	13		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T8	12		T11	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T2	10		T238	8		T270	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	1		T87	4		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	2		T131	6		T218	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T233	6		T248	8		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	5		T40	1		T232	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	9		T37	3		T271	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	2		T131	11		T87	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T113	11		T26	3		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T162	13		T40	1		T19	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T35	3		T138	11		T15	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T113	6		T15	11		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	3		T113	10		T42	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T1	1		T228	1		T175	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	8		T42	9		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T135	17		T162	12		T142	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T43	11		T136	1		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T181	1		T133	22		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T8	13		T11	13		T90	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	11		T36	5		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T39	7		T32	12		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	1		T131	7		T218	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T13	10		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T14	3		T45	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T134	1		T132	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T112	1		T131	12		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T113	12		T26	4		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T12	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	4		T35	5		T42	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	6		T29	1		T31	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T113	11		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	1		T12	1		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	9		T42	10		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T1	2		T7	1		T135	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T134	1		T86	12		T26	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T20	1		T246	16		T189	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18523	1			T1	41		T4	174		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T43	10		T26	9		T29	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T133	23		T234	9		T238	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T41	13		T43	11		T87	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T2	11		T36	3		T86	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	3		T32	13		T130	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T16	6		T146	15		T235	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	4		T13	8		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T144	2		T148	6		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T225	14		T152	9		T255	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T38	6		T87	12		T175	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T26	3		T28	3		T31	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	5		T166	13		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	1		T42	16		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T27	6		T29	11		T31	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T89	12		T234	5		T272	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	2		T27	10		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	8		T87	5		T145	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	1		T135	13		T162	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T86	2		T26	13		T162	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T20	1		T246	13		T189	24

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T227	15		T267	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T246	16		T196	10		T167	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T264	11		T268	1		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T263	1		T110	3		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	11		T136	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T181	1		T133	22		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T8	13		T11	13		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T2	11		T238	9		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	7		T87	5		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	1		T45	1		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T147	1		T233	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	9		T40	4		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	10		T134	1		T37	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	3		T112	1		T131	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T113	12		T26	4		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T112	1		T136	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	5		T138	12		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T12	1		T113	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T13	4		T113	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	2		T29	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	9		T134	1		T42	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T7	2		T12	1		T135	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T227	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T246	13		T167	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T264	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T263	10		T110	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	10		T26	9		T29	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T133	23		T234	9		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T41	13		T43	11		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T2	11		T238	7		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	3		T87	8		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T36	3		T86	4		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	4		T233	5		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T38	6		T144	2		T146	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T13	8		T37	2		T255	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T87	12		T175	8		T148	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	3		T28	3		T160	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T166	13		T162	21		T20	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T166	5		T15	3		T31	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	5		T15	1		T27	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	1		T42	16		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T29	11		T31	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T42	8		T86	2		T87	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T12	2		T135	13		T162	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9