Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24069

1

T1

42

T3

6

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3509

1

T1

3

T2

22

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21421

1

T1

44

T2

22

T3

11

auto[1]

6157

1

T1

1

T4

1

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	754	1			T4	1		T45	2		T36	1
values[0]	2	1			T216	1		T168	1		-	-
values[1]	642	1			T7	1		T113	11		T45	1
values[2]	2966	1			T8	13		T9	9		T11	13
values[3]	763	1			T1	1		T14	3		T134	1
values[4]	711	1			T12	1		T181	1		T43	24
values[5]	593	1			T1	3		T35	5		T131	12
values[6]	681	1			T3	5		T7	1		T13	18
values[7]	664	1			T3	6		T36	8		T42	18
values[8]	638	1			T112	1		T45	1		T43	21
values[9]	1134	1			T2	22		T7	1		T112	1
minimum	18030	1			T1	41		T4	173		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	731	1			T113	11		T45	1		T131	1
values[1]	2890	1			T8	13		T9	9		T11	13
values[2]	805	1			T1	1		T14	3		T134	1
values[3]	689	1			T12	1		T35	5		T181	1
values[4]	672	1			T1	3		T131	12		T138	3
values[5]	643	1			T3	5		T7	1		T13	18
values[6]	640	1			T3	6		T36	8		T42	18
values[7]	620	1			T2	22		T112	1		T45	1
values[8]	1136	1			T7	1		T112	1		T113	7
values[9]	133	1			T31	7		T217	1		T151	17
minimum	18619	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T113	1		T131	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T45	1		T38	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T8	1		T11	2		T12	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T9	1		T13	2		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T134	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	1		T131	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T181	1		T43	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	2		T17	9		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T131	1		T29	15		T144	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T138	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T13	9		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	5		T113	1		T26	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	6		T42	9		T86	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T36	6		T133	14		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T112	1		T45	1		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T2	12		T130	4		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	1		T134	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T112	1		T113	1		T37	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T31	7		T151	9		T223	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T217	1		T273	17		T229	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18392	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T7	1		T132	1		T87	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T113	10		T160	5		T226	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	4		T40	1		T175	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T8	12		T11	11		T247	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	8		T13	3		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T218	14		T224	3		T16	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T14	2		T131	6		T26	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T43	12		T38	5		T27	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	3		T17	6		T274	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T131	11		T234	6		T259	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T138	2		T144	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	9		T133	9		T28	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T113	11		T26	14		T163	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T42	9		T86	14		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T36	2		T133	11		T85	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	10		T27	2		T163	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	10		T130	1		T257	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T228	12		T238	19		T254	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T113	6		T37	3		T42	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T151	8		T223	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T229	8		T275	1		T276	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T87	4		T277	6		T184	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	576	1			T4	1		T45	2		T36	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T147	1		T229	1		T278	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T168	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T113	1		T258	1		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T45	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1661	1			T8	1		T11	2		T12	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T13	2		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T134	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T131	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T181	1		T43	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T219	1		T143	1		T236	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T131	1		T29	15		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	2		T35	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T13	9		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	5		T113	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	6		T42	9		T86	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T36	6		T133	14		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T112	1		T45	1		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T86	3		T163	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	1		T134	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T2	12		T112	1		T113	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17884	1			T1	39		T4	173		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T151	8		T223	2		T254	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T229	8		T278	16		T57	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T113	10		T200	2		T254	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	4		T87	4		T175	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T8	12		T11	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	8		T13	3		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T218	14		T224	3		T16	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	2		T131	6		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T43	12		T38	5		T27	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T232	9		T274	13		T175	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T131	11		T234	6		T259	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	1		T35	3		T138	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	9		T133	9		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T113	11		T163	10		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T42	9		T86	14		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	2		T133	11		T85	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T43	10		T27	2		T163	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T86	11		T163	12		T257	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T228	12		T238	19		T249	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T2	10		T113	6		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T113	11		T131	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T45	1		T38	5		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T8	13		T11	13		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	9		T13	4		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T134	1		T218	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T14	3		T131	7		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T181	1		T43	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	5		T17	11		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T131	12		T29	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T138	3		T144	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T13	10		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T113	12		T26	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T42	10		T86	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	5		T133	12		T85	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T112	1		T45	1		T43	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	11		T130	4		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	1		T134	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T112	1		T113	7		T37	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T31	1		T151	9		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T217	1		T273	1		T229	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18532	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T7	1		T132	1		T87	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T160	5		T254	6		T259	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T175	12		T195	11		T225	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T12	2		T41	13		T239	33
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T13	1		T166	5		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	6		T29	11		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T26	12		T32	13		T135	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	11		T38	6		T27	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	4		T236	6		T146	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	14		T144	2		T234	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T160	7		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	8		T133	10		T89	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	4		T26	13		T261	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	5		T42	8		T86	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T36	3		T133	13		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	10		T166	13		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T2	11		T130	1		T275	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T228	16		T238	19		T254	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T37	2		T42	16		T31	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T31	6		T151	8		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T273	16		T276	12		T279	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T235	4		T200	2		T280	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T87	8		T277	6		T184	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	546	1			T4	1		T45	2		T36	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T147	1		T229	9		T278	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T168	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T113	11		T258	1		T252	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	1		T45	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T8	13		T11	13		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	9		T13	4		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T134	1		T218	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	3		T131	7		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T181	1		T43	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T219	1		T143	1		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	12		T29	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	2		T35	5		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	1		T13	10		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T113	12		T163	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T42	10		T86	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T36	5		T133	12		T85	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T112	1		T45	1		T43	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T86	12		T163	13		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	1		T134	1		T45	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T2	11		T112	1		T113	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18030	1			T1	41		T4	173		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T31	6		T151	8		T223	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T278	22		T57	1		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T235	4		T200	2		T254	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T87	8		T175	12		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T12	2		T41	13		T239	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	1		T166	5		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	6		T29	11		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	3		T26	12		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	11		T38	6		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T236	6		T175	8		T233	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	14		T144	2		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	1		T17	4		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	8		T133	10		T89	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T3	4		T160	7		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	5		T42	8		T86	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	3		T133	13		T86	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T43	10		T166	13		T27	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T86	2		T145	6		T275	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T228	16		T238	19		T249	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T2	11		T37	2		T42	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9