Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24223

1

T1

41

T3

11

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3355

1

T1

4

T2

22

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21731

1

T1

44

T4

174

T5

20

auto[1]

5847

1

T1

1

T2

22

T3

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	194	1			T112	1		T132	1		T87	13
values[0]	14	1			T188	1		T281	12		T282	1
values[1]	697	1			T1	4		T7	1		T134	1
values[2]	811	1			T3	5		T7	1		T112	1
values[3]	595	1			T13	18		T136	1		T218	15
values[4]	801	1			T113	12		T45	2		T37	9
values[5]	807	1			T2	22		T3	6		T13	5
values[6]	676	1			T131	12		T224	4		T133	20
values[7]	553	1			T12	1		T14	3		T131	7
values[8]	714	1			T9	9		T113	11		T137	1
values[9]	3204	1			T7	1		T8	13		T11	13
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	630	1			T1	4		T7	1		T134	1
values[1]	815	1			T3	5		T112	1		T35	5
values[2]	629	1			T13	18		T113	12		T37	9
values[3]	854	1			T13	5		T45	2		T42	18
values[4]	752	1			T2	22		T3	6		T134	1
values[5]	618	1			T14	3		T131	12		T224	4
values[6]	2932	1			T8	13		T11	13		T12	1
values[7]	647	1			T9	9		T137	1		T86	42
values[8]	893	1			T7	1		T12	3		T112	1
values[9]	84	1			T38	15		T26	7		T31	7
minimum	18724	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T42	17		T16	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	3		T134	1		T85	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	5		T35	2		T43	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T112	1		T36	6		T26	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	9		T86	5		T135	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T113	1		T37	6		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T13	2		T45	1		T43	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	1		T42	9		T166	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	6		T27	7		T162	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	12		T134	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	1		T131	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	11		T27	11		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T8	1		T11	2		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T131	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	1		T86	3		T29	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	1		T86	14		T32	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T12	3		T112	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T131	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T38	10		T31	7		T142	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T26	4		T221	12		T283	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18388	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T145	7		T284	1		T19	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T42	15		T16	5		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	1		T85	1		T144	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T35	3		T43	12		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	2		T278	7		T285	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	9		T135	9		T130	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T113	11		T37	3		T160	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	3		T43	10		T15	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	9		T135	17		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T27	5		T162	13		T175	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	10		T142	12		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	2		T131	11		T224	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T133	9		T27	2		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T8	12		T11	11		T113	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T131	6		T133	11		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T86	11		T253	1		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	8		T86	14		T32	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T113	6		T87	4		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T138	2		T39	1		T149	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T38	5		T110	10		T286	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T26	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	2		T37	2		T38	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T19	7		T195	12		T281	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T112	1		T87	9		T29	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T132	1		T188	1		T221	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T188	1		T281	6		T282	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	1		T42	17		T16	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	3		T134	1		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	5		T7	1		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T112	1		T36	6		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	9		T218	1		T89	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T136	1		T26	10		T160	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T45	1		T43	11		T86	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T113	1		T45	1		T37	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	6		T13	2		T27	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	12		T134	1		T42	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T131	1		T224	1		T87	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T133	11		T27	11		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	1		T38	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T131	1		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T113	1		T137	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T86	14		T162	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T8	1		T11	2		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	1		T131	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T87	4		T287	5		T189	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T279	1		T288	5		T289	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T281	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T42	15		T16	5		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T85	1		T19	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	3		T43	12		T15	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T36	2		T144	2		T246	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	9		T218	14		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T160	2		T20	13		T248	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	10		T15	2		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T113	11		T37	3		T135	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	3		T27	5		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	10		T42	9		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T131	11		T224	3		T87	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T133	9		T27	2		T28	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	2		T38	4		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T131	6		T133	11		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T113	10		T138	11		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	8		T86	14		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T8	12		T11	11		T113	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T138	2		T39	1		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T42	16		T16	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	3		T134	1		T85	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	1		T35	5		T43	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T112	1		T36	5		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	10		T86	1		T135	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T113	12		T37	7		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T13	4		T45	1		T43	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	1		T42	10		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	1		T27	6		T162	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	11		T134	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	3		T131	12		T224	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T133	10		T27	3		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T8	13		T11	13		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	1		T131	7		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	1		T86	12		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	9		T86	15		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T12	1		T112	1		T113	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	1		T131	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T38	9		T31	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T26	4		T221	1		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18554	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T145	1		T284	1		T19	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T42	16		T16	6		T31	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T144	13		T236	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	4		T43	11		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	3		T26	9		T240	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	8		T86	4		T135	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	2		T160	7		T146	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	1		T43	10		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T42	8		T166	13		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	5		T27	6		T162	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	11		T142	13		T249	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T87	5		T228	16		T238	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T133	10		T27	10		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T41	13		T87	12		T26	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T133	13		T238	12		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T86	2		T29	14		T148	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T86	13		T32	13		T162	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	2		T87	8		T29	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	3		T182	10		T240	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T38	6		T31	6		T142	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T26	3		T221	11		T283	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T162	4		T234	6		T245	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T145	6		T195	11		T281	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T112	1		T87	5		T29	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T132	1		T188	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T188	1		T281	7		T282	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	1		T42	16		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	3		T134	1		T85	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T7	1		T35	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T112	1		T36	5		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	10		T218	15		T89	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T136	1		T26	1		T160	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T45	1		T43	11		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T113	12		T45	1		T37	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T13	4		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	11		T134	1		T42	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T131	12		T224	4		T87	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T133	10		T27	3		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	3		T38	5		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T131	7		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T113	11		T137	1		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	9		T86	15		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T8	13		T11	13		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	1		T131	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T87	8		T29	11		T142	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T221	11		T187	6		T288	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T281	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T42	16		T16	6		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T144	2		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	4		T43	11		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	3		T144	11		T246	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	8		T89	12		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	9		T160	7		T146	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	10		T86	4		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T37	2		T166	13		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	5		T13	1		T27	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	11		T42	8		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T87	5		T236	8		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T133	10		T27	10		T28	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T26	13		T238	7		T272	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T133	13		T238	12		T175	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T86	2		T87	12		T148	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T86	13		T162	8		T233	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T12	2		T41	13		T38	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	3		T26	3		T32	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9