Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23865

1

T1

42

T3

5

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3713

1

T1

3

T2

22

T3

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21531

1

T1

45

T3

6

T4

174

auto[1]

6047

1

T2

22

T3

5

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	291	1			T7	1		T134	1		T138	3
values[0]	20	1			T263	11		T110	9		-	-
values[1]	800	1			T181	1		T43	21		T136	1
values[2]	2856	1			T2	22		T8	13		T11	13
values[3]	532	1			T7	1		T131	7		T218	15
values[4]	629	1			T3	5		T45	1		T37	9
values[5]	664	1			T13	18		T14	3		T112	1
values[6]	700	1			T112	1		T136	1		T166	14
values[7]	907	1			T3	6		T12	1		T113	19
values[8]	572	1			T1	3		T13	5		T113	11
values[9]	1095	1			T1	1		T7	1		T9	9
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	736	1			T137	1		T224	4		T133	45
values[1]	2924	1			T2	22		T8	13		T11	13
values[2]	497	1			T7	1		T131	7		T218	15
values[3]	673	1			T3	5		T13	18		T14	3
values[4]	618	1			T112	1		T134	1		T131	12
values[5]	784	1			T3	6		T12	1		T112	1
values[6]	847	1			T13	5		T42	32		T137	1
values[7]	620	1			T1	4		T7	1		T12	3
values[8]	1007	1			T7	1		T9	9		T42	18
values[9]	162	1			T134	1		T86	14		T162	9
minimum	18710	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	1		T224	1		T26	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T133	25		T219	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T8	1		T11	2		T90	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	12		T36	6		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	9		T130	4		T145	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	1		T131	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	5		T13	9		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T45	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T134	1		T132	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T112	1		T131	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T113	1		T35	2		T26	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T3	6		T12	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	2		T42	17		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T27	7		T31	10		T142	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	1		T113	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	2		T7	1		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T9	1		T42	9		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T7	1		T135	14		T162	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T134	1		T86	3		T162	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T254	7		T246	14		T189	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18403	1			T1	39		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T181	1		T238	13		T222	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T224	3		T163	10		T160	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T133	20		T234	13		T169	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T8	12		T11	11		T247	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	10		T36	2		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	1		T130	1		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T131	6		T218	14		T16	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	9		T37	3		T233	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	2		T151	8		T259	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T253	1		T225	12		T197	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T131	11		T38	5		T87	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T113	11		T35	3		T26	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T113	6		T15	11		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	3		T42	15		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T27	5		T149	10		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T113	10		T38	4		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T27	2		T228	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	8		T42	9		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T135	17		T162	12		T142	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T86	11		T162	4		T212	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T254	13		T246	15		T189	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	2		T37	2		T43	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T238	11		T222	3		T290	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T134	1		T138	1		T284	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T7	1		T135	14		T145	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T263	11		T110	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T43	11		T136	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T181	1		T133	25		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T8	1		T11	2		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	12		T36	6		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T39	9		T130	4		T236	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T7	1		T131	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	5		T37	6		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	1		T132	1		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	9		T134	1		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	1		T112	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T26	4		T28	5		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T112	1		T136	1		T166	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T113	1		T35	2		T42	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	6		T12	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	2		T113	1		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	2		T29	12		T31	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T9	1		T42	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T7	1		T12	3		T162	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T138	2		T151	8		T212	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T135	17		T225	11		T221	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T110	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T43	10		T224	3		T85	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T133	20		T234	13		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T8	12		T11	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T2	10		T36	2		T137	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	1		T130	1		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T131	6		T218	14		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	3		T233	6		T248	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	1		T232	1		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	9		T271	2		T265	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	2		T131	11		T38	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T26	3		T28	3		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T162	13		T40	1		T19	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T113	11		T35	3		T42	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T113	6		T15	11		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	3		T113	10		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	1		T228	1		T175	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	8		T42	9		T86	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T162	12		T142	12		T144	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T137	1		T224	4		T26	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T133	22		T219	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T8	13		T11	13		T90	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	11		T36	5		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	7		T130	4		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	1		T131	7		T218	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T13	10		T37	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	3		T45	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T134	1		T132	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T112	1		T131	12		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T113	12		T35	5		T26	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	1		T12	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	4		T42	16		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T27	6		T31	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T113	11		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	2		T7	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	9		T42	10		T138	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T7	1		T135	18		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T134	1		T86	12		T162	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T254	14		T246	16		T189	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18567	1			T1	41		T4	174		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T181	1		T238	12		T222	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	9		T29	14		T160	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	23		T234	9		T254	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T41	13		T43	11		T87	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	11		T36	3		T86	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	3		T130	1		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T16	6		T146	15		T235	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	4		T13	8		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T144	2		T148	6		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T225	14		T152	9		T255	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T38	6		T87	12		T175	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	3		T28	3		T31	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	5		T166	13		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	1		T42	16		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T27	6		T31	9		T142	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T89	12		T234	5		T272	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T12	2		T27	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T42	8		T87	5		T26	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T135	13		T162	8		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T86	2		T162	4		T212	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T254	6		T246	13		T189	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T43	10		T135	11		T179	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T238	12		T263	10		T290	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T134	1		T138	3		T284	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	1		T135	18		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T263	1		T110	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T43	11		T136	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T181	1		T133	22		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T8	13		T11	13		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	11		T36	5		T137	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	7		T130	4		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T131	7		T218	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T37	7		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	1		T132	1		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	10		T134	1		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	3		T112	1		T131	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	4		T28	5		T194	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T112	1		T136	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T113	12		T35	5		T42	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T12	1		T113	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	4		T113	11		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	2		T29	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	1		T9	9		T42	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T7	1		T12	1		T162	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T151	8		T212	12		T291	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T135	13		T145	9		T221	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T263	10		T110	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	10		T26	9		T29	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T133	23		T234	9		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T41	13		T43	11		T87	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	11		T36	3		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	3		T130	1		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T86	4		T16	6		T235	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	4		T37	2		T233	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T144	2		T146	15		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	8		T152	9		T255	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T38	6		T87	12		T175	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	3		T28	3		T160	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T166	13		T162	21		T20	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T42	16		T166	5		T15	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	5		T15	1		T27	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	1		T86	13		T89	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	1		T29	11		T31	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T42	8		T86	2		T87	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T12	2		T162	8		T142	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9