Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27578

1

T1

45

T2

22

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24163

1

T1

41

T3

11

T4

174

auto[ADC_CTRL_FILTER_COND_OUT]

3415

1

T1

4

T2

22

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21834

1

T1

44

T4

174

T5

20

auto[1]

5744

1

T1

1

T2

22

T3

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23616

1

T1

42

T2

12

T3

11

auto[1]

3962

1

T1

3

T2

10

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	86	1			T292	12		T212	27		T110	15
values[0]	34	1			T188	1		T281	12		T293	21
values[1]	760	1			T1	4		T7	1		T42	32
values[2]	715	1			T3	5		T7	1		T112	1
values[3]	629	1			T13	18		T37	9		T136	1
values[4]	739	1			T113	12		T45	2		T43	21
values[5]	829	1			T3	6		T13	5		T134	1
values[6]	703	1			T2	22		T131	12		T133	20
values[7]	563	1			T12	1		T14	3		T131	7
values[8]	680	1			T9	9		T113	11		T137	1
values[9]	3328	1			T7	1		T8	13		T11	13
minimum	18512	1			T1	41		T4	174		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	924	1			T1	4		T7	2		T134	1
values[1]	690	1			T3	5		T112	1		T35	5
values[2]	662	1			T13	18		T37	9		T136	1
values[3]	860	1			T13	5		T113	12		T45	1
values[4]	746	1			T2	22		T3	6		T134	1
values[5]	611	1			T14	3		T131	12		T224	4
values[6]	2928	1			T8	13		T11	13		T12	1
values[7]	661	1			T9	9		T137	1		T138	3
values[8]	783	1			T7	1		T12	3		T112	1
values[9]	192	1			T181	1		T38	15		T87	13
minimum	18521	1			T1	41		T4	174		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

4172

1

T1

1

T2

11

T3

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	2		T42	17		T16	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	3		T134	1		T85	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	5		T35	2		T43	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T112	1		T36	6		T26	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	9		T86	5		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	6		T136	1		T218	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T13	2		T113	1		T43	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	1		T42	9		T166	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	6		T45	1		T27	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	12		T134	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	1		T131	1		T87	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T224	1		T133	11		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T8	1		T11	2		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T131	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	1		T86	3		T29	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	1		T138	1		T86	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	3		T112	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	1		T131	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T181	1		T38	10		T87	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T26	4		T216	1		T283	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18371	1			T1	39		T4	174		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T42	15		T16	5		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T85	1		T19	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	3		T43	12		T15	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T36	2		T144	2		T278	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	9		T130	1		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	3		T218	14		T135	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	3		T113	11		T43	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	9		T135	17		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T27	5		T162	13		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	10		T142	12		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	2		T131	11		T87	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T224	3		T133	9		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T8	12		T11	11		T113	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T131	6		T133	11		T87	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T86	11		T253	1		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	8		T138	2		T86	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T113	6		T149	2		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	1		T149	10		T231	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T38	5		T87	4		T110	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T26	3		T294	15		T288	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	2		T37	2		T38	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T292	12		T212	17		T110	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T289	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T293	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T188	1		T281	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T42	17		T16	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	3		T85	1		T144	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	5		T7	1		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T112	1		T134	1		T36	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	9		T89	13		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	6		T136	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T113	1		T45	1		T43	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	1		T166	14		T135	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	6		T13	2		T27	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T134	1		T42	9		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T131	1		T87	6		T163	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	12		T133	11		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	1		T38	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T131	1		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T113	1		T137	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T86	14		T87	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T8	1		T11	2		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T7	1		T131	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18366	1			T1	39		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T212	10		T110	10		T97	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T289	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T293	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T281	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T42	15		T16	5		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	1		T85	1		T19	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	3		T43	12		T15	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T36	2		T144	2		T246	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	9		T130	1		T248	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T37	3		T218	14		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T113	11		T43	10		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	26		T149	2		T248	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	3		T27	5		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T42	9		T40	1		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T131	11		T87	8		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	10		T133	9		T27	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	2		T38	4		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	6		T224	3		T133	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T113	10		T138	11		T253	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	8		T86	14		T87	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T8	12		T11	11		T113	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T138	2		T39	1		T26	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T37	2		T38	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	2		T42	16		T16	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	3		T134	1		T85	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T35	5		T43	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T112	1		T36	5		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	10		T86	1		T130	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	7		T136	1		T218	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	4		T113	12		T43	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	1		T42	10		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	1		T45	1		T27	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	11		T134	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	3		T131	12		T87	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T224	4		T133	10		T27	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T8	13		T11	13		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T131	7		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	1		T86	12		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	9		T138	3		T86	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T112	1		T113	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	1		T131	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T181	1		T38	9		T87	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T26	4		T216	1		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18517	1			T1	41		T4	174		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T42	16		T16	6		T31	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T144	2		T236	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	4		T43	11		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	3		T26	9		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	8		T86	4		T130	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	2		T135	11		T160	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T43	10		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T42	8		T166	13		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	5		T27	6		T162	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	11		T142	13		T249	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T87	5		T228	16		T238	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	10		T27	10		T28	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T41	13		T239	33		T164	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T133	13		T87	12		T26	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T86	2		T29	14		T233	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T86	13		T32	13		T162	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	2		T31	6		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	3		T151	7		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T38	6		T87	8		T29	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T26	3		T283	9		T295	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T162	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T292	1		T212	11		T110	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T289	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T293	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T188	1		T281	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T42	16		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	3		T85	2		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T7	1		T35	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T112	1		T134	1		T36	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	10		T89	1		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T37	7		T136	1		T218	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T113	12		T45	1		T43	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	1		T166	1		T135	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T13	4		T27	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T134	1		T42	10		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T131	12		T87	9		T163	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	11		T133	10		T27	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	3		T38	5		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	1		T131	7		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T113	11		T137	1		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	9		T86	15		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T8	13		T11	13		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T7	1		T131	1		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18512	1			T1	41		T4	174		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T292	11		T212	16		T110	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T289	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T293	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T281	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T42	16		T16	6		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T144	2		T236	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	4		T43	11		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	3		T144	11		T246	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	8		T89	12		T130	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T37	2		T26	9		T160	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	10		T86	4		T15	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T166	13		T135	24		T225	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	5		T13	1		T27	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T42	8		T142	13		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T87	5		T236	8		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	11		T133	10		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T238	7		T272	2		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T133	13		T26	13		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T233	5		T148	6		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T86	13		T87	12		T162	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T12	2		T41	13		T38	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	3		T26	3		T32	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23406

1

T1

44

T2

11

T3

2

auto[1]

auto[0]

4172

1

T1

1

T2

11

T3

9