Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
754 |
1 |
|
|
T1 |
7 |
|
T36 |
7 |
|
T37 |
4 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
415 |
1 |
|
|
T1 |
4 |
|
T36 |
5 |
|
T37 |
3 |
auto[1] |
339 |
1 |
|
|
T1 |
3 |
|
T36 |
2 |
|
T37 |
1 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
462 |
1 |
|
|
T1 |
4 |
|
T36 |
6 |
|
T37 |
2 |
auto[1] |
292 |
1 |
|
|
T1 |
3 |
|
T36 |
1 |
|
T37 |
2 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
462 |
1 |
|
|
T1 |
4 |
|
T36 |
6 |
|
T37 |
2 |
auto[1] |
292 |
1 |
|
|
T1 |
3 |
|
T36 |
1 |
|
T37 |
2 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
2 |
4 |
66.67 |
2 |
Automatically Generated Cross Bins |
6 |
2 |
4 |
66.67 |
2 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER | STATUS |
* |
[auto[0]] |
* |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
242 |
1 |
|
|
T1 |
2 |
|
T36 |
4 |
|
T37 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
220 |
1 |
|
|
T1 |
2 |
|
T36 |
2 |
|
T37 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
173 |
1 |
|
|
T1 |
2 |
|
T36 |
1 |
|
T37 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
119 |
1 |
|
|
T1 |
1 |
|
T38 |
3 |
|
T39 |
4 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |