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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.61


Total test records in report: 919
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T794 /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3295555616 Jul 05 06:01:06 PM PDT 24 Jul 05 06:01:18 PM PDT 24 32180664002 ps
T795 /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1182664694 Jul 05 06:01:31 PM PDT 24 Jul 05 06:02:59 PM PDT 24 38446786375 ps
T796 /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.182781555 Jul 05 06:00:57 PM PDT 24 Jul 05 06:18:56 PM PDT 24 494119190065 ps
T797 /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3031201208 Jul 05 06:00:11 PM PDT 24 Jul 05 06:01:35 PM PDT 24 40049229093 ps
T127 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.802007561 Jul 05 05:16:43 PM PDT 24 Jul 05 05:16:45 PM PDT 24 329135341 ps
T59 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1817472795 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:57 PM PDT 24 493154121 ps
T64 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1504346548 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:48 PM PDT 24 745069141 ps
T798 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3847203947 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 417844681 ps
T799 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4126919050 Jul 05 05:16:55 PM PDT 24 Jul 05 05:16:59 PM PDT 24 460028614 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2491354580 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:41 PM PDT 24 780805265 ps
T53 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3139893557 Jul 05 05:16:41 PM PDT 24 Jul 05 05:16:44 PM PDT 24 398209218 ps
T54 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2269510158 Jul 05 05:16:47 PM PDT 24 Jul 05 05:16:52 PM PDT 24 8708688629 ps
T128 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3591202505 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:59 PM PDT 24 1765900311 ps
T50 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2809591068 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:53 PM PDT 24 4022442619 ps
T115 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1941037648 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:56 PM PDT 24 529748935 ps
T55 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2807970577 Jul 05 05:16:43 PM PDT 24 Jul 05 05:16:55 PM PDT 24 4136355186 ps
T51 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.43568512 Jul 05 05:16:52 PM PDT 24 Jul 05 05:17:11 PM PDT 24 4915993028 ps
T800 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3074142758 Jul 05 05:16:36 PM PDT 24 Jul 05 05:16:38 PM PDT 24 547331959 ps
T67 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.129793028 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:34 PM PDT 24 376906511 ps
T801 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1440018788 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:55 PM PDT 24 430556678 ps
T116 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.584519986 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:34 PM PDT 24 498288566 ps
T802 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3393065121 Jul 05 05:17:07 PM PDT 24 Jul 05 05:17:09 PM PDT 24 391600856 ps
T72 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3893766820 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:40 PM PDT 24 594538504 ps
T803 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.840589345 Jul 05 05:17:01 PM PDT 24 Jul 05 05:17:05 PM PDT 24 448757720 ps
T56 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3664347953 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:54 PM PDT 24 4584320733 ps
T117 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.122190699 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:57 PM PDT 24 388103333 ps
T804 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2837680479 Jul 05 05:16:46 PM PDT 24 Jul 05 05:16:48 PM PDT 24 426392241 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.578459555 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:34 PM PDT 24 441436916 ps
T78 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2477418969 Jul 05 05:16:54 PM PDT 24 Jul 05 05:17:17 PM PDT 24 8408802828 ps
T65 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1045729452 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 711364085 ps
T66 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1314840907 Jul 05 05:16:42 PM PDT 24 Jul 05 05:16:44 PM PDT 24 409056951 ps
T805 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3935178467 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:45 PM PDT 24 491238925 ps
T92 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3753144298 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 645358240 ps
T60 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1492278482 Jul 05 05:16:47 PM PDT 24 Jul 05 05:16:51 PM PDT 24 4673895400 ps
T119 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4184555718 Jul 05 05:16:50 PM PDT 24 Jul 05 05:16:52 PM PDT 24 540074212 ps
T806 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1726041865 Jul 05 05:16:30 PM PDT 24 Jul 05 05:16:33 PM PDT 24 686244242 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1777655300 Jul 05 05:16:33 PM PDT 24 Jul 05 05:16:36 PM PDT 24 992960806 ps
T807 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1722326182 Jul 05 05:17:01 PM PDT 24 Jul 05 05:17:05 PM PDT 24 517812422 ps
T71 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3718575177 Jul 05 05:16:43 PM PDT 24 Jul 05 05:16:46 PM PDT 24 541341180 ps
T121 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.819167246 Jul 05 05:16:47 PM PDT 24 Jul 05 05:16:50 PM PDT 24 377591629 ps
T808 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3972730040 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:39 PM PDT 24 439349307 ps
T52 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1500443541 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:36 PM PDT 24 5169705013 ps
T79 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2610885546 Jul 05 05:16:40 PM PDT 24 Jul 05 05:16:46 PM PDT 24 4463762476 ps
T809 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1129737308 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:48 PM PDT 24 521652251 ps
T810 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2234243119 Jul 05 05:17:01 PM PDT 24 Jul 05 05:17:05 PM PDT 24 459842642 ps
T811 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.312467431 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:39 PM PDT 24 446396137 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.761738744 Jul 05 05:16:48 PM PDT 24 Jul 05 05:17:01 PM PDT 24 4182526903 ps
T813 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2756466062 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:47 PM PDT 24 538494424 ps
T814 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.353958558 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 496285172 ps
T73 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.828272792 Jul 05 05:16:42 PM PDT 24 Jul 05 05:17:01 PM PDT 24 7470524286 ps
T815 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4062263465 Jul 05 05:16:58 PM PDT 24 Jul 05 05:17:02 PM PDT 24 503065918 ps
T816 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2788609357 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:57 PM PDT 24 389951737 ps
T817 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1787029616 Jul 05 05:16:46 PM PDT 24 Jul 05 05:16:48 PM PDT 24 693555272 ps
T818 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1313381630 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:41 PM PDT 24 514033485 ps
T74 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1079014597 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:52 PM PDT 24 553058680 ps
T819 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1352105174 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:47 PM PDT 24 373306869 ps
T820 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3129701024 Jul 05 05:16:51 PM PDT 24 Jul 05 05:16:54 PM PDT 24 464823989 ps
T821 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.858295743 Jul 05 05:16:57 PM PDT 24 Jul 05 05:17:01 PM PDT 24 344809699 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3905443837 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:41 PM PDT 24 574375795 ps
T123 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1265824299 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:46 PM PDT 24 524168303 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.682877887 Jul 05 05:16:53 PM PDT 24 Jul 05 05:16:56 PM PDT 24 510564684 ps
T823 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.477303546 Jul 05 05:16:41 PM PDT 24 Jul 05 05:16:42 PM PDT 24 658548556 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.349644992 Jul 05 05:16:40 PM PDT 24 Jul 05 05:16:42 PM PDT 24 362552198 ps
T825 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3711648128 Jul 05 05:17:02 PM PDT 24 Jul 05 05:17:06 PM PDT 24 441130354 ps
T826 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2315014371 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:52 PM PDT 24 2073230411 ps
T338 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.81023248 Jul 05 05:16:55 PM PDT 24 Jul 05 05:17:00 PM PDT 24 4547448911 ps
T827 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4209687690 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:42 PM PDT 24 449700354 ps
T828 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4178701179 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:57 PM PDT 24 8970356514 ps
T829 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2939759124 Jul 05 05:16:55 PM PDT 24 Jul 05 05:17:04 PM PDT 24 4515367756 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3171544593 Jul 05 05:16:31 PM PDT 24 Jul 05 05:19:58 PM PDT 24 52953729495 ps
T124 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2030675328 Jul 05 05:16:34 PM PDT 24 Jul 05 05:17:03 PM PDT 24 43195088546 ps
T831 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2023015809 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:48 PM PDT 24 585404960 ps
T832 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2270095230 Jul 05 05:16:43 PM PDT 24 Jul 05 05:16:45 PM PDT 24 319850135 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4176262434 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:54 PM PDT 24 350435037 ps
T834 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2037200228 Jul 05 05:16:56 PM PDT 24 Jul 05 05:17:00 PM PDT 24 393966729 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3189305924 Jul 05 05:16:41 PM PDT 24 Jul 05 05:16:46 PM PDT 24 2156968198 ps
T836 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.18431716 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:40 PM PDT 24 493233807 ps
T75 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1309584869 Jul 05 05:16:49 PM PDT 24 Jul 05 05:16:53 PM PDT 24 745645265 ps
T837 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3830230039 Jul 05 05:17:00 PM PDT 24 Jul 05 05:17:03 PM PDT 24 369263915 ps
T80 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2944808631 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:45 PM PDT 24 8405137729 ps
T838 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2654605159 Jul 05 05:17:01 PM PDT 24 Jul 05 05:17:05 PM PDT 24 509267614 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3320147255 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:52 PM PDT 24 2306125915 ps
T840 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.774882944 Jul 05 05:16:51 PM PDT 24 Jul 05 05:17:10 PM PDT 24 4601346829 ps
T841 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2486508547 Jul 05 05:17:00 PM PDT 24 Jul 05 05:17:04 PM PDT 24 503908042 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3496720050 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 490671013 ps
T843 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3450644651 Jul 05 05:16:47 PM PDT 24 Jul 05 05:16:50 PM PDT 24 323685217 ps
T844 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1367068845 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:54 PM PDT 24 545539669 ps
T845 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.571642862 Jul 05 05:17:19 PM PDT 24 Jul 05 05:17:21 PM PDT 24 401707381 ps
T846 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3120635691 Jul 05 05:16:56 PM PDT 24 Jul 05 05:17:00 PM PDT 24 403847448 ps
T847 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1776005631 Jul 05 05:16:47 PM PDT 24 Jul 05 05:16:49 PM PDT 24 396811538 ps
T76 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.478688319 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:50 PM PDT 24 1200231530 ps
T848 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.101906096 Jul 05 05:16:49 PM PDT 24 Jul 05 05:16:56 PM PDT 24 2089423428 ps
T849 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3273201318 Jul 05 05:16:59 PM PDT 24 Jul 05 05:17:03 PM PDT 24 479962761 ps
T850 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2961947007 Jul 05 05:16:33 PM PDT 24 Jul 05 05:16:35 PM PDT 24 513193365 ps
T851 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.515526973 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:49 PM PDT 24 4171396006 ps
T852 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3901385851 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:34 PM PDT 24 444823273 ps
T853 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.322940344 Jul 05 05:16:57 PM PDT 24 Jul 05 05:17:00 PM PDT 24 344459844 ps
T854 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.787449607 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 305722438 ps
T855 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.526061574 Jul 05 05:16:58 PM PDT 24 Jul 05 05:17:03 PM PDT 24 383112691 ps
T856 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4008619701 Jul 05 05:16:59 PM PDT 24 Jul 05 05:17:02 PM PDT 24 430839614 ps
T77 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1956836979 Jul 05 05:16:49 PM PDT 24 Jul 05 05:16:52 PM PDT 24 585118825 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2023678397 Jul 05 05:16:53 PM PDT 24 Jul 05 05:17:01 PM PDT 24 2288839879 ps
T858 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1686198820 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:40 PM PDT 24 8982041595 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2607872385 Jul 05 05:16:40 PM PDT 24 Jul 05 05:17:46 PM PDT 24 26588648234 ps
T860 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.546275865 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:39 PM PDT 24 712470337 ps
T81 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.598262216 Jul 05 05:16:31 PM PDT 24 Jul 05 05:16:40 PM PDT 24 4774416194 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.499663645 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:34 PM PDT 24 579692732 ps
T862 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.797074930 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:41 PM PDT 24 2303706161 ps
T125 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2521143423 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:47 PM PDT 24 472749861 ps
T126 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1923657334 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:41 PM PDT 24 340765540 ps
T863 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2750092317 Jul 05 05:16:49 PM PDT 24 Jul 05 05:16:54 PM PDT 24 4624295482 ps
T864 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2934267903 Jul 05 05:16:51 PM PDT 24 Jul 05 05:16:52 PM PDT 24 452035491 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3069039952 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:36 PM PDT 24 1069021657 ps
T866 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4161846746 Jul 05 05:16:44 PM PDT 24 Jul 05 05:16:46 PM PDT 24 545371715 ps
T867 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2849448362 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:41 PM PDT 24 3126386759 ps
T868 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1084908634 Jul 05 05:17:00 PM PDT 24 Jul 05 05:17:04 PM PDT 24 430503546 ps
T869 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1146887797 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:38 PM PDT 24 4183777000 ps
T870 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2461659889 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:43 PM PDT 24 433427466 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3905347031 Jul 05 05:16:56 PM PDT 24 Jul 05 05:17:20 PM PDT 24 8612348082 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3613043333 Jul 05 05:16:47 PM PDT 24 Jul 05 05:16:50 PM PDT 24 545700073 ps
T873 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3018474136 Jul 05 05:17:43 PM PDT 24 Jul 05 05:17:55 PM PDT 24 4142987363 ps
T874 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2421639091 Jul 05 05:16:55 PM PDT 24 Jul 05 05:17:00 PM PDT 24 1249201540 ps
T875 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3804779509 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:59 PM PDT 24 2675921277 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2759656333 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:39 PM PDT 24 354455390 ps
T877 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2312318863 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:54 PM PDT 24 313578988 ps
T878 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3746992533 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:43 PM PDT 24 575721640 ps
T879 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1910486985 Jul 05 05:16:34 PM PDT 24 Jul 05 05:17:22 PM PDT 24 39685214361 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2543671072 Jul 05 05:16:38 PM PDT 24 Jul 05 05:16:41 PM PDT 24 311732058 ps
T881 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3043440021 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:55 PM PDT 24 2207576375 ps
T882 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2657742064 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:56 PM PDT 24 455666244 ps
T883 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4105799428 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:50 PM PDT 24 424017543 ps
T884 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.819745058 Jul 05 05:16:55 PM PDT 24 Jul 05 05:16:59 PM PDT 24 620155372 ps
T885 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.781384128 Jul 05 05:16:56 PM PDT 24 Jul 05 05:17:00 PM PDT 24 691985059 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2565936111 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:54 PM PDT 24 439154741 ps
T339 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1439658596 Jul 05 05:16:53 PM PDT 24 Jul 05 05:17:18 PM PDT 24 8118463798 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3072648853 Jul 05 05:16:46 PM PDT 24 Jul 05 05:16:50 PM PDT 24 2945176267 ps
T337 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1924196947 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:48 PM PDT 24 8770872594 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2407991544 Jul 05 05:16:53 PM PDT 24 Jul 05 05:16:56 PM PDT 24 308612602 ps
T889 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2959379202 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:37 PM PDT 24 5139293661 ps
T890 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.847426191 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:55 PM PDT 24 355624217 ps
T891 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.774955604 Jul 05 05:16:56 PM PDT 24 Jul 05 05:17:00 PM PDT 24 410086726 ps
T892 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1095063211 Jul 05 05:16:40 PM PDT 24 Jul 05 05:16:44 PM PDT 24 1860889977 ps
T893 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.871667417 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:48 PM PDT 24 466321133 ps
T894 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3093187220 Jul 05 05:16:36 PM PDT 24 Jul 05 05:16:38 PM PDT 24 433870248 ps
T895 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3337062525 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:48 PM PDT 24 369168739 ps
T896 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3009974132 Jul 05 05:17:01 PM PDT 24 Jul 05 05:17:04 PM PDT 24 302350872 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3205558755 Jul 05 05:16:52 PM PDT 24 Jul 05 05:16:57 PM PDT 24 529371781 ps
T898 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1931661304 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 489094597 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3875853159 Jul 05 05:16:40 PM PDT 24 Jul 05 05:17:28 PM PDT 24 20639550176 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2201001172 Jul 05 05:16:35 PM PDT 24 Jul 05 05:16:37 PM PDT 24 486552501 ps
T901 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2739041190 Jul 05 05:17:00 PM PDT 24 Jul 05 05:17:04 PM PDT 24 359481159 ps
T902 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.520266476 Jul 05 05:16:37 PM PDT 24 Jul 05 05:16:40 PM PDT 24 2115933092 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3538702230 Jul 05 05:16:33 PM PDT 24 Jul 05 05:16:37 PM PDT 24 987800065 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1680306492 Jul 05 05:16:36 PM PDT 24 Jul 05 05:16:40 PM PDT 24 2559752516 ps
T905 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2792808410 Jul 05 05:16:49 PM PDT 24 Jul 05 05:16:52 PM PDT 24 599982584 ps
T906 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4103249585 Jul 05 05:16:53 PM PDT 24 Jul 05 05:16:58 PM PDT 24 603651301 ps
T907 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2037296133 Jul 05 05:16:40 PM PDT 24 Jul 05 05:16:42 PM PDT 24 825898307 ps
T908 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2864773996 Jul 05 05:16:55 PM PDT 24 Jul 05 05:16:58 PM PDT 24 360290771 ps
T909 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1911587909 Jul 05 05:16:34 PM PDT 24 Jul 05 05:16:39 PM PDT 24 433341482 ps
T910 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.434420043 Jul 05 05:16:45 PM PDT 24 Jul 05 05:16:47 PM PDT 24 348167669 ps
T911 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2644784949 Jul 05 05:16:55 PM PDT 24 Jul 05 05:16:58 PM PDT 24 490175112 ps
T912 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1594219497 Jul 05 05:16:53 PM PDT 24 Jul 05 05:16:57 PM PDT 24 514762227 ps
T913 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1285494374 Jul 05 05:16:54 PM PDT 24 Jul 05 05:16:58 PM PDT 24 560466687 ps
T914 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.556895257 Jul 05 05:16:48 PM PDT 24 Jul 05 05:16:51 PM PDT 24 540019347 ps
T915 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3769290233 Jul 05 05:16:29 PM PDT 24 Jul 05 05:16:32 PM PDT 24 428820827 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.941927853 Jul 05 05:16:39 PM PDT 24 Jul 05 05:16:41 PM PDT 24 484346831 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2679637271 Jul 05 05:16:35 PM PDT 24 Jul 05 05:16:37 PM PDT 24 637575216 ps
T918 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.136143568 Jul 05 05:16:32 PM PDT 24 Jul 05 05:16:36 PM PDT 24 1334407287 ps
T919 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.147975365 Jul 05 05:16:40 PM PDT 24 Jul 05 05:16:42 PM PDT 24 376456421 ps

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.764459125
Short name T1
Test name
Test status
Simulation time 16744228517 ps
CPU time 38.12 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:00:30 PM PDT 24
Peak memory 202120 kb
Host smart-f6c0ba52-e2c1-49c6-b76c-ae60a32eb066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764459125 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.764459125
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1410367618
Short name T45
Test name
Test status
Simulation time 615411538586 ps
CPU time 636.74 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:10:58 PM PDT 24
Peak memory 210428 kb
Host smart-ab9f3431-a766-4845-b21a-754f7d63d578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410367618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1410367618
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4251133455
Short name T13
Test name
Test status
Simulation time 344326226257 ps
CPU time 491.68 seconds
Started Jul 05 05:59:53 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 201888 kb
Host smart-85a5e9e4-fa8d-4784-982f-b2150793b5f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251133455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4251133455
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3244809150
Short name T15
Test name
Test status
Simulation time 912882833771 ps
CPU time 704.22 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:12:01 PM PDT 24
Peak memory 210608 kb
Host smart-a67ccb30-e9d4-4fec-ab45-dc2185805eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244809150 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3244809150
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.826533998
Short name T160
Test name
Test status
Simulation time 366893048150 ps
CPU time 424.23 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:07:21 PM PDT 24
Peak memory 201976 kb
Host smart-209c4fce-f313-491c-80a0-6c53bb5cc945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826533998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.826533998
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3385878396
Short name T87
Test name
Test status
Simulation time 545769272241 ps
CPU time 271.32 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:04:44 PM PDT 24
Peak memory 201908 kb
Host smart-d0409a87-4540-4f5c-a9ae-85894d73f48d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385878396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3385878396
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.659535108
Short name T162
Test name
Test status
Simulation time 522099733651 ps
CPU time 1102.13 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:18:15 PM PDT 24
Peak memory 202000 kb
Host smart-100a28cb-1d5e-4abb-9bfb-a089b49dcf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659535108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.659535108
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3998635235
Short name T26
Test name
Test status
Simulation time 511869411469 ps
CPU time 197.04 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:03:27 PM PDT 24
Peak memory 201884 kb
Host smart-1e3216b0-2aa1-474e-aca8-5ddf41f3de28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998635235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3998635235
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.785678507
Short name T19
Test name
Test status
Simulation time 318121569195 ps
CPU time 639.75 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 06:10:28 PM PDT 24
Peak memory 210508 kb
Host smart-92d6d8dd-c94a-440a-9304-7b268cb4e97e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785678507 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.785678507
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1035578638
Short name T248
Test name
Test status
Simulation time 500101236250 ps
CPU time 671.24 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:11:54 PM PDT 24
Peak memory 201936 kb
Host smart-6ee9d06b-2f70-4d45-bed8-670b80cf66fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035578638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1035578638
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1504346548
Short name T64
Test name
Test status
Simulation time 745069141 ps
CPU time 2.42 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 201788 kb
Host smart-9df38a84-e7e6-4c05-95c3-d3eee1ba2a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504346548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1504346548
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1214615322
Short name T234
Test name
Test status
Simulation time 523915806716 ps
CPU time 1045.2 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:17:50 PM PDT 24
Peak memory 201936 kb
Host smart-0f419544-8dc6-4b01-8561-4efb2cc47295
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214615322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1214615322
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1626805651
Short name T62
Test name
Test status
Simulation time 4456314681 ps
CPU time 6.23 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:00:12 PM PDT 24
Peak memory 217152 kb
Host smart-ae8b189c-a971-4bcb-8c8a-c315aec8e5c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626805651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1626805651
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3300378624
Short name T230
Test name
Test status
Simulation time 501299312913 ps
CPU time 541.97 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:09:42 PM PDT 24
Peak memory 201888 kb
Host smart-ab5b87ee-9052-474f-bf50-e8cdbea306f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300378624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3300378624
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3966300640
Short name T7
Test name
Test status
Simulation time 495499553083 ps
CPU time 280.36 seconds
Started Jul 05 06:02:35 PM PDT 24
Finished Jul 05 06:07:16 PM PDT 24
Peak memory 201920 kb
Host smart-5a973e67-710d-414d-8b79-8474183c1f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966300640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3966300640
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2145949012
Short name T246
Test name
Test status
Simulation time 364851512258 ps
CPU time 764.73 seconds
Started Jul 05 06:01:57 PM PDT 24
Finished Jul 05 06:14:42 PM PDT 24
Peak memory 201928 kb
Host smart-a88db0df-e32d-4eac-b208-f997a51f764b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145949012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2145949012
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1976137550
Short name T38
Test name
Test status
Simulation time 347948622397 ps
CPU time 259.55 seconds
Started Jul 05 06:03:01 PM PDT 24
Finished Jul 05 06:07:21 PM PDT 24
Peak memory 210600 kb
Host smart-4dd9caa3-1dd7-4f5d-b57e-62ae970554d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976137550 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1976137550
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3139893557
Short name T53
Test name
Test status
Simulation time 398209218 ps
CPU time 1.73 seconds
Started Jul 05 05:16:41 PM PDT 24
Finished Jul 05 05:16:44 PM PDT 24
Peak memory 201468 kb
Host smart-2b77f537-368b-4ae6-b532-5a46a971d8aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139893557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3139893557
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.874769554
Short name T261
Test name
Test status
Simulation time 547569026796 ps
CPU time 1173.56 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:20:19 PM PDT 24
Peak memory 201916 kb
Host smart-41b2d880-c388-4132-b3b3-5498ded0a3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874769554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.874769554
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2733877188
Short name T36
Test name
Test status
Simulation time 50380601482 ps
CPU time 37.49 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:02:57 PM PDT 24
Peak memory 210628 kb
Host smart-8164d352-e504-4c43-b394-0584d5b7c222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733877188 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2733877188
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.236826500
Short name T264
Test name
Test status
Simulation time 527144278850 ps
CPU time 1029.09 seconds
Started Jul 05 06:00:53 PM PDT 24
Finished Jul 05 06:18:03 PM PDT 24
Peak memory 201932 kb
Host smart-1d3d2de9-f313-40f3-8bc9-0395a2cf3c9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236826500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.236826500
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.704632167
Short name T275
Test name
Test status
Simulation time 522556385986 ps
CPU time 782.97 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 06:12:48 PM PDT 24
Peak memory 201792 kb
Host smart-afa0c7cc-7f80-4b36-b493-1fe5b354c6f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704632167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.704632167
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2312018622
Short name T137
Test name
Test status
Simulation time 530917347425 ps
CPU time 1148.68 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:19:47 PM PDT 24
Peak memory 201912 kb
Host smart-438e96f3-68aa-40ad-8583-08677b0c44ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312018622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2312018622
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1203731377
Short name T152
Test name
Test status
Simulation time 661969222223 ps
CPU time 280.62 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:05:25 PM PDT 24
Peak memory 201988 kb
Host smart-ff77ad1f-7dbe-44e5-bce7-165c6a5739c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203731377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1203731377
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2865633461
Short name T27
Test name
Test status
Simulation time 457386056229 ps
CPU time 1403.58 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:23:29 PM PDT 24
Peak memory 210408 kb
Host smart-84922457-812a-417e-98f7-c340e34eeb94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865633461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2865633461
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2238415019
Short name T197
Test name
Test status
Simulation time 196071468273 ps
CPU time 389.05 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:06:56 PM PDT 24
Peak memory 201880 kb
Host smart-4ef07c25-e93d-4c5e-8c5d-07c79168a4c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238415019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2238415019
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1730324592
Short name T110
Test name
Test status
Simulation time 541016907221 ps
CPU time 1208.03 seconds
Started Jul 05 06:01:03 PM PDT 24
Finished Jul 05 06:21:12 PM PDT 24
Peak memory 201896 kb
Host smart-3522b70f-57ca-4bf2-b2f7-9e021bc5ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730324592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1730324592
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2588762224
Short name T90
Test name
Test status
Simulation time 492821378462 ps
CPU time 1027.45 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:17:50 PM PDT 24
Peak memory 201868 kb
Host smart-88afcca9-592e-482f-9efb-be6e62fa77fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588762224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2588762224
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1813817845
Short name T20
Test name
Test status
Simulation time 413044586383 ps
CPU time 690.06 seconds
Started Jul 05 06:02:11 PM PDT 24
Finished Jul 05 06:13:41 PM PDT 24
Peak memory 210548 kb
Host smart-dc5ff68d-595d-479a-a580-d43f785aef45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813817845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1813817845
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1175993367
Short name T259
Test name
Test status
Simulation time 504442007744 ps
CPU time 374.85 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:06:38 PM PDT 24
Peak memory 201900 kb
Host smart-662cf33f-75e1-441d-8dfc-e32c8b3d65aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175993367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1175993367
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3078249108
Short name T366
Test name
Test status
Simulation time 462261403 ps
CPU time 1.74 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:00:24 PM PDT 24
Peak memory 201576 kb
Host smart-1e444133-fe14-42f9-8c94-d8535814f81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078249108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3078249108
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2567153755
Short name T281
Test name
Test status
Simulation time 159705573998 ps
CPU time 92.66 seconds
Started Jul 05 06:01:36 PM PDT 24
Finished Jul 05 06:03:09 PM PDT 24
Peak memory 201872 kb
Host smart-2d453584-cc4f-4368-9e4b-71be91a0d75c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567153755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2567153755
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2067644125
Short name T183
Test name
Test status
Simulation time 329901998495 ps
CPU time 165.55 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:03:00 PM PDT 24
Peak memory 201920 kb
Host smart-795f088a-a162-4070-b789-7e3e973b9e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067644125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2067644125
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2807970577
Short name T55
Test name
Test status
Simulation time 4136355186 ps
CPU time 11.39 seconds
Started Jul 05 05:16:43 PM PDT 24
Finished Jul 05 05:16:55 PM PDT 24
Peak memory 201848 kb
Host smart-16ecbeaa-150d-4c79-a264-2f5c235615b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807970577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2807970577
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2461892194
Short name T250
Test name
Test status
Simulation time 355066678172 ps
CPU time 106.62 seconds
Started Jul 05 06:02:40 PM PDT 24
Finished Jul 05 06:04:27 PM PDT 24
Peak memory 201944 kb
Host smart-6faa8be2-1b1f-4f71-848f-e445d65495e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461892194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2461892194
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.829773483
Short name T189
Test name
Test status
Simulation time 489460570945 ps
CPU time 270.9 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:04:45 PM PDT 24
Peak memory 201904 kb
Host smart-5c8551d5-93ad-4009-b00e-b775bdf0ff71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829773483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.829773483
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1232427070
Short name T221
Test name
Test status
Simulation time 360393828165 ps
CPU time 127.06 seconds
Started Jul 05 06:01:35 PM PDT 24
Finished Jul 05 06:03:43 PM PDT 24
Peak memory 201992 kb
Host smart-48dd8f5b-dffe-4207-9999-ce6976c7be81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232427070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1232427070
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2101438542
Short name T151
Test name
Test status
Simulation time 358021950269 ps
CPU time 748.72 seconds
Started Jul 05 06:01:30 PM PDT 24
Finished Jul 05 06:13:59 PM PDT 24
Peak memory 201912 kb
Host smart-e7e1045a-50ae-4616-b920-f02b1f2ae5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101438542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2101438542
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.671123642
Short name T170
Test name
Test status
Simulation time 326299097406 ps
CPU time 120.16 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:02:06 PM PDT 24
Peak memory 201908 kb
Host smart-d2d5e985-9c0a-4dd1-b870-2e24c58dccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671123642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.671123642
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2030675328
Short name T124
Test name
Test status
Simulation time 43195088546 ps
CPU time 28.02 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:17:03 PM PDT 24
Peak memory 201788 kb
Host smart-df7f0519-7a7c-42c8-a570-665d248a4f9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030675328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2030675328
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.155068232
Short name T40
Test name
Test status
Simulation time 849509119429 ps
CPU time 489.88 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:08:38 PM PDT 24
Peak memory 210608 kb
Host smart-abd8a1f2-6657-4cd0-9d59-e792ddaae5c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155068232 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.155068232
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2508256886
Short name T243
Test name
Test status
Simulation time 355518786660 ps
CPU time 421.75 seconds
Started Jul 05 06:00:36 PM PDT 24
Finished Jul 05 06:07:39 PM PDT 24
Peak memory 201928 kb
Host smart-c6e44fe0-9f3c-4a46-aa41-f69eb61ff168
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508256886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2508256886
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3653295627
Short name T289
Test name
Test status
Simulation time 327147105238 ps
CPU time 287.82 seconds
Started Jul 05 06:00:32 PM PDT 24
Finished Jul 05 06:05:20 PM PDT 24
Peak memory 210420 kb
Host smart-f868895b-4946-4840-b988-4951c8852a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653295627 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3653295627
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4186662342
Short name T11
Test name
Test status
Simulation time 327897145239 ps
CPU time 594.85 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:10:37 PM PDT 24
Peak memory 201916 kb
Host smart-0c129812-904b-41ac-ab07-550e6a57cb98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186662342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4186662342
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2342151488
Short name T101
Test name
Test status
Simulation time 491587343318 ps
CPU time 377.59 seconds
Started Jul 05 06:02:17 PM PDT 24
Finished Jul 05 06:08:34 PM PDT 24
Peak memory 201864 kb
Host smart-97e204a1-592e-4faf-8e9f-19821e4c4b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342151488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2342151488
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3035290461
Short name T168
Test name
Test status
Simulation time 331794935303 ps
CPU time 188.65 seconds
Started Jul 05 06:00:07 PM PDT 24
Finished Jul 05 06:03:16 PM PDT 24
Peak memory 201820 kb
Host smart-aa06a62b-6592-4469-8aa4-d48fdc46b3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035290461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3035290461
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3977381302
Short name T251
Test name
Test status
Simulation time 492492111824 ps
CPU time 1177.44 seconds
Started Jul 05 06:02:55 PM PDT 24
Finished Jul 05 06:22:33 PM PDT 24
Peak memory 201900 kb
Host smart-64f29cb4-d87c-4048-9a3a-0e65fe281a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977381302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3977381302
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1329574270
Short name T300
Test name
Test status
Simulation time 164042609220 ps
CPU time 380.28 seconds
Started Jul 05 06:03:43 PM PDT 24
Finished Jul 05 06:10:04 PM PDT 24
Peak memory 201936 kb
Host smart-ea9805c5-157d-488f-852a-0e1dacc7e885
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329574270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1329574270
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1737822438
Short name T222
Test name
Test status
Simulation time 343587500988 ps
CPU time 786.05 seconds
Started Jul 05 05:59:59 PM PDT 24
Finished Jul 05 06:13:06 PM PDT 24
Peak memory 201900 kb
Host smart-f1372505-2454-4f54-aee9-00cc35d7c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737822438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1737822438
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.473262421
Short name T364
Test name
Test status
Simulation time 400934568563 ps
CPU time 445.73 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:07:50 PM PDT 24
Peak memory 201808 kb
Host smart-aa23fbee-abac-4fcb-a13e-c3afaf0cd0ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473262421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.473262421
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3453895002
Short name T209
Test name
Test status
Simulation time 402320414741 ps
CPU time 1107.11 seconds
Started Jul 05 06:02:44 PM PDT 24
Finished Jul 05 06:21:11 PM PDT 24
Peak memory 210432 kb
Host smart-940b2d00-899d-4033-851a-88a5f7e6c3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453895002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3453895002
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2742687375
Short name T225
Test name
Test status
Simulation time 509685545347 ps
CPU time 299.16 seconds
Started Jul 05 06:03:56 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 201960 kb
Host smart-dffc2604-429c-4173-bca3-cfa5decd76ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742687375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2742687375
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1578791125
Short name T231
Test name
Test status
Simulation time 327354833727 ps
CPU time 154.1 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:02:50 PM PDT 24
Peak memory 202152 kb
Host smart-fc119367-49b4-4c15-a62b-5bb43d149b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578791125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1578791125
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.22571287
Short name T542
Test name
Test status
Simulation time 480665283590 ps
CPU time 1530.46 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:26:08 PM PDT 24
Peak memory 202260 kb
Host smart-781ab64c-da2d-4c24-87e7-4d0dae6adcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.22571287
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.108068554
Short name T216
Test name
Test status
Simulation time 485160072794 ps
CPU time 1007.45 seconds
Started Jul 05 06:00:33 PM PDT 24
Finished Jul 05 06:17:21 PM PDT 24
Peak memory 201996 kb
Host smart-8b669cbc-52fa-45e7-85e5-096815696ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108068554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.108068554
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3885929404
Short name T293
Test name
Test status
Simulation time 162526558402 ps
CPU time 391.23 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:07:10 PM PDT 24
Peak memory 201984 kb
Host smart-836fa347-c072-4585-bf07-0443d0fd9172
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885929404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3885929404
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3861551256
Short name T227
Test name
Test status
Simulation time 160653334616 ps
CPU time 102.95 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 06:01:37 PM PDT 24
Peak memory 201916 kb
Host smart-0f34b777-ee11-4b16-aac9-5ea3f734fa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861551256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3861551256
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4292062493
Short name T295
Test name
Test status
Simulation time 497175042883 ps
CPU time 599.04 seconds
Started Jul 05 06:00:07 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 201892 kb
Host smart-7eabef25-dba6-419e-8b93-4e28b884df9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292062493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4292062493
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.478688319
Short name T76
Test name
Test status
Simulation time 1200231530 ps
CPU time 3.49 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 210944 kb
Host smart-544f7cb3-dc67-40f5-8a47-e6f6eee33073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478688319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.478688319
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.868177445
Short name T205
Test name
Test status
Simulation time 118902842125 ps
CPU time 407 seconds
Started Jul 05 06:00:12 PM PDT 24
Finished Jul 05 06:07:00 PM PDT 24
Peak memory 202188 kb
Host smart-1d7a8dfd-9632-4502-bcde-5ac5cb9d52c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868177445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.868177445
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4085304180
Short name T320
Test name
Test status
Simulation time 488606257611 ps
CPU time 1075.89 seconds
Started Jul 05 06:00:33 PM PDT 24
Finished Jul 05 06:18:29 PM PDT 24
Peak memory 201972 kb
Host smart-48eab24f-1318-4f47-87bb-5fc9f3d62d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085304180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4085304180
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3098224866
Short name T57
Test name
Test status
Simulation time 382831775368 ps
CPU time 650.05 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:11:17 PM PDT 24
Peak memory 217788 kb
Host smart-6f9fd945-89c7-49d8-a2a3-51fbaa865cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098224866 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3098224866
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.617949091
Short name T323
Test name
Test status
Simulation time 161533440717 ps
CPU time 37.76 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:01:07 PM PDT 24
Peak memory 201916 kb
Host smart-1fa28f2f-a93d-4bb8-a08e-96bd3cdee2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617949091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.617949091
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3521593884
Short name T270
Test name
Test status
Simulation time 331824571645 ps
CPU time 366.94 seconds
Started Jul 05 06:00:58 PM PDT 24
Finished Jul 05 06:07:05 PM PDT 24
Peak memory 201976 kb
Host smart-7c367c68-ae78-4b4b-b9b2-0e5e90ed90a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521593884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3521593884
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1977043888
Short name T163
Test name
Test status
Simulation time 493338791098 ps
CPU time 88.33 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:03:01 PM PDT 24
Peak memory 201936 kb
Host smart-673c9b26-9f55-4197-ae43-d7d4f7981a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977043888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1977043888
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1040142998
Short name T212
Test name
Test status
Simulation time 1402729999214 ps
CPU time 3191.99 seconds
Started Jul 05 06:02:11 PM PDT 24
Finished Jul 05 06:55:24 PM PDT 24
Peak memory 213392 kb
Host smart-b00dd4ff-73b9-4b68-8256-fe129f203dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040142998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1040142998
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.598262216
Short name T81
Test name
Test status
Simulation time 4774416194 ps
CPU time 7.59 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 201884 kb
Host smart-3ba7f896-64af-4c83-a46b-062b95333282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598262216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.598262216
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.726286053
Short name T179
Test name
Test status
Simulation time 588174483248 ps
CPU time 258.23 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:04:29 PM PDT 24
Peak memory 201912 kb
Host smart-11de5741-4cd0-48a4-8e4c-af1527615cd0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726286053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.726286053
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2305945774
Short name T291
Test name
Test status
Simulation time 560140518230 ps
CPU time 1262.3 seconds
Started Jul 05 06:00:59 PM PDT 24
Finished Jul 05 06:22:01 PM PDT 24
Peak memory 201984 kb
Host smart-84df094d-219f-494f-9ad3-49beda58db21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305945774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2305945774
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.41524517
Short name T332
Test name
Test status
Simulation time 486753480543 ps
CPU time 1082.21 seconds
Started Jul 05 06:01:29 PM PDT 24
Finished Jul 05 06:19:31 PM PDT 24
Peak memory 201876 kb
Host smart-492612ce-6d97-4256-a116-40727951a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41524517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.41524517
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1299784535
Short name T266
Test name
Test status
Simulation time 366696509543 ps
CPU time 690.25 seconds
Started Jul 05 06:01:52 PM PDT 24
Finished Jul 05 06:13:22 PM PDT 24
Peak memory 211872 kb
Host smart-eb54b28d-3e91-467d-85ce-c34149689a49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299784535 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1299784535
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2477418969
Short name T78
Test name
Test status
Simulation time 8408802828 ps
CPU time 20.27 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:17:17 PM PDT 24
Peak memory 201820 kb
Host smart-d4954e3c-7d26-4ce9-bd74-87b321834f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477418969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2477418969
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.830872585
Short name T201
Test name
Test status
Simulation time 100693647786 ps
CPU time 540.23 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 202096 kb
Host smart-1e7cbb66-d71e-4eb6-964b-9e93ee40ba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830872585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.830872585
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3583274255
Short name T276
Test name
Test status
Simulation time 344344870824 ps
CPU time 759.85 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:13:00 PM PDT 24
Peak memory 201876 kb
Host smart-ef561dbc-57e2-4a9e-bb94-18b9bf20f28a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583274255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3583274255
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.289450180
Short name T184
Test name
Test status
Simulation time 541059573380 ps
CPU time 256.58 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:04:54 PM PDT 24
Peak memory 201916 kb
Host smart-ac9614ed-2e7f-46f9-b97a-6276394daf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289450180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.289450180
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.643500629
Short name T330
Test name
Test status
Simulation time 401731714380 ps
CPU time 453 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 201908 kb
Host smart-ea4df9c4-5a54-4ec6-ae30-12f205ae0aca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643500629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.643500629
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1395510221
Short name T206
Test name
Test status
Simulation time 133898609216 ps
CPU time 447.45 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 202216 kb
Host smart-768f7978-d7c7-45ca-935f-fbcbfd4772fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395510221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1395510221
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3645572259
Short name T296
Test name
Test status
Simulation time 172990033296 ps
CPU time 367.77 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:06:43 PM PDT 24
Peak memory 201916 kb
Host smart-6afafef5-3493-4ca2-b100-ca182b161ea6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645572259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3645572259
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3675239909
Short name T242
Test name
Test status
Simulation time 516295262299 ps
CPU time 389.38 seconds
Started Jul 05 06:00:43 PM PDT 24
Finished Jul 05 06:07:14 PM PDT 24
Peak memory 201904 kb
Host smart-9722d172-2152-4352-aa37-ec563432edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675239909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3675239909
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1493912383
Short name T202
Test name
Test status
Simulation time 145397103144 ps
CPU time 509.11 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:08:21 PM PDT 24
Peak memory 202140 kb
Host smart-086e51a7-b3de-4784-8b76-5bc19e1575f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493912383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1493912383
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2888710850
Short name T213
Test name
Test status
Simulation time 126854824865 ps
CPU time 399.61 seconds
Started Jul 05 06:01:04 PM PDT 24
Finished Jul 05 06:07:44 PM PDT 24
Peak memory 202224 kb
Host smart-2954bc9a-48ac-4ef5-9940-37f963ad6a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888710850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2888710850
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.231702501
Short name T58
Test name
Test status
Simulation time 42134192516 ps
CPU time 112.39 seconds
Started Jul 05 06:02:45 PM PDT 24
Finished Jul 05 06:04:38 PM PDT 24
Peak memory 218036 kb
Host smart-96280410-8f7f-4700-a093-5ffb70eed586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231702501 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.231702501
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1595161455
Short name T187
Test name
Test status
Simulation time 336990014549 ps
CPU time 152.38 seconds
Started Jul 05 06:03:57 PM PDT 24
Finished Jul 05 06:06:30 PM PDT 24
Peak memory 201992 kb
Host smart-71c27d58-ca87-4dba-9126-6787b32d617f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595161455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1595161455
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2492795417
Short name T109
Test name
Test status
Simulation time 507085696321 ps
CPU time 539.1 seconds
Started Jul 05 05:59:56 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 201936 kb
Host smart-01f81878-c04e-49d0-b4fd-535558aaca15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492795417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2492795417
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.781384128
Short name T885
Test name
Test status
Simulation time 691985059 ps
CPU time 2.23 seconds
Started Jul 05 05:16:56 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 201624 kb
Host smart-0a6a8368-1c44-4211-8019-8ea4fa3d1625
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781384128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.781384128
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3171544593
Short name T830
Test name
Test status
Simulation time 52953729495 ps
CPU time 205.5 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:19:58 PM PDT 24
Peak memory 201832 kb
Host smart-f9f5bfb1-e7b1-425a-a7f1-ff7e25a7a9cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171544593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3171544593
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1726041865
Short name T806
Test name
Test status
Simulation time 686244242 ps
CPU time 2.21 seconds
Started Jul 05 05:16:30 PM PDT 24
Finished Jul 05 05:16:33 PM PDT 24
Peak memory 201488 kb
Host smart-10bfc8d2-c94d-4041-8244-6bc90633fc17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726041865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1726041865
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2201001172
Short name T900
Test name
Test status
Simulation time 486552501 ps
CPU time 1.05 seconds
Started Jul 05 05:16:35 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 201540 kb
Host smart-fdefe259-bc47-4104-aad5-7051c9f13d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201001172 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2201001172
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3769290233
Short name T915
Test name
Test status
Simulation time 428820827 ps
CPU time 1.48 seconds
Started Jul 05 05:16:29 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 201500 kb
Host smart-9035a505-b4fe-4c44-9e2a-8cfcaf336c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769290233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3769290233
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.18431716
Short name T836
Test name
Test status
Simulation time 493233807 ps
CPU time 1.93 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 201444 kb
Host smart-8933b1cf-a09a-4eec-b627-ca6d920ac564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18431716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.18431716
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2959379202
Short name T889
Test name
Test status
Simulation time 5139293661 ps
CPU time 3.73 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 201844 kb
Host smart-552c840f-528e-4b65-b49b-bc6fa429d6fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959379202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2959379202
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1911587909
Short name T909
Test name
Test status
Simulation time 433341482 ps
CPU time 3.24 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:16:39 PM PDT 24
Peak memory 217768 kb
Host smart-824fa81c-2728-4fbc-9235-2f4982e23313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911587909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1911587909
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1146887797
Short name T869
Test name
Test status
Simulation time 4183777000 ps
CPU time 4.93 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 201824 kb
Host smart-9c8ce9a0-05ba-45bc-9ba6-ea37c3ef7009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146887797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1146887797
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.578459555
Short name T118
Test name
Test status
Simulation time 441436916 ps
CPU time 1.91 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:34 PM PDT 24
Peak memory 201580 kb
Host smart-6edcc53e-d5fa-4a58-943c-9470d4eadfa3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578459555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.578459555
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1910486985
Short name T879
Test name
Test status
Simulation time 39685214361 ps
CPU time 47.74 seconds
Started Jul 05 05:16:34 PM PDT 24
Finished Jul 05 05:17:22 PM PDT 24
Peak memory 201856 kb
Host smart-de2f7d15-8222-45c6-a568-c189ea4d1741
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910486985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1910486985
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3069039952
Short name T865
Test name
Test status
Simulation time 1069021657 ps
CPU time 3 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 201424 kb
Host smart-79a14d09-b02e-4128-909a-38359104f5ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069039952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3069039952
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.499663645
Short name T861
Test name
Test status
Simulation time 579692732 ps
CPU time 1.02 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:34 PM PDT 24
Peak memory 201588 kb
Host smart-1ace0867-997b-48d7-a189-8a2ee90f5261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499663645 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.499663645
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.584519986
Short name T116
Test name
Test status
Simulation time 498288566 ps
CPU time 1.09 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:34 PM PDT 24
Peak memory 201500 kb
Host smart-835b263b-8ce9-43ed-b0e7-8032c90ee57e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584519986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.584519986
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2961947007
Short name T850
Test name
Test status
Simulation time 513193365 ps
CPU time 0.94 seconds
Started Jul 05 05:16:33 PM PDT 24
Finished Jul 05 05:16:35 PM PDT 24
Peak memory 201428 kb
Host smart-961dccf3-a032-4f06-a253-4d1a413db549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961947007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2961947007
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1500443541
Short name T52
Test name
Test status
Simulation time 5169705013 ps
CPU time 3.19 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 201836 kb
Host smart-24526d95-3426-43de-b798-a21e087ea75e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500443541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1500443541
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3538702230
Short name T903
Test name
Test status
Simulation time 987800065 ps
CPU time 3.01 seconds
Started Jul 05 05:16:33 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 217640 kb
Host smart-0c122e60-7642-40e9-9e6f-66eb1beb1dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538702230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3538702230
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1129737308
Short name T809
Test name
Test status
Simulation time 521652251 ps
CPU time 2.1 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 201556 kb
Host smart-c9d474b8-7a29-4815-90d9-4f145132d5b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129737308 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1129737308
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1265824299
Short name T123
Test name
Test status
Simulation time 524168303 ps
CPU time 1.85 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 201496 kb
Host smart-e22a0a5c-501e-4691-bbf2-fb2e97b3c943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265824299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1265824299
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.571642862
Short name T845
Test name
Test status
Simulation time 401707381 ps
CPU time 1.59 seconds
Started Jul 05 05:17:19 PM PDT 24
Finished Jul 05 05:17:21 PM PDT 24
Peak memory 201396 kb
Host smart-7056950a-87c7-42c9-991a-ff9cd6ab35fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571642862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.571642862
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3804779509
Short name T875
Test name
Test status
Simulation time 2675921277 ps
CPU time 11.92 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:59 PM PDT 24
Peak memory 201568 kb
Host smart-56281ef0-676a-4518-92e4-679d5b6100f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804779509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3804779509
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3337062525
Short name T895
Test name
Test status
Simulation time 369168739 ps
CPU time 1.43 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 201724 kb
Host smart-4e089d00-2d0b-4057-937b-7ddba03056ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337062525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3337062525
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4178701179
Short name T828
Test name
Test status
Simulation time 8970356514 ps
CPU time 8.25 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:57 PM PDT 24
Peak memory 201888 kb
Host smart-00ec32c3-f306-4645-b323-92f300b07ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178701179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4178701179
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1787029616
Short name T817
Test name
Test status
Simulation time 693555272 ps
CPU time 1.1 seconds
Started Jul 05 05:16:46 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 201556 kb
Host smart-32cc9bd5-4390-40e8-8a6f-844d90363aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787029616 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1787029616
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.819167246
Short name T121
Test name
Test status
Simulation time 377591629 ps
CPU time 1.23 seconds
Started Jul 05 05:16:47 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 201436 kb
Host smart-dce322cd-bb9f-46c5-bfef-35b20fa48420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819167246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.819167246
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1776005631
Short name T847
Test name
Test status
Simulation time 396811538 ps
CPU time 0.84 seconds
Started Jul 05 05:16:47 PM PDT 24
Finished Jul 05 05:16:49 PM PDT 24
Peak memory 201448 kb
Host smart-2b951f54-9447-46cd-a8ad-de430c74fa7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776005631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1776005631
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2315014371
Short name T826
Test name
Test status
Simulation time 2073230411 ps
CPU time 2.9 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201528 kb
Host smart-fea7f16e-ca8a-4169-9adc-4342f896de31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315014371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2315014371
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.515526973
Short name T851
Test name
Test status
Simulation time 4171396006 ps
CPU time 2.92 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:49 PM PDT 24
Peak memory 201852 kb
Host smart-470ba2b2-c908-4507-81c2-ed1ca91477ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515526973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.515526973
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1352105174
Short name T819
Test name
Test status
Simulation time 373306869 ps
CPU time 1.76 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:47 PM PDT 24
Peak memory 201496 kb
Host smart-b89c0924-bccd-46fa-b97a-d235e31befa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352105174 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1352105174
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.556895257
Short name T914
Test name
Test status
Simulation time 540019347 ps
CPU time 1.06 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:51 PM PDT 24
Peak memory 201504 kb
Host smart-398e916e-7c2d-4b12-b0c8-78446c427dfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556895257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.556895257
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2756466062
Short name T813
Test name
Test status
Simulation time 538494424 ps
CPU time 1.29 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:47 PM PDT 24
Peak memory 201396 kb
Host smart-f6c2c5a8-a749-47fc-993f-32b9907287c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756466062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2756466062
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3072648853
Short name T887
Test name
Test status
Simulation time 2945176267 ps
CPU time 2.55 seconds
Started Jul 05 05:16:46 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 201620 kb
Host smart-964668eb-6a3a-4716-a945-e6a473ad3501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072648853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3072648853
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.871667417
Short name T893
Test name
Test status
Simulation time 466321133 ps
CPU time 1.8 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 218016 kb
Host smart-6dbc93ae-086e-4b06-b571-f23fe1fc9343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871667417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.871667417
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.761738744
Short name T812
Test name
Test status
Simulation time 4182526903 ps
CPU time 11.24 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:17:01 PM PDT 24
Peak memory 201852 kb
Host smart-fa259220-ceb3-493c-a3c8-3f64e44532c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761738744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.761738744
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4105799428
Short name T883
Test name
Test status
Simulation time 424017543 ps
CPU time 1.11 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 201596 kb
Host smart-00036a90-2b31-4875-bae1-6e3f7d84dc85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105799428 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4105799428
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.802007561
Short name T127
Test name
Test status
Simulation time 329135341 ps
CPU time 0.93 seconds
Started Jul 05 05:16:43 PM PDT 24
Finished Jul 05 05:16:45 PM PDT 24
Peak memory 201500 kb
Host smart-5d1a5a7e-e6d2-4625-a575-b545eec261b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802007561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.802007561
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.434420043
Short name T910
Test name
Test status
Simulation time 348167669 ps
CPU time 0.88 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:47 PM PDT 24
Peak memory 201420 kb
Host smart-1f1c4af3-2dc5-4b59-a137-71a3b13cd20e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434420043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.434420043
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3320147255
Short name T839
Test name
Test status
Simulation time 2306125915 ps
CPU time 2.56 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201620 kb
Host smart-837219e1-5061-4fec-aa89-31a5b9558e16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320147255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3320147255
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1285494374
Short name T913
Test name
Test status
Simulation time 560466687 ps
CPU time 1.3 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201504 kb
Host smart-a48f8bca-bc0f-477b-910a-fa66754532eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285494374 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1285494374
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2270095230
Short name T832
Test name
Test status
Simulation time 319850135 ps
CPU time 1.1 seconds
Started Jul 05 05:16:43 PM PDT 24
Finished Jul 05 05:16:45 PM PDT 24
Peak memory 201492 kb
Host smart-e5cd06ab-62c5-4689-9520-b744cdc106bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270095230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2270095230
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2837680479
Short name T804
Test name
Test status
Simulation time 426392241 ps
CPU time 0.89 seconds
Started Jul 05 05:16:46 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 201420 kb
Host smart-bed6ceb3-92a5-404f-9d55-c5dcbfa721e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837680479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2837680479
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2939759124
Short name T829
Test name
Test status
Simulation time 4515367756 ps
CPU time 5.99 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:17:04 PM PDT 24
Peak memory 201836 kb
Host smart-668338c6-f20f-4305-bd6d-491afa70a2d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939759124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2939759124
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1309584869
Short name T75
Test name
Test status
Simulation time 745645265 ps
CPU time 2.68 seconds
Started Jul 05 05:16:49 PM PDT 24
Finished Jul 05 05:16:53 PM PDT 24
Peak memory 217600 kb
Host smart-ce500620-95eb-47b5-bb37-40a433564ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309584869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1309584869
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3664347953
Short name T56
Test name
Test status
Simulation time 4584320733 ps
CPU time 4.36 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201836 kb
Host smart-5109ab12-7497-4aa0-b48e-1aba55bc02f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664347953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3664347953
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3496720050
Short name T842
Test name
Test status
Simulation time 490671013 ps
CPU time 2.14 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201588 kb
Host smart-43f4bcfc-5d8a-4eb3-bd8d-412830b5934c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496720050 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3496720050
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.847426191
Short name T890
Test name
Test status
Simulation time 355624217 ps
CPU time 1.19 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:55 PM PDT 24
Peak memory 201484 kb
Host smart-aabf2d99-e3d5-41d6-b035-bdb919690d5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847426191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.847426191
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4176262434
Short name T833
Test name
Test status
Simulation time 350435037 ps
CPU time 0.82 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201436 kb
Host smart-383202d7-eed8-4f25-bf89-49272ac64a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176262434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4176262434
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.43568512
Short name T51
Test name
Test status
Simulation time 4915993028 ps
CPU time 17.19 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:17:11 PM PDT 24
Peak memory 201736 kb
Host smart-450fad92-cc86-47d9-aa3f-71db27783494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43568512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ct
rl_same_csr_outstanding.43568512
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2421639091
Short name T874
Test name
Test status
Simulation time 1249201540 ps
CPU time 2.87 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 211012 kb
Host smart-0db890ec-21d6-4260-9a8b-71b62585af03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421639091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2421639091
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3753144298
Short name T92
Test name
Test status
Simulation time 645358240 ps
CPU time 1.03 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201576 kb
Host smart-9ea08c8a-3690-4d4f-887b-7766283c7f86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753144298 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3753144298
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2407991544
Short name T888
Test name
Test status
Simulation time 308612602 ps
CPU time 1.07 seconds
Started Jul 05 05:16:53 PM PDT 24
Finished Jul 05 05:16:56 PM PDT 24
Peak memory 201460 kb
Host smart-0ec44164-a4a8-41b7-a8f1-5a49e30be8f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407991544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2407991544
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1594219497
Short name T912
Test name
Test status
Simulation time 514762227 ps
CPU time 1.18 seconds
Started Jul 05 05:16:53 PM PDT 24
Finished Jul 05 05:16:57 PM PDT 24
Peak memory 201416 kb
Host smart-669f0cd0-8cc8-4837-8cb1-613e1a8a9677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594219497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1594219497
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.774882944
Short name T840
Test name
Test status
Simulation time 4601346829 ps
CPU time 18.57 seconds
Started Jul 05 05:16:51 PM PDT 24
Finished Jul 05 05:17:10 PM PDT 24
Peak memory 201836 kb
Host smart-a1014749-98d8-4c21-a179-ece0362b786f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774882944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.774882944
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.4103249585
Short name T906
Test name
Test status
Simulation time 603651301 ps
CPU time 2.52 seconds
Started Jul 05 05:16:53 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201744 kb
Host smart-70256555-7048-4d13-a161-5494b7e9c5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103249585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.4103249585
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1439658596
Short name T339
Test name
Test status
Simulation time 8118463798 ps
CPU time 21.96 seconds
Started Jul 05 05:16:53 PM PDT 24
Finished Jul 05 05:17:18 PM PDT 24
Peak memory 201752 kb
Host smart-fb9d7585-ee6c-4a8d-85c5-75ff95c305ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439658596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1439658596
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.819745058
Short name T884
Test name
Test status
Simulation time 620155372 ps
CPU time 1.34 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:16:59 PM PDT 24
Peak memory 201584 kb
Host smart-1c825921-d2ec-4a16-8e91-f8284f7616db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819745058 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.819745058
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2565936111
Short name T886
Test name
Test status
Simulation time 439154741 ps
CPU time 1.05 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201504 kb
Host smart-faf0203f-a1c6-4dce-994f-6ed258a1cd6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565936111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2565936111
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2312318863
Short name T877
Test name
Test status
Simulation time 313578988 ps
CPU time 0.91 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201412 kb
Host smart-ab7cf545-c980-4d38-b4d9-e4bc654e5b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312318863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2312318863
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2023678397
Short name T857
Test name
Test status
Simulation time 2288839879 ps
CPU time 5.5 seconds
Started Jul 05 05:16:53 PM PDT 24
Finished Jul 05 05:17:01 PM PDT 24
Peak memory 201620 kb
Host smart-e5751f13-c9a4-48cf-be5c-83a6f9e5ed0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023678397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2023678397
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3205558755
Short name T897
Test name
Test status
Simulation time 529371781 ps
CPU time 3.21 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:57 PM PDT 24
Peak memory 201764 kb
Host smart-58236020-7fd2-4e5b-9730-00f988430800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205558755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3205558755
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2750092317
Short name T863
Test name
Test status
Simulation time 4624295482 ps
CPU time 4.12 seconds
Started Jul 05 05:16:49 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201756 kb
Host smart-91ca2bc3-8cea-4b30-8632-9ec5742d2a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750092317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2750092317
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.682877887
Short name T822
Test name
Test status
Simulation time 510564684 ps
CPU time 1.15 seconds
Started Jul 05 05:16:53 PM PDT 24
Finished Jul 05 05:16:56 PM PDT 24
Peak memory 201592 kb
Host smart-fbbe1216-cac9-48dc-9e45-8b505eca73e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682877887 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.682877887
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.122190699
Short name T117
Test name
Test status
Simulation time 388103333 ps
CPU time 0.96 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:57 PM PDT 24
Peak memory 201460 kb
Host smart-37972353-812f-4d10-b950-62008c325556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122190699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.122190699
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4126919050
Short name T799
Test name
Test status
Simulation time 460028614 ps
CPU time 1.69 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:16:59 PM PDT 24
Peak memory 201444 kb
Host smart-c21b80ea-12c4-481c-88d7-d4ea3eea66a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126919050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4126919050
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3043440021
Short name T881
Test name
Test status
Simulation time 2207576375 ps
CPU time 2.11 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:55 PM PDT 24
Peak memory 201632 kb
Host smart-d14a38c7-92da-4a23-a05f-c4792b297b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043440021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3043440021
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1045729452
Short name T65
Test name
Test status
Simulation time 711364085 ps
CPU time 1.83 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201768 kb
Host smart-fd3aff79-2f1c-4eff-a307-ac3083255ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045729452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1045729452
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3905347031
Short name T871
Test name
Test status
Simulation time 8612348082 ps
CPU time 21.18 seconds
Started Jul 05 05:16:56 PM PDT 24
Finished Jul 05 05:17:20 PM PDT 24
Peak memory 201816 kb
Host smart-3f948f14-1316-4794-9ddc-d40019af862c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905347031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3905347031
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1817472795
Short name T59
Test name
Test status
Simulation time 493154121 ps
CPU time 1.26 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:57 PM PDT 24
Peak memory 201548 kb
Host smart-8cf0fb54-bd73-4a77-a9b9-631e3065adf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817472795 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1817472795
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1941037648
Short name T115
Test name
Test status
Simulation time 529748935 ps
CPU time 1.97 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:56 PM PDT 24
Peak memory 201472 kb
Host smart-318874ff-1d56-4037-bb10-b9f507492a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941037648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1941037648
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3129701024
Short name T820
Test name
Test status
Simulation time 464823989 ps
CPU time 1.68 seconds
Started Jul 05 05:16:51 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201292 kb
Host smart-c61924f0-9591-4cd3-97c6-bcc1a33e2bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129701024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3129701024
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3591202505
Short name T128
Test name
Test status
Simulation time 1765900311 ps
CPU time 2.58 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:59 PM PDT 24
Peak memory 201504 kb
Host smart-c17dc4a1-0e2f-4bad-80da-46f9de50ecce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591202505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3591202505
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1931661304
Short name T898
Test name
Test status
Simulation time 489094597 ps
CPU time 1.92 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 200748 kb
Host smart-9e5a1eea-d6a5-493d-9505-3b4f91bad775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931661304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1931661304
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.81023248
Short name T338
Test name
Test status
Simulation time 4547448911 ps
CPU time 2.76 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 201864 kb
Host smart-581e30f2-2e6c-4745-990f-25ed4a6615cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81023248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_int
g_err.81023248
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.136143568
Short name T918
Test name
Test status
Simulation time 1334407287 ps
CPU time 3.2 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 201672 kb
Host smart-a6c7147d-9a55-4713-84bd-ee3010020a3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136143568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.136143568
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1777655300
Short name T120
Test name
Test status
Simulation time 992960806 ps
CPU time 1.57 seconds
Started Jul 05 05:16:33 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 201516 kb
Host smart-f26ad2a9-bfbb-43ed-8ed8-8b87d26a2430
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777655300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1777655300
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2759656333
Short name T876
Test name
Test status
Simulation time 354455390 ps
CPU time 1.35 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:39 PM PDT 24
Peak memory 201572 kb
Host smart-b917aa9b-f09a-446f-9190-1ed45d0a91ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759656333 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2759656333
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.147975365
Short name T919
Test name
Test status
Simulation time 376456421 ps
CPU time 1.19 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:16:42 PM PDT 24
Peak memory 201500 kb
Host smart-eba5f64a-b168-4b15-848d-441f71dae4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147975365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.147975365
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3901385851
Short name T852
Test name
Test status
Simulation time 444823273 ps
CPU time 0.92 seconds
Started Jul 05 05:16:32 PM PDT 24
Finished Jul 05 05:16:34 PM PDT 24
Peak memory 201344 kb
Host smart-cc61faa1-7f50-45f9-bbc7-ef81ccf44636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901385851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3901385851
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.520266476
Short name T902
Test name
Test status
Simulation time 2115933092 ps
CPU time 2.98 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 201428 kb
Host smart-1b3c4523-f42f-470d-b54e-fbc04e371eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520266476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.520266476
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.129793028
Short name T67
Test name
Test status
Simulation time 376906511 ps
CPU time 2.08 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:34 PM PDT 24
Peak memory 201804 kb
Host smart-7960574a-dbfd-4409-8982-40ae2841b0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129793028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.129793028
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1686198820
Short name T858
Test name
Test status
Simulation time 8982041595 ps
CPU time 7.81 seconds
Started Jul 05 05:16:31 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 201884 kb
Host smart-c273ac5d-b3d9-439d-bd57-56d97e76761e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686198820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1686198820
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.353958558
Short name T814
Test name
Test status
Simulation time 496285172 ps
CPU time 0.95 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201388 kb
Host smart-371d5772-6658-404b-9ca1-27473a0d9eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353958558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.353958558
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3120635691
Short name T846
Test name
Test status
Simulation time 403847448 ps
CPU time 1.1 seconds
Started Jul 05 05:16:56 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 201444 kb
Host smart-56779222-33b5-40bb-b7da-b87549c686b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120635691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3120635691
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.787449607
Short name T854
Test name
Test status
Simulation time 305722438 ps
CPU time 1.27 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201380 kb
Host smart-d73750ea-ee1b-44cb-ae6b-4cef881ffd6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787449607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.787449607
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1367068845
Short name T844
Test name
Test status
Simulation time 545539669 ps
CPU time 0.74 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:54 PM PDT 24
Peak memory 201456 kb
Host smart-8713ec17-7c9a-430f-a615-ed43a0c9eb97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367068845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1367068845
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2657742064
Short name T882
Test name
Test status
Simulation time 455666244 ps
CPU time 1.6 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:56 PM PDT 24
Peak memory 201320 kb
Host smart-08bf25a8-44a2-44ff-a0ad-a8d155e4352f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657742064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2657742064
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.774955604
Short name T891
Test name
Test status
Simulation time 410086726 ps
CPU time 1.55 seconds
Started Jul 05 05:16:56 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 201336 kb
Host smart-02f9d095-6283-4a80-ae42-53ebb6766369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774955604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.774955604
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2788609357
Short name T816
Test name
Test status
Simulation time 389951737 ps
CPU time 0.86 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:57 PM PDT 24
Peak memory 200400 kb
Host smart-407b7efe-a018-43aa-9018-64b6d8531df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788609357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2788609357
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2644784949
Short name T911
Test name
Test status
Simulation time 490175112 ps
CPU time 1.24 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201444 kb
Host smart-43b9bece-e451-4397-8a76-295d856886a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644784949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2644784949
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3847203947
Short name T798
Test name
Test status
Simulation time 417844681 ps
CPU time 1.55 seconds
Started Jul 05 05:16:54 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201368 kb
Host smart-a592cfca-233f-45fc-8e28-4aad9106c623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847203947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3847203947
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2934267903
Short name T864
Test name
Test status
Simulation time 452035491 ps
CPU time 0.71 seconds
Started Jul 05 05:16:51 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201444 kb
Host smart-935eb3fa-553b-42e5-be8d-473291f58983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934267903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2934267903
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3905443837
Short name T122
Test name
Test status
Simulation time 574375795 ps
CPU time 2.64 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201640 kb
Host smart-204d2a45-8553-48c2-a165-f2706128288c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905443837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3905443837
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3875853159
Short name T899
Test name
Test status
Simulation time 20639550176 ps
CPU time 47.35 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:17:28 PM PDT 24
Peak memory 201788 kb
Host smart-f8968c1c-b616-42a3-ae37-c85e59b2609c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875853159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3875853159
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2792808410
Short name T905
Test name
Test status
Simulation time 599982584 ps
CPU time 2.06 seconds
Started Jul 05 05:16:49 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201496 kb
Host smart-bc00fc40-172b-4ec6-8b1d-25279cb04fc5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792808410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2792808410
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.941927853
Short name T916
Test name
Test status
Simulation time 484346831 ps
CPU time 1.01 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201556 kb
Host smart-9459ae87-cdc9-4c07-a076-11ffe374ad6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941927853 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.941927853
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3093187220
Short name T894
Test name
Test status
Simulation time 433870248 ps
CPU time 1.01 seconds
Started Jul 05 05:16:36 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 201420 kb
Host smart-d1dc7ff1-6bf7-461b-bb1f-b5673e58a732
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093187220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3093187220
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.312467431
Short name T811
Test name
Test status
Simulation time 446396137 ps
CPU time 1.52 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:39 PM PDT 24
Peak memory 201416 kb
Host smart-edff5514-f46d-44c5-a3aa-e1c049f636be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312467431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.312467431
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3189305924
Short name T835
Test name
Test status
Simulation time 2156968198 ps
CPU time 4.15 seconds
Started Jul 05 05:16:41 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 201568 kb
Host smart-b1039300-5225-4407-99c7-629fe8ac4fff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189305924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3189305924
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2543671072
Short name T880
Test name
Test status
Simulation time 311732058 ps
CPU time 2.36 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201652 kb
Host smart-e56b1821-4500-48ef-9c96-7fc4a430099f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543671072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2543671072
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3018474136
Short name T873
Test name
Test status
Simulation time 4142987363 ps
CPU time 11.33 seconds
Started Jul 05 05:17:43 PM PDT 24
Finished Jul 05 05:17:55 PM PDT 24
Peak memory 201792 kb
Host smart-a91d7ac6-8b37-4044-8b34-073972671022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018474136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3018474136
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1440018788
Short name T801
Test name
Test status
Simulation time 430556678 ps
CPU time 0.92 seconds
Started Jul 05 05:16:52 PM PDT 24
Finished Jul 05 05:16:55 PM PDT 24
Peak memory 201448 kb
Host smart-ee9ce294-eacd-40b7-a128-2afc562e9cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440018788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1440018788
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2864773996
Short name T908
Test name
Test status
Simulation time 360290771 ps
CPU time 0.85 seconds
Started Jul 05 05:16:55 PM PDT 24
Finished Jul 05 05:16:58 PM PDT 24
Peak memory 201424 kb
Host smart-478a6225-9b47-4b65-9d51-dc7e218ce78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864773996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2864773996
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3009974132
Short name T896
Test name
Test status
Simulation time 302350872 ps
CPU time 0.84 seconds
Started Jul 05 05:17:01 PM PDT 24
Finished Jul 05 05:17:04 PM PDT 24
Peak memory 201448 kb
Host smart-7716600f-d999-438e-bfc0-68b7370f0668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009974132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3009974132
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2654605159
Short name T838
Test name
Test status
Simulation time 509267614 ps
CPU time 0.76 seconds
Started Jul 05 05:17:01 PM PDT 24
Finished Jul 05 05:17:05 PM PDT 24
Peak memory 201392 kb
Host smart-a634441d-a8af-4c0b-8475-f6c763259f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654605159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2654605159
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.840589345
Short name T803
Test name
Test status
Simulation time 448757720 ps
CPU time 1.7 seconds
Started Jul 05 05:17:01 PM PDT 24
Finished Jul 05 05:17:05 PM PDT 24
Peak memory 201440 kb
Host smart-8129917a-bc47-458f-9eb8-eb30bb8141a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840589345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.840589345
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2486508547
Short name T841
Test name
Test status
Simulation time 503908042 ps
CPU time 1.87 seconds
Started Jul 05 05:17:00 PM PDT 24
Finished Jul 05 05:17:04 PM PDT 24
Peak memory 201440 kb
Host smart-d55813b3-1cbd-4026-9d94-0ae3b9e00c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486508547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2486508547
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4062263465
Short name T815
Test name
Test status
Simulation time 503065918 ps
CPU time 1.23 seconds
Started Jul 05 05:16:58 PM PDT 24
Finished Jul 05 05:17:02 PM PDT 24
Peak memory 201420 kb
Host smart-d109a0b5-bb1b-42f4-b996-9a6d3e28ad31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062263465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4062263465
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3711648128
Short name T825
Test name
Test status
Simulation time 441130354 ps
CPU time 0.85 seconds
Started Jul 05 05:17:02 PM PDT 24
Finished Jul 05 05:17:06 PM PDT 24
Peak memory 201332 kb
Host smart-9da3c4ee-e63e-4c8b-8733-f231d505cd22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711648128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3711648128
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3830230039
Short name T837
Test name
Test status
Simulation time 369263915 ps
CPU time 1.05 seconds
Started Jul 05 05:17:00 PM PDT 24
Finished Jul 05 05:17:03 PM PDT 24
Peak memory 201444 kb
Host smart-ac8641be-c7a6-4e1a-90f6-cbaf79bc67dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830230039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3830230039
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1084908634
Short name T868
Test name
Test status
Simulation time 430503546 ps
CPU time 0.86 seconds
Started Jul 05 05:17:00 PM PDT 24
Finished Jul 05 05:17:04 PM PDT 24
Peak memory 201424 kb
Host smart-86b1468c-8acc-42ce-8ce9-447e19c88bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084908634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1084908634
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2491354580
Short name T114
Test name
Test status
Simulation time 780805265 ps
CPU time 2.47 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201660 kb
Host smart-70d2d338-ebfc-494f-945a-729321b59a19
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491354580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2491354580
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2607872385
Short name T859
Test name
Test status
Simulation time 26588648234 ps
CPU time 64.3 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:17:46 PM PDT 24
Peak memory 201836 kb
Host smart-d8c74da6-b297-4b00-b6f9-65aedc85b7bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607872385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2607872385
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2037296133
Short name T907
Test name
Test status
Simulation time 825898307 ps
CPU time 1.14 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:16:42 PM PDT 24
Peak memory 201504 kb
Host smart-b6bd661f-54b4-48cd-bf42-142be4315e1e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037296133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2037296133
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3893766820
Short name T72
Test name
Test status
Simulation time 594538504 ps
CPU time 1.94 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 201580 kb
Host smart-32709bf7-03de-4905-b5bd-03184a4d135d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893766820 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3893766820
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2679637271
Short name T917
Test name
Test status
Simulation time 637575216 ps
CPU time 1.01 seconds
Started Jul 05 05:16:35 PM PDT 24
Finished Jul 05 05:16:37 PM PDT 24
Peak memory 201496 kb
Host smart-ee87ce56-3e28-4f5d-ba3b-89182be507ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679637271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2679637271
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3972730040
Short name T808
Test name
Test status
Simulation time 439349307 ps
CPU time 1.22 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:39 PM PDT 24
Peak memory 201420 kb
Host smart-11558dc1-6560-42e7-b646-6dc370d94cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972730040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3972730040
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2849448362
Short name T867
Test name
Test status
Simulation time 3126386759 ps
CPU time 1.39 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201800 kb
Host smart-c7b1ac38-1084-4399-ab8f-2573e7a1219d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849448362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2849448362
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1314840907
Short name T66
Test name
Test status
Simulation time 409056951 ps
CPU time 2.31 seconds
Started Jul 05 05:16:42 PM PDT 24
Finished Jul 05 05:16:44 PM PDT 24
Peak memory 201772 kb
Host smart-8170c13e-be12-4062-84b7-108893f24531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314840907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1314840907
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2944808631
Short name T80
Test name
Test status
Simulation time 8405137729 ps
CPU time 7.76 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:45 PM PDT 24
Peak memory 201852 kb
Host smart-aec2aa33-5efa-4f77-8563-cb074fb0e569
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944808631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2944808631
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3393065121
Short name T802
Test name
Test status
Simulation time 391600856 ps
CPU time 0.97 seconds
Started Jul 05 05:17:07 PM PDT 24
Finished Jul 05 05:17:09 PM PDT 24
Peak memory 201432 kb
Host smart-f63755d3-43c0-4a57-ba14-2c63e2d2b3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393065121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3393065121
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.858295743
Short name T821
Test name
Test status
Simulation time 344809699 ps
CPU time 1.39 seconds
Started Jul 05 05:16:57 PM PDT 24
Finished Jul 05 05:17:01 PM PDT 24
Peak memory 201344 kb
Host smart-0800d53c-e278-424e-a0d6-8f54bb1a296d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858295743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.858295743
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2739041190
Short name T901
Test name
Test status
Simulation time 359481159 ps
CPU time 1.45 seconds
Started Jul 05 05:17:00 PM PDT 24
Finished Jul 05 05:17:04 PM PDT 24
Peak memory 201420 kb
Host smart-e395087d-69ba-4d46-858c-3fcfc7c4caa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739041190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2739041190
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1722326182
Short name T807
Test name
Test status
Simulation time 517812422 ps
CPU time 1.71 seconds
Started Jul 05 05:17:01 PM PDT 24
Finished Jul 05 05:17:05 PM PDT 24
Peak memory 201416 kb
Host smart-53d96d77-62f5-4a0e-ab53-444c2fd4b640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722326182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1722326182
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.322940344
Short name T853
Test name
Test status
Simulation time 344459844 ps
CPU time 0.77 seconds
Started Jul 05 05:16:57 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 201432 kb
Host smart-5a41245a-d2c6-4a71-9d11-f06d66d7f42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322940344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.322940344
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3273201318
Short name T849
Test name
Test status
Simulation time 479962761 ps
CPU time 0.95 seconds
Started Jul 05 05:16:59 PM PDT 24
Finished Jul 05 05:17:03 PM PDT 24
Peak memory 201448 kb
Host smart-df28902e-f6c6-4bc8-a007-9f001c4d0d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273201318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3273201318
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4008619701
Short name T856
Test name
Test status
Simulation time 430839614 ps
CPU time 0.84 seconds
Started Jul 05 05:16:59 PM PDT 24
Finished Jul 05 05:17:02 PM PDT 24
Peak memory 201348 kb
Host smart-b599bc4a-abf5-40aa-864b-3215feeb2de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008619701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4008619701
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2037200228
Short name T834
Test name
Test status
Simulation time 393966729 ps
CPU time 1.53 seconds
Started Jul 05 05:16:56 PM PDT 24
Finished Jul 05 05:17:00 PM PDT 24
Peak memory 201348 kb
Host smart-eb89a3c7-4cbd-4655-96e6-2223ee3532a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037200228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2037200228
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.526061574
Short name T855
Test name
Test status
Simulation time 383112691 ps
CPU time 1.52 seconds
Started Jul 05 05:16:58 PM PDT 24
Finished Jul 05 05:17:03 PM PDT 24
Peak memory 201428 kb
Host smart-2b5eb970-b8aa-4321-9cb4-195adc7413ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526061574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.526061574
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2234243119
Short name T810
Test name
Test status
Simulation time 459842642 ps
CPU time 0.85 seconds
Started Jul 05 05:17:01 PM PDT 24
Finished Jul 05 05:17:05 PM PDT 24
Peak memory 201448 kb
Host smart-ceef81f3-d46c-43dd-ac55-3ba34d07fc74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234243119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2234243119
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4209687690
Short name T827
Test name
Test status
Simulation time 449700354 ps
CPU time 1.89 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:42 PM PDT 24
Peak memory 201500 kb
Host smart-82c948ff-5956-4229-b470-57809d6549f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209687690 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.4209687690
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.349644992
Short name T824
Test name
Test status
Simulation time 362552198 ps
CPU time 0.9 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:16:42 PM PDT 24
Peak memory 201396 kb
Host smart-b5cfeb4b-cf96-4d5b-87c3-01d0dd10c690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349644992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.349644992
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3074142758
Short name T800
Test name
Test status
Simulation time 547331959 ps
CPU time 0.82 seconds
Started Jul 05 05:16:36 PM PDT 24
Finished Jul 05 05:16:38 PM PDT 24
Peak memory 201356 kb
Host smart-08922c6c-dfb3-4cb8-b9c9-efc40eec3b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074142758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3074142758
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1095063211
Short name T892
Test name
Test status
Simulation time 1860889977 ps
CPU time 3.47 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:16:44 PM PDT 24
Peak memory 201508 kb
Host smart-bc7dc8df-fca6-4c2b-b664-dd7d762bc474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095063211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1095063211
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3746992533
Short name T878
Test name
Test status
Simulation time 575721640 ps
CPU time 2.15 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:43 PM PDT 24
Peak memory 201688 kb
Host smart-ee8b3a1b-adf3-450c-b5b4-d672cf92bc1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746992533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3746992533
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1924196947
Short name T337
Test name
Test status
Simulation time 8770872594 ps
CPU time 7.25 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 201900 kb
Host smart-5c693914-cadb-4bef-877b-29562e9380ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924196947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1924196947
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.546275865
Short name T860
Test name
Test status
Simulation time 712470337 ps
CPU time 0.94 seconds
Started Jul 05 05:16:37 PM PDT 24
Finished Jul 05 05:16:39 PM PDT 24
Peak memory 201572 kb
Host smart-cb832c63-3846-411f-8496-2a0e78ed5d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546275865 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.546275865
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1923657334
Short name T126
Test name
Test status
Simulation time 340765540 ps
CPU time 1.06 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201516 kb
Host smart-ce0b080c-df75-41f8-ac6f-e28c43935c1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923657334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1923657334
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1313381630
Short name T818
Test name
Test status
Simulation time 514033485 ps
CPU time 1.73 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201356 kb
Host smart-76d161a5-bdfc-42d6-a7da-f46fbd5af5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313381630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1313381630
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1680306492
Short name T904
Test name
Test status
Simulation time 2559752516 ps
CPU time 2.73 seconds
Started Jul 05 05:16:36 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 201808 kb
Host smart-955c31df-5dfa-45a5-bd0f-832d637c949a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680306492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1680306492
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1956836979
Short name T77
Test name
Test status
Simulation time 585118825 ps
CPU time 2.22 seconds
Started Jul 05 05:16:49 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 217564 kb
Host smart-a8f9a83f-f20b-4c54-8f59-8cf411d53a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956836979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1956836979
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2610885546
Short name T79
Test name
Test status
Simulation time 4463762476 ps
CPU time 4.09 seconds
Started Jul 05 05:16:40 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 201748 kb
Host smart-e3c1d717-4c87-41ea-95d7-582a8be321ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610885546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2610885546
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4161846746
Short name T866
Test name
Test status
Simulation time 545371715 ps
CPU time 1.27 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 201596 kb
Host smart-95744965-e087-4cef-a584-580463d0affe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161846746 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4161846746
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.477303546
Short name T823
Test name
Test status
Simulation time 658548556 ps
CPU time 0.72 seconds
Started Jul 05 05:16:41 PM PDT 24
Finished Jul 05 05:16:42 PM PDT 24
Peak memory 201348 kb
Host smart-60aac9da-c1c5-4501-91ce-20d52e41bbdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477303546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.477303546
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.797074930
Short name T862
Test name
Test status
Simulation time 2303706161 ps
CPU time 1.92 seconds
Started Jul 05 05:16:38 PM PDT 24
Finished Jul 05 05:16:41 PM PDT 24
Peak memory 201632 kb
Host smart-1f6eb629-1e1d-412c-8266-8b0625f1c887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797074930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.797074930
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2461659889
Short name T870
Test name
Test status
Simulation time 433427466 ps
CPU time 2.13 seconds
Started Jul 05 05:16:39 PM PDT 24
Finished Jul 05 05:16:43 PM PDT 24
Peak memory 201664 kb
Host smart-c28964f9-09aa-4c3f-a780-ca951967c7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461659889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2461659889
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.828272792
Short name T73
Test name
Test status
Simulation time 7470524286 ps
CPU time 18.15 seconds
Started Jul 05 05:16:42 PM PDT 24
Finished Jul 05 05:17:01 PM PDT 24
Peak memory 201736 kb
Host smart-fb0ea3f2-b2bc-4e61-b355-0dab0b9a952b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828272792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.828272792
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3718575177
Short name T71
Test name
Test status
Simulation time 541341180 ps
CPU time 2.07 seconds
Started Jul 05 05:16:43 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 201508 kb
Host smart-1a6a1523-a83b-452e-b64b-07d52d4d15df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718575177 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3718575177
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4184555718
Short name T119
Test name
Test status
Simulation time 540074212 ps
CPU time 1.99 seconds
Started Jul 05 05:16:50 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201484 kb
Host smart-1582695f-f75d-4958-ac22-974bdcf103e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184555718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4184555718
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3935178467
Short name T805
Test name
Test status
Simulation time 491238925 ps
CPU time 0.74 seconds
Started Jul 05 05:16:44 PM PDT 24
Finished Jul 05 05:16:45 PM PDT 24
Peak memory 201380 kb
Host smart-118670ff-f4eb-4517-b611-d56a776226e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935178467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3935178467
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2809591068
Short name T50
Test name
Test status
Simulation time 4022442619 ps
CPU time 6.96 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:53 PM PDT 24
Peak memory 201760 kb
Host smart-316ca729-2e20-41d7-aab6-95691337849d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809591068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2809591068
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2023015809
Short name T831
Test name
Test status
Simulation time 585404960 ps
CPU time 1.97 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:48 PM PDT 24
Peak memory 210968 kb
Host smart-c361adf7-4a97-4c05-ae3a-9108902fa3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023015809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2023015809
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2269510158
Short name T54
Test name
Test status
Simulation time 8708688629 ps
CPU time 4.48 seconds
Started Jul 05 05:16:47 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201856 kb
Host smart-18b84687-871b-4983-92be-748f255efaae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269510158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2269510158
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3613043333
Short name T872
Test name
Test status
Simulation time 545700073 ps
CPU time 2.03 seconds
Started Jul 05 05:16:47 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 201476 kb
Host smart-05c7f758-e289-4aaa-bd5e-e3fbb725f314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613043333 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3613043333
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2521143423
Short name T125
Test name
Test status
Simulation time 472749861 ps
CPU time 1.02 seconds
Started Jul 05 05:16:45 PM PDT 24
Finished Jul 05 05:16:47 PM PDT 24
Peak memory 201440 kb
Host smart-3f0c00b2-8cef-4153-a792-77d4439f2c68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521143423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2521143423
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3450644651
Short name T843
Test name
Test status
Simulation time 323685217 ps
CPU time 1.36 seconds
Started Jul 05 05:16:47 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 201424 kb
Host smart-27d34830-b4cc-4d05-af2e-17f41908e549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450644651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3450644651
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.101906096
Short name T848
Test name
Test status
Simulation time 2089423428 ps
CPU time 5.5 seconds
Started Jul 05 05:16:49 PM PDT 24
Finished Jul 05 05:16:56 PM PDT 24
Peak memory 201492 kb
Host smart-372365d9-746a-4e0d-a303-33f2fb217afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101906096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.101906096
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1079014597
Short name T74
Test name
Test status
Simulation time 553058680 ps
CPU time 2.64 seconds
Started Jul 05 05:16:48 PM PDT 24
Finished Jul 05 05:16:52 PM PDT 24
Peak memory 201748 kb
Host smart-c1ce9bff-d71a-4980-8d34-09efeda432a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079014597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1079014597
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1492278482
Short name T60
Test name
Test status
Simulation time 4673895400 ps
CPU time 2.68 seconds
Started Jul 05 05:16:47 PM PDT 24
Finished Jul 05 05:16:51 PM PDT 24
Peak memory 201888 kb
Host smart-ea682497-f2c7-4604-844b-a50b374ba1f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492278482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1492278482
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4238807653
Short name T599
Test name
Test status
Simulation time 427519906 ps
CPU time 0.82 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 201676 kb
Host smart-4538475d-1af3-4cde-9e96-2ac9bcc7324a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238807653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4238807653
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3948099551
Short name T594
Test name
Test status
Simulation time 328373447949 ps
CPU time 791.87 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 06:13:00 PM PDT 24
Peak memory 201916 kb
Host smart-d8006016-a5d3-4331-9549-30b878847575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948099551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3948099551
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3239773767
Short name T355
Test name
Test status
Simulation time 164073008146 ps
CPU time 202.05 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 06:03:15 PM PDT 24
Peak memory 201908 kb
Host smart-cf666bd6-c4de-4db3-9d13-1d51e153f939
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239773767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3239773767
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.33410331
Short name T573
Test name
Test status
Simulation time 496592757735 ps
CPU time 1096.2 seconds
Started Jul 05 05:59:53 PM PDT 24
Finished Jul 05 06:18:10 PM PDT 24
Peak memory 201976 kb
Host smart-389e7593-9b95-4ca5-8511-a776c3437d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33410331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.33410331
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3063818871
Short name T88
Test name
Test status
Simulation time 166219177146 ps
CPU time 341.91 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 06:05:35 PM PDT 24
Peak memory 201916 kb
Host smart-2a14c9b7-42f9-4989-b536-e73bdf440296
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063818871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3063818871
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3949840130
Short name T687
Test name
Test status
Simulation time 345180273874 ps
CPU time 348.82 seconds
Started Jul 05 06:00:12 PM PDT 24
Finished Jul 05 06:06:01 PM PDT 24
Peak memory 201940 kb
Host smart-d3bccebb-a19b-486d-abb2-d7b7ecb640d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949840130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3949840130
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4058892394
Short name T105
Test name
Test status
Simulation time 404446468627 ps
CPU time 243.78 seconds
Started Jul 05 06:00:00 PM PDT 24
Finished Jul 05 06:04:04 PM PDT 24
Peak memory 201880 kb
Host smart-6e68f0ee-4396-4747-81cf-e91862b7aaa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058892394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4058892394
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3584948866
Short name T403
Test name
Test status
Simulation time 44856831577 ps
CPU time 6.96 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:53 PM PDT 24
Peak memory 201720 kb
Host smart-8e6ec9d0-6b74-429f-8699-49f2e8e5aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584948866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3584948866
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4187641151
Short name T447
Test name
Test status
Simulation time 5096251330 ps
CPU time 3.66 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 05:59:54 PM PDT 24
Peak memory 201724 kb
Host smart-db09f135-b523-4424-a567-ab982afcdd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187641151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4187641151
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.60337118
Short name T84
Test name
Test status
Simulation time 4057926304 ps
CPU time 2.31 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 217188 kb
Host smart-cc7739a5-db4c-4309-b364-1bf97a1ab26c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60337118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.60337118
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2668015355
Short name T435
Test name
Test status
Simulation time 6105357982 ps
CPU time 2.18 seconds
Started Jul 05 05:59:43 PM PDT 24
Finished Jul 05 05:59:46 PM PDT 24
Peak memory 201660 kb
Host smart-9c86896f-38f3-42a8-aa31-3e7bc01bbd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668015355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2668015355
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3648368408
Short name T696
Test name
Test status
Simulation time 337273731323 ps
CPU time 389.39 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 06:06:14 PM PDT 24
Peak memory 212064 kb
Host smart-b3ad4dd1-4837-46e1-ac84-ae2b6d416a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648368408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3648368408
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2217365495
Short name T17
Test name
Test status
Simulation time 80355071847 ps
CPU time 78.32 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:01:11 PM PDT 24
Peak memory 202048 kb
Host smart-6f67cd26-095e-4627-885c-09345181c812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217365495 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2217365495
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3258066327
Short name T766
Test name
Test status
Simulation time 329610638 ps
CPU time 0.9 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:48 PM PDT 24
Peak memory 201668 kb
Host smart-23c288e3-e7b9-4ddc-b1e8-ec6dd3e5e703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258066327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3258066327
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.769443164
Short name T783
Test name
Test status
Simulation time 341422028657 ps
CPU time 753.36 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 06:12:20 PM PDT 24
Peak memory 201984 kb
Host smart-3164abb9-c144-43c7-9237-1a3aaa549540
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769443164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.769443164
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3069644757
Short name T178
Test name
Test status
Simulation time 364002663863 ps
CPU time 217.03 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:03:30 PM PDT 24
Peak memory 201916 kb
Host smart-4df693c8-2d08-464b-a09b-8091a3552ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069644757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3069644757
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2918225559
Short name T764
Test name
Test status
Simulation time 336696388034 ps
CPU time 805.74 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:13:17 PM PDT 24
Peak memory 201904 kb
Host smart-f91cdcc3-be80-4e99-87b1-249684c5d484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918225559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2918225559
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.104046836
Short name T644
Test name
Test status
Simulation time 163300712829 ps
CPU time 99.19 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 06:01:25 PM PDT 24
Peak memory 201880 kb
Host smart-8addba08-22d3-46c5-b4fd-5946b4402023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=104046836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.104046836
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3509755220
Short name T258
Test name
Test status
Simulation time 490377274119 ps
CPU time 1129.08 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:18:40 PM PDT 24
Peak memory 201988 kb
Host smart-542933f2-388b-45e7-842c-b0c27fd6b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509755220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3509755220
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3556731646
Short name T415
Test name
Test status
Simulation time 162605163157 ps
CPU time 102.25 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 06:01:30 PM PDT 24
Peak memory 201872 kb
Host smart-3cecd503-e942-4390-812c-77b05b9f8f09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556731646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3556731646
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2300225688
Short name T317
Test name
Test status
Simulation time 382850198771 ps
CPU time 394.78 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 06:06:22 PM PDT 24
Peak memory 201952 kb
Host smart-76a53051-2e18-45e2-b278-b326238b94db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300225688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2300225688
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2690971932
Short name T544
Test name
Test status
Simulation time 602414213248 ps
CPU time 1357.05 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:22:28 PM PDT 24
Peak memory 201820 kb
Host smart-9025844c-1373-4179-9a0f-ba69980822b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690971932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2690971932
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.68210633
Short name T422
Test name
Test status
Simulation time 125709354509 ps
CPU time 460.31 seconds
Started Jul 05 05:59:53 PM PDT 24
Finished Jul 05 06:07:34 PM PDT 24
Peak memory 202220 kb
Host smart-648723b3-94eb-479a-bb3f-0a28dfcc3c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68210633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.68210633
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2360016007
Short name T504
Test name
Test status
Simulation time 25682207510 ps
CPU time 51.31 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 06:00:40 PM PDT 24
Peak memory 201728 kb
Host smart-04d91a4f-8611-4e9b-97d2-12d2c2d7e5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360016007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2360016007
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4204258508
Short name T704
Test name
Test status
Simulation time 2816427475 ps
CPU time 5.32 seconds
Started Jul 05 05:59:39 PM PDT 24
Finished Jul 05 05:59:45 PM PDT 24
Peak memory 201708 kb
Host smart-50e29193-86bc-437b-b96f-8b210a2d40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204258508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4204258508
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2716182384
Short name T5
Test name
Test status
Simulation time 5650390211 ps
CPU time 3.59 seconds
Started Jul 05 06:00:01 PM PDT 24
Finished Jul 05 06:00:05 PM PDT 24
Peak memory 201640 kb
Host smart-0fb0d7bf-f6be-416e-829f-48df7f9c9687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716182384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2716182384
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2357976075
Short name T678
Test name
Test status
Simulation time 329956112374 ps
CPU time 579.06 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:09:31 PM PDT 24
Peak memory 202276 kb
Host smart-3ca9df7e-024a-4a71-8516-bf3987329e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357976075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2357976075
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1394656230
Short name T357
Test name
Test status
Simulation time 31795168217 ps
CPU time 76.3 seconds
Started Jul 05 05:59:44 PM PDT 24
Finished Jul 05 06:01:01 PM PDT 24
Peak memory 210584 kb
Host smart-175d4b36-dc25-4518-b3a1-4482c1e3d5e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394656230 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1394656230
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3537557949
Short name T473
Test name
Test status
Simulation time 419889871 ps
CPU time 0.74 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:00:16 PM PDT 24
Peak memory 201652 kb
Host smart-0c398432-46a8-447f-a194-2ef25712e10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537557949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3537557949
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3600022856
Short name T650
Test name
Test status
Simulation time 327531370235 ps
CPU time 173.66 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:03:10 PM PDT 24
Peak memory 201928 kb
Host smart-5bb77d50-9cf4-4c60-8c94-e6acee3e1867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600022856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3600022856
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2621426966
Short name T397
Test name
Test status
Simulation time 330029866786 ps
CPU time 151.07 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:02:48 PM PDT 24
Peak memory 201892 kb
Host smart-cca4eec1-0539-4f15-8ec7-4c0a32616ac8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621426966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2621426966
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1486453413
Short name T460
Test name
Test status
Simulation time 162724659957 ps
CPU time 355.99 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:06:10 PM PDT 24
Peak memory 201724 kb
Host smart-422dff35-a054-46db-a6bc-490fed3e7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486453413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1486453413
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1197216084
Short name T718
Test name
Test status
Simulation time 485223081912 ps
CPU time 1007.32 seconds
Started Jul 05 06:00:06 PM PDT 24
Finished Jul 05 06:16:54 PM PDT 24
Peak memory 201976 kb
Host smart-70350763-d596-42a6-8aa9-d45bcb56ff1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197216084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1197216084
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1720094514
Short name T309
Test name
Test status
Simulation time 186663163064 ps
CPU time 420.67 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:07:17 PM PDT 24
Peak memory 201976 kb
Host smart-9dfcbbbe-7732-464b-a0a5-3bb9a1a2ecb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720094514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1720094514
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3057874530
Short name T688
Test name
Test status
Simulation time 401409220382 ps
CPU time 234.56 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:04:10 PM PDT 24
Peak memory 201916 kb
Host smart-2140e238-14fe-48b4-b657-8825e6ea4e30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057874530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3057874530
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.973618102
Short name T470
Test name
Test status
Simulation time 38306081874 ps
CPU time 67.5 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:01:17 PM PDT 24
Peak memory 201704 kb
Host smart-0eb0b226-2301-4e81-9317-e3b291c497dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973618102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.973618102
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3196597998
Short name T602
Test name
Test status
Simulation time 4835533042 ps
CPU time 7.11 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:00:23 PM PDT 24
Peak memory 201704 kb
Host smart-84bb2468-defc-4399-99d7-787198ea0baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196597998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3196597998
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3621301738
Short name T387
Test name
Test status
Simulation time 5761283126 ps
CPU time 14.08 seconds
Started Jul 05 06:00:11 PM PDT 24
Finished Jul 05 06:00:26 PM PDT 24
Peak memory 201712 kb
Host smart-e1f98ec4-dde3-4a7b-94fb-ac3ee0497b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621301738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3621301738
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.291667156
Short name T97
Test name
Test status
Simulation time 174376784704 ps
CPU time 390 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:06:46 PM PDT 24
Peak memory 201852 kb
Host smart-cfe58840-d794-40d9-ab0a-ba6ca552f7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291667156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
291667156
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.67260407
Short name T22
Test name
Test status
Simulation time 244135381684 ps
CPU time 98.38 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:01:58 PM PDT 24
Peak memory 212896 kb
Host smart-97b89967-d8db-409b-9398-30044bcabd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67260407 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.67260407
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1232767837
Short name T768
Test name
Test status
Simulation time 342965215 ps
CPU time 0.82 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:00:09 PM PDT 24
Peak memory 201584 kb
Host smart-0187123b-9342-4211-8547-bc73e78132ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232767837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1232767837
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.4016708655
Short name T652
Test name
Test status
Simulation time 163794166079 ps
CPU time 93.2 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:01:54 PM PDT 24
Peak memory 201932 kb
Host smart-e095d1a3-3cf0-4235-b135-d8f854982819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016708655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.4016708655
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.238165114
Short name T477
Test name
Test status
Simulation time 331697754720 ps
CPU time 715.3 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:12:04 PM PDT 24
Peak memory 201896 kb
Host smart-9ab22543-94bf-44c7-bfe8-acac46123d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238165114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.238165114
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1569267694
Short name T399
Test name
Test status
Simulation time 490439392210 ps
CPU time 157.48 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:02:58 PM PDT 24
Peak memory 201848 kb
Host smart-cf736731-9e58-4c2b-bdd4-f149df606dbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569267694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1569267694
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3785656879
Short name T375
Test name
Test status
Simulation time 323457302794 ps
CPU time 383.97 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:06:39 PM PDT 24
Peak memory 201916 kb
Host smart-271ee7e8-54b0-44aa-a78e-4aa9837d2b4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785656879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3785656879
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2806305719
Short name T182
Test name
Test status
Simulation time 338769247381 ps
CPU time 194.53 seconds
Started Jul 05 06:00:19 PM PDT 24
Finished Jul 05 06:03:34 PM PDT 24
Peak memory 201928 kb
Host smart-443cd3ee-7d90-4fc7-88a3-02b4e2958549
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806305719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2806305719
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1380552362
Short name T530
Test name
Test status
Simulation time 605920542364 ps
CPU time 1439.79 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:24:19 PM PDT 24
Peak memory 201900 kb
Host smart-b59a5d09-61fb-4b7f-a724-da00bdca21bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380552362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1380552362
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3489509974
Short name T596
Test name
Test status
Simulation time 76164164272 ps
CPU time 281.31 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:04:57 PM PDT 24
Peak memory 202228 kb
Host smart-9a53cd7c-9145-434b-96cf-5b205b8b40f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489509974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3489509974
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.104254775
Short name T46
Test name
Test status
Simulation time 33037380931 ps
CPU time 39.19 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:00:54 PM PDT 24
Peak memory 201720 kb
Host smart-122e6d3f-072e-4141-89f6-df2aa3c73b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104254775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.104254775
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1559670701
Short name T543
Test name
Test status
Simulation time 2948938176 ps
CPU time 7.34 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:00:21 PM PDT 24
Peak memory 201732 kb
Host smart-1242a92a-7ee7-402e-ace4-cd08895d191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559670701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1559670701
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1008166418
Short name T367
Test name
Test status
Simulation time 5581197108 ps
CPU time 12.62 seconds
Started Jul 05 06:00:19 PM PDT 24
Finished Jul 05 06:00:32 PM PDT 24
Peak memory 201684 kb
Host smart-9d0a7be1-bcd8-4bbc-920f-813c55bf8b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008166418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1008166418
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.394369952
Short name T325
Test name
Test status
Simulation time 244189194163 ps
CPU time 132.63 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:02:29 PM PDT 24
Peak memory 201892 kb
Host smart-af091076-5890-4735-90b4-49288691cdd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394369952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
394369952
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2055254900
Short name T91
Test name
Test status
Simulation time 31897870759 ps
CPU time 38.29 seconds
Started Jul 05 06:00:04 PM PDT 24
Finished Jul 05 06:00:43 PM PDT 24
Peak memory 210236 kb
Host smart-4c330a4c-cf13-469d-9fd7-52e5732ba4c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055254900 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2055254900
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2352078065
Short name T639
Test name
Test status
Simulation time 443949907 ps
CPU time 0.86 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:00:14 PM PDT 24
Peak memory 201672 kb
Host smart-9dc4978a-67ef-4699-99bb-e002f5c0b53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352078065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2352078065
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3688857371
Short name T254
Test name
Test status
Simulation time 508207656465 ps
CPU time 233.17 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:04:10 PM PDT 24
Peak memory 201968 kb
Host smart-61117ace-2873-4d89-b50a-55bb4f536d51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688857371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3688857371
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.717853913
Short name T195
Test name
Test status
Simulation time 159741983175 ps
CPU time 88.2 seconds
Started Jul 05 06:00:19 PM PDT 24
Finished Jul 05 06:01:48 PM PDT 24
Peak memory 201920 kb
Host smart-6abaf40d-35b0-4824-b21a-6be13eb78c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717853913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.717853913
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2543408915
Short name T100
Test name
Test status
Simulation time 496860837029 ps
CPU time 93.64 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:01:58 PM PDT 24
Peak memory 201916 kb
Host smart-c48899cc-fe3c-465d-8b39-99062a99783f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543408915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2543408915
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.781267805
Short name T176
Test name
Test status
Simulation time 485764035633 ps
CPU time 602.9 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:10:21 PM PDT 24
Peak memory 201968 kb
Host smart-bffa6be0-b357-49d2-8365-58c979d0a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781267805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.781267805
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2196586369
Short name T430
Test name
Test status
Simulation time 492714694567 ps
CPU time 130.54 seconds
Started Jul 05 06:00:12 PM PDT 24
Finished Jul 05 06:02:23 PM PDT 24
Peak memory 201920 kb
Host smart-4aee01f0-738d-4eb1-aa4b-4f9eb8420811
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196586369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2196586369
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3092153900
Short name T533
Test name
Test status
Simulation time 175967786149 ps
CPU time 423.49 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:07:22 PM PDT 24
Peak memory 201932 kb
Host smart-c3ee9e5a-6118-4a66-8f5a-11a707240a97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092153900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3092153900
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1159627829
Short name T564
Test name
Test status
Simulation time 604648114081 ps
CPU time 1219.37 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:20:37 PM PDT 24
Peak memory 201904 kb
Host smart-289aa280-7ba0-4f1e-b765-9edd681947dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159627829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1159627829
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3913579969
Short name T513
Test name
Test status
Simulation time 111009480802 ps
CPU time 416.38 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:07:10 PM PDT 24
Peak memory 201984 kb
Host smart-51ea6c66-39c6-4d1f-aa1f-d50f09d99100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913579969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3913579969
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4199860310
Short name T595
Test name
Test status
Simulation time 22936534543 ps
CPU time 51.18 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:00:59 PM PDT 24
Peak memory 201704 kb
Host smart-5e26b6a7-e616-44a0-9f23-9b013db055a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199860310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4199860310
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3111245562
Short name T706
Test name
Test status
Simulation time 3302736580 ps
CPU time 8.07 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:00:27 PM PDT 24
Peak memory 201624 kb
Host smart-269c57ff-f5c1-40f3-8c2b-4cfea5eba264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111245562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3111245562
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1441551674
Short name T709
Test name
Test status
Simulation time 5698932834 ps
CPU time 13.45 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:00:31 PM PDT 24
Peak memory 201636 kb
Host smart-cbfc1a89-dfa1-45fe-b288-37a0b99bd5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441551674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1441551674
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1146573508
Short name T694
Test name
Test status
Simulation time 193575702323 ps
CPU time 111.87 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:02:08 PM PDT 24
Peak memory 201908 kb
Host smart-cccd91a5-9b27-4a14-b3f4-706691623f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146573508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1146573508
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1596516428
Short name T200
Test name
Test status
Simulation time 72313862859 ps
CPU time 172.46 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:03:06 PM PDT 24
Peak memory 218624 kb
Host smart-4444173d-2936-4c44-a30c-14166422f075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596516428 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1596516428
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2898054457
Short name T414
Test name
Test status
Simulation time 446799723 ps
CPU time 1.37 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:00:19 PM PDT 24
Peak memory 201628 kb
Host smart-2b0a46f9-f71b-4d04-b986-e7ec881e98f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898054457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2898054457
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1872631406
Short name T582
Test name
Test status
Simulation time 181916875550 ps
CPU time 396.12 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:07:04 PM PDT 24
Peak memory 201944 kb
Host smart-c734000d-e484-48ba-a7fa-f75f76d18031
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872631406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1872631406
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2381089448
Short name T249
Test name
Test status
Simulation time 166156053255 ps
CPU time 400 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:06:56 PM PDT 24
Peak memory 201848 kb
Host smart-b5e3fde7-cbf9-4b5b-8373-17abec2d1487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381089448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2381089448
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3564746336
Short name T103
Test name
Test status
Simulation time 332646024312 ps
CPU time 197.51 seconds
Started Jul 05 06:00:19 PM PDT 24
Finished Jul 05 06:03:38 PM PDT 24
Peak memory 201900 kb
Host smart-074fefe6-19ea-45ec-ad19-7450e8093c08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564746336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3564746336
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2929857134
Short name T614
Test name
Test status
Simulation time 329448167226 ps
CPU time 367.36 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:06:23 PM PDT 24
Peak memory 201912 kb
Host smart-f2baf704-a164-44b2-a180-e58638ffed63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929857134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2929857134
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3704453425
Short name T436
Test name
Test status
Simulation time 496508149980 ps
CPU time 521 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 201852 kb
Host smart-d46cfca7-e330-431a-9a42-6ff3dcfbe201
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704453425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3704453425
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2368915604
Short name T547
Test name
Test status
Simulation time 368281636427 ps
CPU time 402.09 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:07:10 PM PDT 24
Peak memory 201924 kb
Host smart-a5d04389-c834-4182-9a55-59185ea8d111
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368915604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2368915604
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3239209438
Short name T159
Test name
Test status
Simulation time 61902631904 ps
CPU time 272.01 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:04:58 PM PDT 24
Peak memory 202148 kb
Host smart-c54c1317-06bb-461b-beb3-e8efa5c86fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239209438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3239209438
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3031201208
Short name T797
Test name
Test status
Simulation time 40049229093 ps
CPU time 82.34 seconds
Started Jul 05 06:00:11 PM PDT 24
Finished Jul 05 06:01:35 PM PDT 24
Peak memory 201700 kb
Host smart-3030a7b5-d57c-40a4-9b0e-f555936ddc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031201208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3031201208
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.55259382
Short name T487
Test name
Test status
Simulation time 5178090141 ps
CPU time 11.6 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:00:30 PM PDT 24
Peak memory 201700 kb
Host smart-189b503d-7ddc-4c19-837b-a8ecab5ab10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55259382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.55259382
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3712487784
Short name T601
Test name
Test status
Simulation time 5920276543 ps
CPU time 14.49 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:00:30 PM PDT 24
Peak memory 201964 kb
Host smart-fd46bb67-42be-4ca5-9e86-3f80558067d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712487784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3712487784
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.68198767
Short name T605
Test name
Test status
Simulation time 11658831300 ps
CPU time 29.57 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:00:51 PM PDT 24
Peak memory 210572 kb
Host smart-053791c2-51d9-4623-858d-f773f76d208b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68198767 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.68198767
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.203077169
Short name T683
Test name
Test status
Simulation time 496490574 ps
CPU time 1.67 seconds
Started Jul 05 06:00:22 PM PDT 24
Finished Jul 05 06:00:24 PM PDT 24
Peak memory 201660 kb
Host smart-000fee0c-1653-4227-bfd3-2e7cf3354d09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203077169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.203077169
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1993550776
Short name T315
Test name
Test status
Simulation time 500804147608 ps
CPU time 563.65 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:09:43 PM PDT 24
Peak memory 201976 kb
Host smart-ff4ca3bf-07d6-43c9-9117-7700305953e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993550776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1993550776
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3982674404
Short name T453
Test name
Test status
Simulation time 494061593017 ps
CPU time 136.16 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:02:39 PM PDT 24
Peak memory 201804 kb
Host smart-de588d29-d999-4dbd-84a3-bfd47b8f5a71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982674404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3982674404
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1536698249
Short name T763
Test name
Test status
Simulation time 484388519585 ps
CPU time 247.51 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:04:42 PM PDT 24
Peak memory 201900 kb
Host smart-446e5658-7c18-41b7-8d8f-c581bd8614f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536698249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1536698249
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.378705455
Short name T732
Test name
Test status
Simulation time 493489175965 ps
CPU time 543.07 seconds
Started Jul 05 06:00:11 PM PDT 24
Finished Jul 05 06:09:14 PM PDT 24
Peak memory 201884 kb
Host smart-0ab29862-4c17-472e-8e93-0651daaa8a63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=378705455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.378705455
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2536596714
Short name T263
Test name
Test status
Simulation time 172558753571 ps
CPU time 51.06 seconds
Started Jul 05 06:00:33 PM PDT 24
Finished Jul 05 06:01:25 PM PDT 24
Peak memory 201936 kb
Host smart-a8eeadec-d4f1-40e2-a2bb-a6de79d943d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536596714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2536596714
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.961522505
Short name T722
Test name
Test status
Simulation time 400600442067 ps
CPU time 929.33 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:15:48 PM PDT 24
Peak memory 201832 kb
Host smart-ab7310c2-802c-432a-80e5-1676bce5df8a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961522505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.961522505
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.287963276
Short name T158
Test name
Test status
Simulation time 136249797562 ps
CPU time 449.44 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:07:51 PM PDT 24
Peak memory 202280 kb
Host smart-ad3fd3e6-5108-466e-bc12-8c859625df69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287963276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.287963276
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.822184745
Short name T99
Test name
Test status
Simulation time 29271198139 ps
CPU time 37.37 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:01:04 PM PDT 24
Peak memory 201720 kb
Host smart-11c4e4ec-54fd-4135-9146-7eb525f5bb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822184745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.822184745
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3780469936
Short name T790
Test name
Test status
Simulation time 3817111833 ps
CPU time 2.4 seconds
Started Jul 05 06:00:19 PM PDT 24
Finished Jul 05 06:00:22 PM PDT 24
Peak memory 201680 kb
Host smart-1cfd5d86-93e8-4977-8cbb-05231a2de731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780469936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3780469936
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.91612644
Short name T699
Test name
Test status
Simulation time 6010653886 ps
CPU time 4.39 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:00:19 PM PDT 24
Peak memory 201684 kb
Host smart-d5f1d0f2-7943-43fb-b161-287363532780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91612644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.91612644
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2783374602
Short name T406
Test name
Test status
Simulation time 14209537639 ps
CPU time 15.98 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:00:42 PM PDT 24
Peak memory 201724 kb
Host smart-7f29f149-b872-490d-add6-64fc213565cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783374602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2783374602
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3195002674
Short name T35
Test name
Test status
Simulation time 69524226515 ps
CPU time 38.46 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:00:57 PM PDT 24
Peak memory 202068 kb
Host smart-e18276b8-4809-4e41-a2f9-4c12564c0534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195002674 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3195002674
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1722398224
Short name T617
Test name
Test status
Simulation time 453974304 ps
CPU time 1.55 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:00:26 PM PDT 24
Peak memory 201672 kb
Host smart-7a31735e-772d-44ce-a4f2-0e6e75cdb487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722398224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1722398224
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1290927217
Short name T169
Test name
Test status
Simulation time 326464312123 ps
CPU time 758.75 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:12:59 PM PDT 24
Peak memory 201624 kb
Host smart-41ea5920-5566-4bef-801f-26379c23ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290927217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1290927217
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1162777761
Short name T705
Test name
Test status
Simulation time 167556384025 ps
CPU time 204.2 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:03:41 PM PDT 24
Peak memory 201916 kb
Host smart-41aaa235-b36d-492e-bdb1-69b4722976bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162777761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1162777761
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2127330894
Short name T779
Test name
Test status
Simulation time 159138751107 ps
CPU time 350.45 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:06:08 PM PDT 24
Peak memory 201892 kb
Host smart-c5bb20d1-9fd8-423c-8760-c2fac1da8f96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127330894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2127330894
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1025344922
Short name T609
Test name
Test status
Simulation time 162563067937 ps
CPU time 352.4 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:06:31 PM PDT 24
Peak memory 201888 kb
Host smart-c63c1f67-8fe0-45b6-8c41-98d8fc8bbba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025344922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1025344922
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3735384293
Short name T637
Test name
Test status
Simulation time 329714361719 ps
CPU time 706.89 seconds
Started Jul 05 06:00:22 PM PDT 24
Finished Jul 05 06:12:09 PM PDT 24
Peak memory 201872 kb
Host smart-0f3ea50f-17a8-4495-9e74-ea60b39527d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735384293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3735384293
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.542068072
Short name T256
Test name
Test status
Simulation time 356688300969 ps
CPU time 356.59 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:06:18 PM PDT 24
Peak memory 201924 kb
Host smart-6a63e695-4410-486a-bdfd-5610b53acb9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542068072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.542068072
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3372488764
Short name T239
Test name
Test status
Simulation time 405434442719 ps
CPU time 223.65 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:04:09 PM PDT 24
Peak memory 201816 kb
Host smart-7f7e06b8-268b-4e24-b3ba-7fd6e2c77c64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372488764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3372488764
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.99515491
Short name T586
Test name
Test status
Simulation time 80273722577 ps
CPU time 383 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:06:38 PM PDT 24
Peak memory 202244 kb
Host smart-0daec2bd-4add-4939-86f0-2653bf823099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99515491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.99515491
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2102480468
Short name T588
Test name
Test status
Simulation time 39192070862 ps
CPU time 21.62 seconds
Started Jul 05 06:00:19 PM PDT 24
Finished Jul 05 06:00:41 PM PDT 24
Peak memory 201720 kb
Host smart-f254545a-8a70-42af-99cf-5fa150df3dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102480468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2102480468
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2056430830
Short name T554
Test name
Test status
Simulation time 4443129485 ps
CPU time 10.17 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:00:34 PM PDT 24
Peak memory 201704 kb
Host smart-5f862816-f2b7-4f12-ad58-2af27be97f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056430830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2056430830
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1034950642
Short name T669
Test name
Test status
Simulation time 5987465257 ps
CPU time 12.31 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:00:31 PM PDT 24
Peak memory 201740 kb
Host smart-3e96ef5c-b6c7-4057-bdb6-40fc828bfe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034950642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1034950642
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3707340147
Short name T626
Test name
Test status
Simulation time 217809053842 ps
CPU time 365.92 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:06:31 PM PDT 24
Peak memory 218324 kb
Host smart-2ae31565-3529-4be6-a6ab-7e0f871933f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707340147 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3707340147
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3436565489
Short name T615
Test name
Test status
Simulation time 362253858 ps
CPU time 0.74 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:00:28 PM PDT 24
Peak memory 201668 kb
Host smart-889822ec-7ae5-4ba8-bcc4-cb180fc84671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436565489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3436565489
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3296727959
Short name T245
Test name
Test status
Simulation time 507078032628 ps
CPU time 347.52 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:06:08 PM PDT 24
Peak memory 201880 kb
Host smart-54adad43-524a-46f9-9604-939aa5646f68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296727959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3296727959
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1255913120
Short name T310
Test name
Test status
Simulation time 342054399846 ps
CPU time 774.05 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:13:15 PM PDT 24
Peak memory 201872 kb
Host smart-0612f04c-63be-44cb-a322-4d0c188940e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255913120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1255913120
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2937224090
Short name T287
Test name
Test status
Simulation time 327798081410 ps
CPU time 332.43 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:05:51 PM PDT 24
Peak memory 201968 kb
Host smart-94969e4b-cac6-4d20-8549-96fcca726e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937224090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2937224090
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1422477277
Short name T478
Test name
Test status
Simulation time 494072757275 ps
CPU time 588.75 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 201784 kb
Host smart-dea90b58-b64f-4825-a9ff-957862e98489
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422477277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1422477277
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1183775000
Short name T147
Test name
Test status
Simulation time 490191294612 ps
CPU time 288.28 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:05:09 PM PDT 24
Peak memory 201904 kb
Host smart-5a37a1cb-0058-4a86-8de0-ecc050d1a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183775000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1183775000
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2063093497
Short name T552
Test name
Test status
Simulation time 501822515806 ps
CPU time 293.79 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 201980 kb
Host smart-f6825912-c1d0-4ed3-bd56-f8ae5369852b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063093497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2063093497
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2616325766
Short name T255
Test name
Test status
Simulation time 376650104495 ps
CPU time 862.5 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:14:48 PM PDT 24
Peak memory 201996 kb
Host smart-89ed304a-ca17-49eb-892b-399f5f4dd83b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616325766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2616325766
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3337937834
Short name T174
Test name
Test status
Simulation time 202566502974 ps
CPU time 76.83 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:01:38 PM PDT 24
Peak memory 201856 kb
Host smart-b33b29ee-b89d-4c87-9494-b9dee68e8753
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337937834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3337937834
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.391142378
Short name T47
Test name
Test status
Simulation time 85118816748 ps
CPU time 284.34 seconds
Started Jul 05 06:00:30 PM PDT 24
Finished Jul 05 06:05:15 PM PDT 24
Peak memory 202268 kb
Host smart-656a2d14-38f4-45c1-8a41-5105e4774f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391142378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.391142378
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2632254137
Short name T720
Test name
Test status
Simulation time 32403161136 ps
CPU time 8.42 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:00:29 PM PDT 24
Peak memory 201688 kb
Host smart-79d69248-0c8f-4f9c-b7a7-787593f8b8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632254137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2632254137
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.708679931
Short name T710
Test name
Test status
Simulation time 3749860660 ps
CPU time 7.33 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:00:25 PM PDT 24
Peak memory 201716 kb
Host smart-3b6cad20-5073-4885-8191-dbd0d0be6939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708679931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.708679931
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.59450887
Short name T408
Test name
Test status
Simulation time 6005728882 ps
CPU time 4.27 seconds
Started Jul 05 06:00:20 PM PDT 24
Finished Jul 05 06:00:25 PM PDT 24
Peak memory 201752 kb
Host smart-950e1df0-a2c3-44d2-8094-95aa52fdeb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59450887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.59450887
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3377437681
Short name T774
Test name
Test status
Simulation time 53057316928 ps
CPU time 70.64 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:01:37 PM PDT 24
Peak memory 210568 kb
Host smart-90bb5925-fe50-4e42-89c6-2e807a418042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377437681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3377437681
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3562047986
Short name T410
Test name
Test status
Simulation time 492410719 ps
CPU time 0.93 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:42 PM PDT 24
Peak memory 201640 kb
Host smart-2c48c6cd-8d53-4b1a-b746-05ad39dc9f21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562047986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3562047986
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1727694778
Short name T331
Test name
Test status
Simulation time 169585358524 ps
CPU time 31.07 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:00:58 PM PDT 24
Peak memory 201920 kb
Host smart-8a9e4154-17a3-49c5-ad97-569d4e3711fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727694778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1727694778
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4145307210
Short name T390
Test name
Test status
Simulation time 331502916662 ps
CPU time 168.34 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:03:17 PM PDT 24
Peak memory 201872 kb
Host smart-26a7d3ae-012b-4749-9ea9-2ec7272631d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145307210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4145307210
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.49038729
Short name T302
Test name
Test status
Simulation time 158661926083 ps
CPU time 193.28 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:03:38 PM PDT 24
Peak memory 201936 kb
Host smart-23feb59c-8110-425f-977d-5e53333972e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49038729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.49038729
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2938641848
Short name T634
Test name
Test status
Simulation time 164587719221 ps
CPU time 385.88 seconds
Started Jul 05 06:00:22 PM PDT 24
Finished Jul 05 06:06:48 PM PDT 24
Peak memory 201928 kb
Host smart-b0cf1e3b-6690-4ba3-a1cb-9605cb7279cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938641848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2938641848
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2316437074
Short name T532
Test name
Test status
Simulation time 556837651967 ps
CPU time 1246.36 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:21:13 PM PDT 24
Peak memory 201932 kb
Host smart-140148ef-e950-46dd-8cf8-d7d592a00406
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316437074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2316437074
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4086792971
Short name T538
Test name
Test status
Simulation time 597061601843 ps
CPU time 1320.23 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:22:30 PM PDT 24
Peak memory 201924 kb
Host smart-219b92a8-7d4e-467e-af3e-cf8891314480
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086792971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4086792971
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1126137494
Short name T344
Test name
Test status
Simulation time 121563792523 ps
CPU time 465.87 seconds
Started Jul 05 06:00:30 PM PDT 24
Finished Jul 05 06:08:17 PM PDT 24
Peak memory 202216 kb
Host smart-ecdb74b5-7b15-4b06-b4b9-45c2f5f19ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126137494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1126137494
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3473330116
Short name T353
Test name
Test status
Simulation time 31566836713 ps
CPU time 13.91 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:00:43 PM PDT 24
Peak memory 201724 kb
Host smart-067f7ffe-037d-4f9f-b2bc-71ed05244b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473330116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3473330116
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3162413539
Short name T363
Test name
Test status
Simulation time 3464403645 ps
CPU time 8.77 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:00:33 PM PDT 24
Peak memory 201736 kb
Host smart-53fa97c4-5f39-41cd-81c9-51c8287e75e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162413539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3162413539
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3356489869
Short name T691
Test name
Test status
Simulation time 5982763593 ps
CPU time 4.28 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:00:28 PM PDT 24
Peak memory 201680 kb
Host smart-e4208a90-6cf1-42b5-927d-bfd49afb0860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356489869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3356489869
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2906384649
Short name T632
Test name
Test status
Simulation time 329727159203 ps
CPU time 180.03 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:03:28 PM PDT 24
Peak memory 201920 kb
Host smart-25fa7cc0-874f-425b-89cb-50dc61343da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906384649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2906384649
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.244499524
Short name T759
Test name
Test status
Simulation time 395139969 ps
CPU time 0.86 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:00:22 PM PDT 24
Peak memory 201688 kb
Host smart-e5a489c6-cfc7-4040-aae7-382cccc37b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244499524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.244499524
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.505221523
Short name T85
Test name
Test status
Simulation time 161367904302 ps
CPU time 6.72 seconds
Started Jul 05 06:00:32 PM PDT 24
Finished Jul 05 06:00:39 PM PDT 24
Peak memory 201908 kb
Host smart-29a7fc36-ac9d-4168-8750-8265aea493c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505221523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.505221523
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.417977955
Short name T335
Test name
Test status
Simulation time 336099763432 ps
CPU time 201.95 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:03:49 PM PDT 24
Peak memory 201888 kb
Host smart-71d12c48-830b-46c9-a47f-1ca3d27c2f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417977955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.417977955
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1903995674
Short name T579
Test name
Test status
Simulation time 485536696635 ps
CPU time 1072.61 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:18:28 PM PDT 24
Peak memory 201864 kb
Host smart-75b89e45-55af-4523-9e8a-4c5d97e4e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903995674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1903995674
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3165931893
Short name T556
Test name
Test status
Simulation time 323852024072 ps
CPU time 727.35 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:12:31 PM PDT 24
Peak memory 201920 kb
Host smart-78917ccc-89e9-47b7-bb43-afb6ac4c4bbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165931893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3165931893
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.305210667
Short name T597
Test name
Test status
Simulation time 166442386575 ps
CPU time 370.73 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:06:32 PM PDT 24
Peak memory 201920 kb
Host smart-6fb3d0de-4612-4363-b6d4-d0ea0bd0f7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305210667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.305210667
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.617749342
Short name T140
Test name
Test status
Simulation time 488245752430 ps
CPU time 451.74 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:08:09 PM PDT 24
Peak memory 201840 kb
Host smart-3dadf074-19e1-4a7b-a02e-55856360f3e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=617749342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.617749342
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3325479197
Short name T623
Test name
Test status
Simulation time 202846411775 ps
CPU time 78.57 seconds
Started Jul 05 06:00:36 PM PDT 24
Finished Jul 05 06:01:56 PM PDT 24
Peak memory 201916 kb
Host smart-3fb0b1e1-a733-41a1-b35b-feb237052a01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325479197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3325479197
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2397498405
Short name T455
Test name
Test status
Simulation time 37818211661 ps
CPU time 91.02 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:02:06 PM PDT 24
Peak memory 201720 kb
Host smart-4472d9d3-559d-4d2a-b484-463189a9f489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397498405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2397498405
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2507807713
Short name T507
Test name
Test status
Simulation time 4195820620 ps
CPU time 9.82 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:00:36 PM PDT 24
Peak memory 201728 kb
Host smart-5910e58d-6eae-4622-a37a-ef945b8cc85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507807713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2507807713
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3294185182
Short name T348
Test name
Test status
Simulation time 5965402689 ps
CPU time 11.68 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:00:40 PM PDT 24
Peak memory 201736 kb
Host smart-0ccb5986-60ba-454a-8424-27fd3dd40606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294185182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3294185182
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1795363571
Short name T286
Test name
Test status
Simulation time 456155011422 ps
CPU time 833.03 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:14:22 PM PDT 24
Peak memory 201856 kb
Host smart-c3348394-8404-453e-992c-48ecf6114e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795363571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1795363571
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3388485552
Short name T762
Test name
Test status
Simulation time 389704872 ps
CPU time 0.77 seconds
Started Jul 05 06:00:31 PM PDT 24
Finished Jul 05 06:00:33 PM PDT 24
Peak memory 201660 kb
Host smart-619e544d-e256-414c-ae91-8aae4c8f1c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388485552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3388485552
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2558576515
Short name T616
Test name
Test status
Simulation time 173042182705 ps
CPU time 378.79 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:06:42 PM PDT 24
Peak memory 201864 kb
Host smart-8cba9eee-b4d2-4047-8b5f-d841619f5cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558576515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2558576515
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2216407090
Short name T531
Test name
Test status
Simulation time 167489250073 ps
CPU time 90.66 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:02:10 PM PDT 24
Peak memory 201964 kb
Host smart-d1de6f5b-1720-4584-ad31-4c1e7b2bff20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216407090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2216407090
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3992580752
Short name T268
Test name
Test status
Simulation time 331943609933 ps
CPU time 136.42 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:02:46 PM PDT 24
Peak memory 201820 kb
Host smart-25cf6ba5-c372-454a-a4d0-dfa3de615675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992580752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3992580752
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1453661
Short name T516
Test name
Test status
Simulation time 327327258689 ps
CPU time 175.22 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:03:19 PM PDT 24
Peak memory 201884 kb
Host smart-d9329b63-9870-40c6-9aad-7dcf3d01b903
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed.1453661
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.197693086
Short name T3
Test name
Test status
Simulation time 359029968813 ps
CPU time 82.32 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:02:05 PM PDT 24
Peak memory 201936 kb
Host smart-f8b8e60b-c380-4b5c-9632-6f2b0b00158e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197693086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.197693086
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3462847224
Short name T426
Test name
Test status
Simulation time 390171255223 ps
CPU time 840.16 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:14:30 PM PDT 24
Peak memory 201900 kb
Host smart-17bbbb56-531c-473f-9ddf-1418c0dd5bf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462847224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3462847224
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1840590201
Short name T681
Test name
Test status
Simulation time 92431530053 ps
CPU time 498.66 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:08:48 PM PDT 24
Peak memory 202224 kb
Host smart-823e65d9-aa3e-4223-84a9-c5205bfcb7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840590201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1840590201
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3224544822
Short name T670
Test name
Test status
Simulation time 29349604863 ps
CPU time 58.75 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:01:24 PM PDT 24
Peak memory 201724 kb
Host smart-9bcde6f0-ab03-4583-a379-d93e2beb4b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224544822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3224544822
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4094579969
Short name T668
Test name
Test status
Simulation time 4150082939 ps
CPU time 1.52 seconds
Started Jul 05 06:00:21 PM PDT 24
Finished Jul 05 06:00:23 PM PDT 24
Peak memory 201672 kb
Host smart-b88d426d-73a2-4857-8f7a-8b73c05c0c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094579969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4094579969
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2465372521
Short name T629
Test name
Test status
Simulation time 5720774487 ps
CPU time 3.69 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:00:34 PM PDT 24
Peak memory 201732 kb
Host smart-d1c34842-e3e5-4cc6-96c4-3801bfb387f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465372521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2465372521
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2630083271
Short name T600
Test name
Test status
Simulation time 132917793772 ps
CPU time 389.09 seconds
Started Jul 05 06:00:31 PM PDT 24
Finished Jul 05 06:07:01 PM PDT 24
Peak memory 218140 kb
Host smart-8ee6748f-28a4-49a4-8da3-33a97e334ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630083271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2630083271
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.208709810
Short name T735
Test name
Test status
Simulation time 403513850747 ps
CPU time 250.47 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:04:53 PM PDT 24
Peak memory 210592 kb
Host smart-d38ada09-5b2a-4403-92cf-455b48bdb145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208709810 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.208709810
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3346732204
Short name T429
Test name
Test status
Simulation time 375846398 ps
CPU time 0.83 seconds
Started Jul 05 06:00:01 PM PDT 24
Finished Jul 05 06:00:03 PM PDT 24
Peak memory 201668 kb
Host smart-f9714feb-4443-4ebd-ad8c-540badd86fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346732204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3346732204
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.381578654
Short name T610
Test name
Test status
Simulation time 334807724770 ps
CPU time 51.81 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:00:44 PM PDT 24
Peak memory 201912 kb
Host smart-033e3cb1-74dc-44e3-969f-5ebc62dd9f54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381578654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.381578654
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1704053368
Short name T327
Test name
Test status
Simulation time 530777598460 ps
CPU time 328.81 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 201920 kb
Host smart-dc7e647b-8c44-465e-88aa-faa88f0bc2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704053368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1704053368
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3816528220
Short name T437
Test name
Test status
Simulation time 162199684376 ps
CPU time 41.73 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:00:34 PM PDT 24
Peak memory 201852 kb
Host smart-6ea6080b-7e90-4cd0-9bb6-81b148a3b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816528220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3816528220
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3900932711
Short name T742
Test name
Test status
Simulation time 330535658070 ps
CPU time 722.64 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:11:55 PM PDT 24
Peak memory 201968 kb
Host smart-e1451f3c-3836-4570-a4f9-8377b117fb2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900932711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3900932711
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3068600377
Short name T136
Test name
Test status
Simulation time 332360561445 ps
CPU time 369.4 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:06:20 PM PDT 24
Peak memory 201996 kb
Host smart-f07fd804-7397-45e7-b5a9-44281e85f141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068600377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3068600377
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2548555255
Short name T643
Test name
Test status
Simulation time 328995142371 ps
CPU time 402.37 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 06:06:36 PM PDT 24
Peak memory 201884 kb
Host smart-2b35f2d7-a94d-466f-bb99-aaf910e8e1e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548555255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2548555255
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2313594258
Short name T148
Test name
Test status
Simulation time 232287499095 ps
CPU time 255.61 seconds
Started Jul 05 05:59:45 PM PDT 24
Finished Jul 05 06:04:02 PM PDT 24
Peak memory 201992 kb
Host smart-e067e4e8-d450-4879-b25e-6bb1278a8f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313594258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2313594258
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2646577450
Short name T440
Test name
Test status
Simulation time 614504894249 ps
CPU time 334.88 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 201904 kb
Host smart-c13096af-9ae6-4192-94a2-97c5868d1a78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646577450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2646577450
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1340426152
Short name T210
Test name
Test status
Simulation time 78785865469 ps
CPU time 271.94 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:04:25 PM PDT 24
Peak memory 202204 kb
Host smart-de50c32c-8e1e-4dce-b487-25f60406d84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340426152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1340426152
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1385525327
Short name T438
Test name
Test status
Simulation time 22701275287 ps
CPU time 3.39 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:55 PM PDT 24
Peak memory 201724 kb
Host smart-339bb287-0a63-4d55-ad4f-348dcb2840f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385525327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1385525327
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1513224795
Short name T673
Test name
Test status
Simulation time 4804992459 ps
CPU time 6.02 seconds
Started Jul 05 05:59:56 PM PDT 24
Finished Jul 05 06:00:02 PM PDT 24
Peak memory 201644 kb
Host smart-be48557d-ab9e-4182-a992-6e68dd4f31f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513224795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1513224795
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.336708409
Short name T61
Test name
Test status
Simulation time 7836158680 ps
CPU time 9.99 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 05:59:59 PM PDT 24
Peak memory 218256 kb
Host smart-53b08ea5-25ac-4722-876d-0e6d80323752
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336708409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.336708409
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3996310777
Short name T441
Test name
Test status
Simulation time 5784746964 ps
CPU time 13.99 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:00:06 PM PDT 24
Peak memory 201736 kb
Host smart-9e0c7e2f-6400-4e20-9aeb-65182cbcae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996310777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3996310777
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2396301246
Short name T345
Test name
Test status
Simulation time 154947807472 ps
CPU time 679.69 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 06:11:09 PM PDT 24
Peak memory 210300 kb
Host smart-aef40c21-ffd8-4127-8021-8bb363414ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396301246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2396301246
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3171529105
Short name T674
Test name
Test status
Simulation time 479327391 ps
CPU time 0.86 seconds
Started Jul 05 06:00:31 PM PDT 24
Finished Jul 05 06:00:32 PM PDT 24
Peak memory 201628 kb
Host smart-fc1018ba-caae-413f-bf40-3f48e74dea36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171529105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3171529105
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2273812096
Short name T244
Test name
Test status
Simulation time 411680222676 ps
CPU time 421.85 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:07:42 PM PDT 24
Peak memory 201932 kb
Host smart-394ab8c0-5a3e-4082-bfaa-d9063c8df496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273812096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2273812096
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1730726897
Short name T303
Test name
Test status
Simulation time 168693943650 ps
CPU time 401.83 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:07:09 PM PDT 24
Peak memory 201916 kb
Host smart-59bff71f-f6d5-4f38-aa09-fb5c83ef7a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730726897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1730726897
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1976467155
Short name T226
Test name
Test status
Simulation time 493341032259 ps
CPU time 562.51 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 201996 kb
Host smart-7c966011-a82d-484f-bcdb-381c2788fe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976467155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1976467155
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1458054751
Short name T8
Test name
Test status
Simulation time 166078737918 ps
CPU time 185.34 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:03:44 PM PDT 24
Peak memory 201920 kb
Host smart-e4bd1119-d192-4268-8edf-3020ec563b74
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458054751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1458054751
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2213973662
Short name T269
Test name
Test status
Simulation time 326748602178 ps
CPU time 129.63 seconds
Started Jul 05 06:00:30 PM PDT 24
Finished Jul 05 06:02:40 PM PDT 24
Peak memory 201836 kb
Host smart-d78dc29d-ac9f-41d2-89f9-a5cedb3763fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213973662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2213973662
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1714795139
Short name T787
Test name
Test status
Simulation time 328129906838 ps
CPU time 183.5 seconds
Started Jul 05 06:00:28 PM PDT 24
Finished Jul 05 06:03:32 PM PDT 24
Peak memory 201916 kb
Host smart-533768ea-5e0b-45f5-8ae1-fb2405045fa4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714795139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1714795139
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3512776271
Short name T457
Test name
Test status
Simulation time 413983827629 ps
CPU time 265.08 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:04:55 PM PDT 24
Peak memory 201900 kb
Host smart-2010c3d6-e445-4c8a-8bbb-2bcc79ae90af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512776271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3512776271
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2577816476
Short name T341
Test name
Test status
Simulation time 109112098545 ps
CPU time 405.35 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:07:28 PM PDT 24
Peak memory 202228 kb
Host smart-5b1eb141-75d4-4ee0-b932-bd12b830048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577816476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2577816476
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.635846927
Short name T534
Test name
Test status
Simulation time 26452894786 ps
CPU time 15.77 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:00:59 PM PDT 24
Peak memory 201724 kb
Host smart-b6d88663-f47e-4500-9c12-dd81b29ac2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635846927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.635846927
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1730783935
Short name T598
Test name
Test status
Simulation time 2985412387 ps
CPU time 6.75 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:00:50 PM PDT 24
Peak memory 201724 kb
Host smart-d08284a1-be56-43a8-9292-33b33db2f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730783935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1730783935
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1202526036
Short name T483
Test name
Test status
Simulation time 6039744639 ps
CPU time 15.28 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:00:51 PM PDT 24
Peak memory 201740 kb
Host smart-329afc22-ac4f-4e65-895c-a3169a8ceb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202526036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1202526036
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.667973950
Short name T16
Test name
Test status
Simulation time 172861055386 ps
CPU time 203.31 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:03:53 PM PDT 24
Peak memory 210556 kb
Host smart-84fbe3fc-a2f1-4630-8c45-1db675d6a9c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667973950 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.667973950
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1714811853
Short name T278
Test name
Test status
Simulation time 571868100272 ps
CPU time 1253.12 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:21:36 PM PDT 24
Peak memory 201832 kb
Host smart-2c4bb18f-f4da-4e87-84e8-75b2d7193297
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714811853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1714811853
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3288721789
Short name T685
Test name
Test status
Simulation time 489266766644 ps
CPU time 318.91 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:05:58 PM PDT 24
Peak memory 201904 kb
Host smart-2f05cf8a-7dc7-4a41-b9a4-531fc9084668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288721789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3288721789
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.944446278
Short name T692
Test name
Test status
Simulation time 168203264929 ps
CPU time 357.96 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:06:32 PM PDT 24
Peak memory 201860 kb
Host smart-19228875-d54f-4e25-a319-6fe945a7da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944446278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.944446278
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.4087224749
Short name T642
Test name
Test status
Simulation time 167184463485 ps
CPU time 367.4 seconds
Started Jul 05 06:00:31 PM PDT 24
Finished Jul 05 06:06:39 PM PDT 24
Peak memory 201888 kb
Host smart-09ce26e4-eb95-4d97-a9df-55374f3c75e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087224749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.4087224749
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1646021200
Short name T571
Test name
Test status
Simulation time 163327908179 ps
CPU time 178.43 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:03:25 PM PDT 24
Peak memory 201912 kb
Host smart-c7a3b9b8-3622-4e46-bdd7-f66c1ba2c489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646021200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1646021200
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1581189706
Short name T141
Test name
Test status
Simulation time 168073753014 ps
CPU time 336.97 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:06:21 PM PDT 24
Peak memory 201908 kb
Host smart-c653eaf1-48e1-4193-a06b-e8b454db4f06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581189706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1581189706
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.345613427
Short name T240
Test name
Test status
Simulation time 520603201509 ps
CPU time 1175.26 seconds
Started Jul 05 06:00:30 PM PDT 24
Finished Jul 05 06:20:06 PM PDT 24
Peak memory 201904 kb
Host smart-5c0cc416-5200-47c7-9c39-bfa71db84d15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345613427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.345613427
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1737645128
Short name T560
Test name
Test status
Simulation time 397991395522 ps
CPU time 216 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:04:12 PM PDT 24
Peak memory 201920 kb
Host smart-d4d9e59a-f880-454d-8c88-1b638019a1a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737645128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1737645128
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.163647395
Short name T431
Test name
Test status
Simulation time 126021114278 ps
CPU time 399.68 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:07:19 PM PDT 24
Peak memory 202212 kb
Host smart-7b03d9b0-cdcf-484b-a6c8-f62d58eb7a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163647395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.163647395
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2129960543
Short name T400
Test name
Test status
Simulation time 41179975857 ps
CPU time 22.28 seconds
Started Jul 05 06:00:30 PM PDT 24
Finished Jul 05 06:00:53 PM PDT 24
Peak memory 201968 kb
Host smart-e2bb7fab-f523-496f-b387-ccb48cc61b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129960543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2129960543
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.457088157
Short name T658
Test name
Test status
Simulation time 3770778923 ps
CPU time 4.87 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:00:33 PM PDT 24
Peak memory 201724 kb
Host smart-709ab333-2b2e-480a-8ce1-2b712073d80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457088157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.457088157
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1409977264
Short name T412
Test name
Test status
Simulation time 5848184919 ps
CPU time 13.84 seconds
Started Jul 05 06:00:26 PM PDT 24
Finished Jul 05 06:00:41 PM PDT 24
Peak memory 201700 kb
Host smart-3760dcfb-fab6-4af1-8163-db06baf9618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409977264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1409977264
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2028038759
Short name T751
Test name
Test status
Simulation time 209067389832 ps
CPU time 441.62 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 201980 kb
Host smart-54d3a9c7-36f3-44fd-9421-7501588a3015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028038759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2028038759
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2552380584
Short name T208
Test name
Test status
Simulation time 339687504374 ps
CPU time 693.79 seconds
Started Jul 05 06:00:32 PM PDT 24
Finished Jul 05 06:12:06 PM PDT 24
Peak memory 218000 kb
Host smart-6b51e24c-13f4-4bc5-8f6e-bbead3a651ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552380584 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2552380584
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.639854813
Short name T731
Test name
Test status
Simulation time 525217403 ps
CPU time 0.88 seconds
Started Jul 05 06:00:27 PM PDT 24
Finished Jul 05 06:00:28 PM PDT 24
Peak memory 201676 kb
Host smart-507deb1d-6506-4343-a054-a9c935b4f395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639854813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.639854813
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1311350865
Short name T788
Test name
Test status
Simulation time 353422993209 ps
CPU time 227.86 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:04:24 PM PDT 24
Peak memory 201916 kb
Host smart-8bded66d-8d90-4223-94e5-d84c35377071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311350865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1311350865
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3827067398
Short name T733
Test name
Test status
Simulation time 158040862265 ps
CPU time 355.97 seconds
Started Jul 05 06:00:23 PM PDT 24
Finished Jul 05 06:06:20 PM PDT 24
Peak memory 201988 kb
Host smart-bec974b6-3c1c-46e6-9f8d-976b9ae56f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827067398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3827067398
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.484365132
Short name T767
Test name
Test status
Simulation time 170022992473 ps
CPU time 99.67 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:02:19 PM PDT 24
Peak memory 201892 kb
Host smart-a05b3bbb-7963-4c92-8ad2-714d4353fe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484365132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.484365132
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.337759506
Short name T604
Test name
Test status
Simulation time 487180294967 ps
CPU time 802.54 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:13:53 PM PDT 24
Peak memory 201928 kb
Host smart-63ea3564-e7b2-4cb9-b02c-4578c1f3ef86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=337759506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.337759506
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2960240173
Short name T619
Test name
Test status
Simulation time 537470051702 ps
CPU time 314.89 seconds
Started Jul 05 06:00:36 PM PDT 24
Finished Jul 05 06:05:52 PM PDT 24
Peak memory 201936 kb
Host smart-3ddc0f74-9299-46f9-8c29-15a0e70a1efc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960240173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2960240173
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3164485213
Short name T464
Test name
Test status
Simulation time 399638082412 ps
CPU time 417.01 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:07:31 PM PDT 24
Peak memory 201812 kb
Host smart-a3f02534-2b5e-4f9e-905a-35151a3afa13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164485213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3164485213
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1572432944
Short name T165
Test name
Test status
Simulation time 101832335227 ps
CPU time 349.05 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:06:15 PM PDT 24
Peak memory 202192 kb
Host smart-7311e6d2-ab71-4cf9-9515-f34516b9c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572432944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1572432944
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1346500672
Short name T401
Test name
Test status
Simulation time 25481024096 ps
CPU time 56.78 seconds
Started Jul 05 06:00:31 PM PDT 24
Finished Jul 05 06:01:28 PM PDT 24
Peak memory 201720 kb
Host smart-c1a0aa73-c597-4d21-8484-5dd39ea342c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346500672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1346500672
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.4166928106
Short name T589
Test name
Test status
Simulation time 5105673467 ps
CPU time 6.04 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:48 PM PDT 24
Peak memory 201712 kb
Host smart-5eec816c-be51-4a23-9134-45687e831b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166928106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4166928106
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3535700651
Short name T402
Test name
Test status
Simulation time 5803817683 ps
CPU time 5.7 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:00:41 PM PDT 24
Peak memory 201736 kb
Host smart-068d901c-ceb8-4194-a56f-0009ae4c370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535700651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3535700651
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2928650078
Short name T557
Test name
Test status
Simulation time 405439765803 ps
CPU time 715.23 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:12:37 PM PDT 24
Peak memory 210456 kb
Host smart-36e8500f-43c7-4731-a794-2d521cc26d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928650078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2928650078
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2604370228
Short name T778
Test name
Test status
Simulation time 59238579270 ps
CPU time 104.64 seconds
Started Jul 05 06:00:24 PM PDT 24
Finished Jul 05 06:02:10 PM PDT 24
Peak memory 210228 kb
Host smart-ee9cb67c-60fb-4bd1-87a9-e37dbcd109d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604370228 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2604370228
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3429510408
Short name T739
Test name
Test status
Simulation time 522674289 ps
CPU time 0.9 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:00:41 PM PDT 24
Peak memory 201664 kb
Host smart-34b92394-2102-4460-89aa-a8c3e5bd672c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429510408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3429510408
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1338653052
Short name T482
Test name
Test status
Simulation time 169736403069 ps
CPU time 15.62 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:00:50 PM PDT 24
Peak memory 201828 kb
Host smart-2e4079fd-1a68-4602-979e-4394aa552c57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338653052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1338653052
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1549418300
Short name T620
Test name
Test status
Simulation time 160537421558 ps
CPU time 100.81 seconds
Started Jul 05 06:00:44 PM PDT 24
Finished Jul 05 06:02:26 PM PDT 24
Peak memory 201980 kb
Host smart-46166d93-f779-4519-aecd-9fb73a1ba7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549418300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1549418300
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2939793153
Short name T545
Test name
Test status
Simulation time 486244096716 ps
CPU time 113.27 seconds
Started Jul 05 06:00:32 PM PDT 24
Finished Jul 05 06:02:25 PM PDT 24
Peak memory 201912 kb
Host smart-c3b268ce-135c-4b8c-b021-17f0e839206e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939793153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2939793153
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2966391067
Short name T635
Test name
Test status
Simulation time 324013166695 ps
CPU time 663.64 seconds
Started Jul 05 06:00:29 PM PDT 24
Finished Jul 05 06:11:34 PM PDT 24
Peak memory 201900 kb
Host smart-2b69eec1-6a4f-4700-8b2f-0d1be6f6ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966391067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2966391067
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3700612614
Short name T139
Test name
Test status
Simulation time 166311060511 ps
CPU time 231.73 seconds
Started Jul 05 06:00:36 PM PDT 24
Finished Jul 05 06:04:29 PM PDT 24
Peak memory 202136 kb
Host smart-7f1ca025-3605-447e-9a19-27ff698fc889
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700612614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3700612614
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1946420899
Short name T89
Test name
Test status
Simulation time 195062107011 ps
CPU time 413.47 seconds
Started Jul 05 06:00:31 PM PDT 24
Finished Jul 05 06:07:25 PM PDT 24
Peak memory 201856 kb
Host smart-9769d1ee-e4e7-4e86-915f-8b9a87ead32d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946420899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1946420899
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3869666636
Short name T690
Test name
Test status
Simulation time 408958520816 ps
CPU time 856.18 seconds
Started Jul 05 06:00:25 PM PDT 24
Finished Jul 05 06:14:42 PM PDT 24
Peak memory 201920 kb
Host smart-bfc998f8-1f15-4110-8881-d05f20e7e078
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869666636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3869666636
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.796083705
Short name T528
Test name
Test status
Simulation time 91476880263 ps
CPU time 505.87 seconds
Started Jul 05 06:00:32 PM PDT 24
Finished Jul 05 06:08:59 PM PDT 24
Peak memory 202292 kb
Host smart-519d45dd-71b7-49fa-9809-f213f7365dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796083705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.796083705
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1314260775
Short name T421
Test name
Test status
Simulation time 25437007308 ps
CPU time 52.33 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:01:31 PM PDT 24
Peak memory 201720 kb
Host smart-d73b92b3-5667-4f78-8e55-a8de8855c04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314260775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1314260775
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2712371902
Short name T434
Test name
Test status
Simulation time 4816360590 ps
CPU time 2.34 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:44 PM PDT 24
Peak memory 201700 kb
Host smart-2f4dcbf6-3c88-447d-a359-198d8325469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712371902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2712371902
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1488721568
Short name T462
Test name
Test status
Simulation time 5733550925 ps
CPU time 13.75 seconds
Started Jul 05 06:00:43 PM PDT 24
Finished Jul 05 06:00:58 PM PDT 24
Peak memory 201740 kb
Host smart-13ed5f47-0fb8-4496-ad34-362757a8c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488721568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1488721568
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.962944677
Short name T789
Test name
Test status
Simulation time 959946883901 ps
CPU time 1061.2 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:18:23 PM PDT 24
Peak memory 201960 kb
Host smart-db692a95-3691-404e-a840-931b3df0db9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962944677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
962944677
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1568755000
Short name T130
Test name
Test status
Simulation time 51243399909 ps
CPU time 75.04 seconds
Started Jul 05 06:00:43 PM PDT 24
Finished Jul 05 06:01:59 PM PDT 24
Peak memory 210280 kb
Host smart-e77a29c2-06ba-4d0f-8e44-9de8533e5c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568755000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1568755000
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.885193190
Short name T70
Test name
Test status
Simulation time 595615875 ps
CPU time 0.76 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:00:39 PM PDT 24
Peak memory 201664 kb
Host smart-3c04158a-5e58-4ae5-a2b0-66f8c6f92ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885193190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.885193190
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2755753901
Short name T277
Test name
Test status
Simulation time 242605855337 ps
CPU time 94.34 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:02:15 PM PDT 24
Peak memory 201884 kb
Host smart-755026be-6032-4f00-af05-10328f913fcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755753901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2755753901
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1964378818
Short name T86
Test name
Test status
Simulation time 501310293318 ps
CPU time 1223.55 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:21:05 PM PDT 24
Peak memory 201904 kb
Host smart-df3853da-633e-4f7d-86a3-d05abf9a1cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964378818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1964378818
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3644635293
Short name T784
Test name
Test status
Simulation time 331628780992 ps
CPU time 195.65 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:03:57 PM PDT 24
Peak memory 201920 kb
Host smart-224dbb5a-c68b-4a44-9aa6-c85c7a185358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644635293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3644635293
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.198399819
Short name T425
Test name
Test status
Simulation time 495984772883 ps
CPU time 916.97 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:15:57 PM PDT 24
Peak memory 201888 kb
Host smart-980a1c85-7b06-455d-97fc-ea4253d8935b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=198399819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.198399819
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1301511093
Short name T740
Test name
Test status
Simulation time 503059790896 ps
CPU time 267.2 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:05:10 PM PDT 24
Peak memory 201864 kb
Host smart-6cd1f87e-fb90-4dae-ae1f-e5997c8e8b58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301511093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1301511093
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3237710688
Short name T304
Test name
Test status
Simulation time 392466552885 ps
CPU time 803.11 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:14:01 PM PDT 24
Peak memory 201996 kb
Host smart-5028bd39-e425-44c4-8c7b-2509449ab048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237710688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3237710688
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3718260191
Short name T756
Test name
Test status
Simulation time 391575242840 ps
CPU time 413.51 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:07:29 PM PDT 24
Peak memory 201892 kb
Host smart-cfcd51b2-fd98-458e-afe3-c38850f054c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718260191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3718260191
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3723811727
Short name T215
Test name
Test status
Simulation time 127716656969 ps
CPU time 696.82 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:12:16 PM PDT 24
Peak memory 202248 kb
Host smart-858bc0f2-f746-4f38-ba7f-feb095b251fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723811727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3723811727
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3980543841
Short name T424
Test name
Test status
Simulation time 41296343301 ps
CPU time 12.85 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:00:48 PM PDT 24
Peak memory 201724 kb
Host smart-1e401aed-079c-49f1-86c0-43443b757b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980543841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3980543841
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1023615836
Short name T362
Test name
Test status
Simulation time 4055178698 ps
CPU time 4.9 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:46 PM PDT 24
Peak memory 201696 kb
Host smart-276e3e37-a140-4d0f-ab49-f713404636b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023615836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1023615836
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3488385878
Short name T572
Test name
Test status
Simulation time 5875432818 ps
CPU time 2.79 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:00:46 PM PDT 24
Peak memory 201744 kb
Host smart-05974b57-4488-4344-b551-3e51820a005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488385878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3488385878
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3104956941
Short name T32
Test name
Test status
Simulation time 345476168664 ps
CPU time 955.26 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:16:35 PM PDT 24
Peak memory 210472 kb
Host smart-b994b864-151b-4ddf-bdbc-0af7e09d3391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104956941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3104956941
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2371724784
Short name T656
Test name
Test status
Simulation time 500509853 ps
CPU time 0.95 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:00:44 PM PDT 24
Peak memory 201664 kb
Host smart-a58326c6-dab2-4735-8874-e90969e5c72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371724784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2371724784
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2785099913
Short name T536
Test name
Test status
Simulation time 159986025789 ps
CPU time 195.81 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:03:55 PM PDT 24
Peak memory 202004 kb
Host smart-db8b1112-9493-47d9-bd97-da80ed967ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785099913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2785099913
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.37123633
Short name T757
Test name
Test status
Simulation time 331559015431 ps
CPU time 128.72 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:02:51 PM PDT 24
Peak memory 201900 kb
Host smart-17e9d812-ac3a-4213-b17c-f6171fc1577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37123633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.37123633
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2045068769
Short name T376
Test name
Test status
Simulation time 167755014344 ps
CPU time 190.81 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:03:46 PM PDT 24
Peak memory 201912 kb
Host smart-131f3b67-c57b-4789-8dea-103f8c6b7151
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045068769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2045068769
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2697164665
Short name T284
Test name
Test status
Simulation time 495571550352 ps
CPU time 279.19 seconds
Started Jul 05 06:00:34 PM PDT 24
Finished Jul 05 06:05:14 PM PDT 24
Peak memory 201820 kb
Host smart-53530cef-9000-41fb-a75b-64d8c051c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697164665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2697164665
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2665691468
Short name T515
Test name
Test status
Simulation time 494893047918 ps
CPU time 1154.2 seconds
Started Jul 05 06:00:32 PM PDT 24
Finished Jul 05 06:19:47 PM PDT 24
Peak memory 201960 kb
Host smart-8efd7937-5524-471b-a22c-ddd1af133fd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665691468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2665691468
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3614454408
Short name T675
Test name
Test status
Simulation time 189166673298 ps
CPU time 110.23 seconds
Started Jul 05 06:00:36 PM PDT 24
Finished Jul 05 06:02:27 PM PDT 24
Peak memory 201984 kb
Host smart-5cb2f7ef-d209-4721-8bc8-9ab591d71d39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614454408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3614454408
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3662512855
Short name T420
Test name
Test status
Simulation time 186362297913 ps
CPU time 209.98 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:04:11 PM PDT 24
Peak memory 201888 kb
Host smart-b44cb043-6bef-4084-91be-90b7c656fad2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662512855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3662512855
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1859432978
Short name T44
Test name
Test status
Simulation time 118741520379 ps
CPU time 502.6 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:09:00 PM PDT 24
Peak memory 202272 kb
Host smart-f9ee2a43-4ca0-41c3-aa67-085f7116f61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859432978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1859432978
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.642696848
Short name T381
Test name
Test status
Simulation time 37993281718 ps
CPU time 79.53 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:02:02 PM PDT 24
Peak memory 201712 kb
Host smart-21bef339-1a2d-4ee2-80cd-80223f94b90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642696848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.642696848
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1698294661
Short name T660
Test name
Test status
Simulation time 5056486425 ps
CPU time 3.91 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:45 PM PDT 24
Peak memory 201724 kb
Host smart-70116922-33d9-422f-a5b4-062ed1ebee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698294661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1698294661
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.172290268
Short name T96
Test name
Test status
Simulation time 5986906784 ps
CPU time 4.47 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:00:43 PM PDT 24
Peak memory 201708 kb
Host smart-41a7375f-1e0d-421f-b462-cffaafeb5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172290268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.172290268
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3617959764
Short name T370
Test name
Test status
Simulation time 8859877347 ps
CPU time 9.38 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:50 PM PDT 24
Peak memory 201692 kb
Host smart-982044ed-54c9-4b5c-8781-befa445ccfb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617959764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3617959764
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3374286094
Short name T280
Test name
Test status
Simulation time 482458841770 ps
CPU time 198.88 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:04:01 PM PDT 24
Peak memory 210608 kb
Host smart-c726f07b-df01-46e6-a452-c34d27ad63e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374286094 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3374286094
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4227628720
Short name T607
Test name
Test status
Simulation time 495048398 ps
CPU time 0.93 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:00:44 PM PDT 24
Peak memory 201664 kb
Host smart-df291c6c-35d7-4334-96da-e20cf3e2527d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227628720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4227628720
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2597649945
Short name T697
Test name
Test status
Simulation time 502703535260 ps
CPU time 611.79 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:10:53 PM PDT 24
Peak memory 201908 kb
Host smart-9fc541b7-ab9f-46cc-bcd9-4aab29152638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597649945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2597649945
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2902240554
Short name T611
Test name
Test status
Simulation time 165857287972 ps
CPU time 395.37 seconds
Started Jul 05 06:00:35 PM PDT 24
Finished Jul 05 06:07:11 PM PDT 24
Peak memory 201920 kb
Host smart-592f80bd-20da-4c0c-a7d5-dc041a76eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902240554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2902240554
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3401848465
Short name T411
Test name
Test status
Simulation time 330357284590 ps
CPU time 772.47 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:13:35 PM PDT 24
Peak memory 201936 kb
Host smart-bcada2cd-bbf6-4307-a76a-5eef2cdc8159
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401848465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3401848465
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3739706650
Short name T583
Test name
Test status
Simulation time 168530075592 ps
CPU time 67.61 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:01:50 PM PDT 24
Peak memory 201900 kb
Host smart-7a5b1b4d-b576-406e-952d-a57fd97dfda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739706650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3739706650
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3128857675
Short name T273
Test name
Test status
Simulation time 177545291796 ps
CPU time 202.86 seconds
Started Jul 05 06:00:43 PM PDT 24
Finished Jul 05 06:04:07 PM PDT 24
Peak memory 201980 kb
Host smart-73ebd7b2-67c8-4c1d-b04d-c20372475efa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128857675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3128857675
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3372603668
Short name T492
Test name
Test status
Simulation time 198142252898 ps
CPU time 37.45 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:01:15 PM PDT 24
Peak memory 201868 kb
Host smart-5ed18dbd-055a-4065-ba8b-80592fe7909d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372603668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3372603668
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1134215233
Short name T511
Test name
Test status
Simulation time 123466670635 ps
CPU time 617.74 seconds
Started Jul 05 06:00:43 PM PDT 24
Finished Jul 05 06:11:02 PM PDT 24
Peak memory 202256 kb
Host smart-54465bfd-c967-426f-a314-0e05f9115cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134215233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1134215233
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3561937655
Short name T156
Test name
Test status
Simulation time 31726805542 ps
CPU time 34.24 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:01:17 PM PDT 24
Peak memory 201692 kb
Host smart-307bfebe-1f97-4dbf-bec6-9c7811a204fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561937655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3561937655
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1001287924
Short name T727
Test name
Test status
Simulation time 4655145192 ps
CPU time 10.75 seconds
Started Jul 05 06:00:36 PM PDT 24
Finished Jul 05 06:00:47 PM PDT 24
Peak memory 201732 kb
Host smart-da1c5e31-c698-43d0-8b56-e03f03c6e1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001287924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1001287924
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2775345532
Short name T500
Test name
Test status
Simulation time 5985656426 ps
CPU time 1.87 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:00:43 PM PDT 24
Peak memory 201732 kb
Host smart-ced10e82-01f4-4ac8-9e9b-dd69cb88de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775345532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2775345532
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3901642131
Short name T761
Test name
Test status
Simulation time 169742046940 ps
CPU time 352.48 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:06:36 PM PDT 24
Peak memory 201908 kb
Host smart-3c0755b1-cd6d-46f9-b15f-e17334480c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901642131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3901642131
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2493348694
Short name T102
Test name
Test status
Simulation time 63425440301 ps
CPU time 54.39 seconds
Started Jul 05 06:00:42 PM PDT 24
Finished Jul 05 06:01:38 PM PDT 24
Peak memory 202076 kb
Host smart-d39a41c3-721a-48cc-9ab5-d26009b199ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493348694 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2493348694
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3365017538
Short name T351
Test name
Test status
Simulation time 314937292 ps
CPU time 0.79 seconds
Started Jul 05 06:00:44 PM PDT 24
Finished Jul 05 06:00:46 PM PDT 24
Peak memory 201660 kb
Host smart-f6c685ef-79f4-46c3-9f87-8017c7623cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365017538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3365017538
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.469661246
Short name T43
Test name
Test status
Simulation time 401307262516 ps
CPU time 203.43 seconds
Started Jul 05 06:00:43 PM PDT 24
Finished Jul 05 06:04:08 PM PDT 24
Peak memory 201892 kb
Host smart-dbf8da22-7806-44ad-a08a-caf7791ae5c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469661246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.469661246
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.271272033
Short name T2
Test name
Test status
Simulation time 161868902205 ps
CPU time 363.77 seconds
Started Jul 05 06:00:40 PM PDT 24
Finished Jul 05 06:06:45 PM PDT 24
Peak memory 201920 kb
Host smart-8400014f-c336-48ce-86f5-967fc0a5a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271272033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.271272033
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.978136949
Short name T322
Test name
Test status
Simulation time 164873874168 ps
CPU time 200.06 seconds
Started Jul 05 06:00:55 PM PDT 24
Finished Jul 05 06:04:15 PM PDT 24
Peak memory 201892 kb
Host smart-0920b9a3-d79b-4bee-b4ac-23a874abcbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978136949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.978136949
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2110304580
Short name T702
Test name
Test status
Simulation time 160359529415 ps
CPU time 182.02 seconds
Started Jul 05 06:00:41 PM PDT 24
Finished Jul 05 06:03:45 PM PDT 24
Peak memory 201916 kb
Host smart-e8800d21-3094-44d9-bc06-016a567fb9d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110304580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2110304580
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4294316177
Short name T566
Test name
Test status
Simulation time 165353493426 ps
CPU time 48.3 seconds
Started Jul 05 06:00:38 PM PDT 24
Finished Jul 05 06:01:27 PM PDT 24
Peak memory 201896 kb
Host smart-4a0067b1-c9a2-4e82-afc9-d51c36197971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294316177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4294316177
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4195593260
Short name T541
Test name
Test status
Simulation time 318125549526 ps
CPU time 693.21 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:12:13 PM PDT 24
Peak memory 201908 kb
Host smart-007ca239-c57e-4c16-9db3-3e99668fd08e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195593260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4195593260
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2227765370
Short name T553
Test name
Test status
Simulation time 193270437122 ps
CPU time 240.98 seconds
Started Jul 05 06:00:51 PM PDT 24
Finished Jul 05 06:04:53 PM PDT 24
Peak memory 201896 kb
Host smart-ebe51ea8-ba41-4228-8648-45a364d4faa6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227765370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2227765370
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.219501030
Short name T449
Test name
Test status
Simulation time 127313426272 ps
CPU time 431.31 seconds
Started Jul 05 06:00:47 PM PDT 24
Finished Jul 05 06:07:58 PM PDT 24
Peak memory 202280 kb
Host smart-b670221b-a309-485c-b97e-6c5b5da989f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219501030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.219501030
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2436019165
Short name T574
Test name
Test status
Simulation time 31823448308 ps
CPU time 74.14 seconds
Started Jul 05 06:00:39 PM PDT 24
Finished Jul 05 06:01:54 PM PDT 24
Peak memory 201664 kb
Host smart-b7ed2dd3-1e00-4c7b-92da-7c5e661aaf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436019165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2436019165
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1858399525
Short name T517
Test name
Test status
Simulation time 3717662051 ps
CPU time 2.45 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:00:49 PM PDT 24
Peak memory 201680 kb
Host smart-df3f24ae-bd95-4635-accf-29a6f9de6d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858399525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1858399525
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2381420792
Short name T701
Test name
Test status
Simulation time 6013120220 ps
CPU time 4.05 seconds
Started Jul 05 06:00:37 PM PDT 24
Finished Jul 05 06:00:42 PM PDT 24
Peak memory 201736 kb
Host smart-470fcf6a-05d3-45ec-8736-62fa40873799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381420792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2381420792
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3864944274
Short name T454
Test name
Test status
Simulation time 168551659570 ps
CPU time 348.23 seconds
Started Jul 05 06:00:49 PM PDT 24
Finished Jul 05 06:06:37 PM PDT 24
Peak memory 201872 kb
Host smart-c7306158-92c1-4a78-b0c0-29cce7043287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864944274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3864944274
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.351155828
Short name T725
Test name
Test status
Simulation time 423461525596 ps
CPU time 662.89 seconds
Started Jul 05 06:00:53 PM PDT 24
Finished Jul 05 06:11:56 PM PDT 24
Peak memory 217852 kb
Host smart-97456e51-486c-4ba9-82cb-01d623eb3021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351155828 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.351155828
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.262891221
Short name T69
Test name
Test status
Simulation time 418456978 ps
CPU time 1.53 seconds
Started Jul 05 06:00:53 PM PDT 24
Finished Jul 05 06:00:55 PM PDT 24
Peak memory 201664 kb
Host smart-7f4886dd-d779-4b6e-b851-4cd708a6faf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262891221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.262891221
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3307134966
Short name T498
Test name
Test status
Simulation time 170376244630 ps
CPU time 26.26 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:01:12 PM PDT 24
Peak memory 201980 kb
Host smart-b2360082-ebb1-43d4-ad6b-0aefc14e27d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307134966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3307134966
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1440644457
Short name T14
Test name
Test status
Simulation time 169795261758 ps
CPU time 103.76 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:02:30 PM PDT 24
Peak memory 201876 kb
Host smart-f217acb5-a23f-45f3-9a18-96b1d298279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440644457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1440644457
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3878409859
Short name T535
Test name
Test status
Simulation time 323352021605 ps
CPU time 204.3 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:04:10 PM PDT 24
Peak memory 201840 kb
Host smart-ff8f94f6-2323-472e-bccc-f36b17f1ae3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878409859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3878409859
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2339959371
Short name T539
Test name
Test status
Simulation time 502329800942 ps
CPU time 549.59 seconds
Started Jul 05 06:00:46 PM PDT 24
Finished Jul 05 06:09:56 PM PDT 24
Peak memory 201976 kb
Host smart-900599e8-30d4-4553-bd1c-bfc0041fa6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339959371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2339959371
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3776109130
Short name T654
Test name
Test status
Simulation time 474215148981 ps
CPU time 257.46 seconds
Started Jul 05 06:00:44 PM PDT 24
Finished Jul 05 06:05:03 PM PDT 24
Peak memory 201896 kb
Host smart-65f82494-4dba-444c-b14f-631becbcb5f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776109130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3776109130
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3237491506
Short name T311
Test name
Test status
Simulation time 180812754383 ps
CPU time 222.9 seconds
Started Jul 05 06:00:46 PM PDT 24
Finished Jul 05 06:04:29 PM PDT 24
Peak memory 201972 kb
Host smart-c3001028-4784-4987-ae76-6534383c0d38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237491506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3237491506
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.242147978
Short name T379
Test name
Test status
Simulation time 401265385715 ps
CPU time 447.69 seconds
Started Jul 05 06:00:47 PM PDT 24
Finished Jul 05 06:08:15 PM PDT 24
Peak memory 201860 kb
Host smart-541258b2-70c7-437e-8660-3454949c6091
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242147978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.242147978
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3689779106
Short name T207
Test name
Test status
Simulation time 97413970438 ps
CPU time 520.6 seconds
Started Jul 05 06:00:47 PM PDT 24
Finished Jul 05 06:09:28 PM PDT 24
Peak memory 202160 kb
Host smart-38bfd36f-3f81-4fc0-99de-1a3a83d16d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689779106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3689779106
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.126526880
Short name T729
Test name
Test status
Simulation time 45884807747 ps
CPU time 15.92 seconds
Started Jul 05 06:00:52 PM PDT 24
Finished Jul 05 06:01:08 PM PDT 24
Peak memory 201724 kb
Host smart-5486769d-174a-48a2-a250-15c9e83eab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126526880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.126526880
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2745778694
Short name T569
Test name
Test status
Simulation time 3268258307 ps
CPU time 1.55 seconds
Started Jul 05 06:00:54 PM PDT 24
Finished Jul 05 06:00:56 PM PDT 24
Peak memory 201632 kb
Host smart-fc062a32-f954-4bac-af23-f3b3d179f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745778694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2745778694
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1914380640
Short name T550
Test name
Test status
Simulation time 5701697000 ps
CPU time 14.41 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:01:00 PM PDT 24
Peak memory 201732 kb
Host smart-8a8b1b19-00fa-4dec-b27d-7473aaea4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914380640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1914380640
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2368030136
Short name T591
Test name
Test status
Simulation time 170082756323 ps
CPU time 718.14 seconds
Started Jul 05 06:00:54 PM PDT 24
Finished Jul 05 06:12:52 PM PDT 24
Peak memory 202132 kb
Host smart-6e0896fd-8d11-4f20-b7fa-77599112e878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368030136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2368030136
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3588040318
Short name T753
Test name
Test status
Simulation time 69652184423 ps
CPU time 81.72 seconds
Started Jul 05 06:00:45 PM PDT 24
Finished Jul 05 06:02:08 PM PDT 24
Peak memory 210580 kb
Host smart-f4f95377-7335-4cb9-966a-816080eab2e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588040318 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3588040318
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3550355288
Short name T769
Test name
Test status
Simulation time 397076567 ps
CPU time 1.08 seconds
Started Jul 05 06:00:57 PM PDT 24
Finished Jul 05 06:00:59 PM PDT 24
Peak memory 201628 kb
Host smart-941a1b7e-fbee-43cf-b0c8-614e8a747136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550355288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3550355288
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3865876466
Short name T663
Test name
Test status
Simulation time 537126836443 ps
CPU time 1320.32 seconds
Started Jul 05 06:00:51 PM PDT 24
Finished Jul 05 06:22:53 PM PDT 24
Peak memory 201916 kb
Host smart-049d7219-5bbe-4471-ad15-2354ef5a001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865876466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3865876466
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3238295249
Short name T149
Test name
Test status
Simulation time 487377448846 ps
CPU time 522.47 seconds
Started Jul 05 06:00:50 PM PDT 24
Finished Jul 05 06:09:33 PM PDT 24
Peak memory 201924 kb
Host smart-09655759-a0ce-48d4-ad08-1b2d22f8335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238295249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3238295249
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.901255977
Short name T695
Test name
Test status
Simulation time 495947313045 ps
CPU time 101.56 seconds
Started Jul 05 06:00:51 PM PDT 24
Finished Jul 05 06:02:33 PM PDT 24
Peak memory 201784 kb
Host smart-c1d6dd7d-e815-473d-b167-4656916fd2e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=901255977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.901255977
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.252926547
Short name T730
Test name
Test status
Simulation time 166060235574 ps
CPU time 104.26 seconds
Started Jul 05 06:00:58 PM PDT 24
Finished Jul 05 06:02:43 PM PDT 24
Peak memory 201972 kb
Host smart-c9ef3938-6387-4d2e-a953-9b98aa1a0ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252926547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.252926547
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3292970917
Short name T386
Test name
Test status
Simulation time 163167872212 ps
CPU time 91.5 seconds
Started Jul 05 06:00:50 PM PDT 24
Finished Jul 05 06:02:22 PM PDT 24
Peak memory 201916 kb
Host smart-f5c86ce7-50d0-41e1-9894-d3c44a66c3e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292970917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3292970917
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.431879538
Short name T12
Test name
Test status
Simulation time 350376424614 ps
CPU time 148.26 seconds
Started Jul 05 06:00:53 PM PDT 24
Finished Jul 05 06:03:22 PM PDT 24
Peak memory 201948 kb
Host smart-d334348f-ba6c-4b3d-ad6c-df3a8536168a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431879538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.431879538
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2779389351
Short name T385
Test name
Test status
Simulation time 406747356845 ps
CPU time 941.04 seconds
Started Jul 05 06:00:56 PM PDT 24
Finished Jul 05 06:16:37 PM PDT 24
Peak memory 201912 kb
Host smart-b266f0aa-f1d3-4591-8554-8e3506878c5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779389351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2779389351
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1369499305
Short name T203
Test name
Test status
Simulation time 113317424407 ps
CPU time 450.87 seconds
Started Jul 05 06:00:49 PM PDT 24
Finished Jul 05 06:08:20 PM PDT 24
Peak memory 202220 kb
Host smart-9afe86a6-9ec3-4acf-a112-40c37144e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369499305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1369499305
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1795426727
Short name T630
Test name
Test status
Simulation time 42424599240 ps
CPU time 92.8 seconds
Started Jul 05 06:00:51 PM PDT 24
Finished Jul 05 06:02:24 PM PDT 24
Peak memory 201724 kb
Host smart-5067f8bb-fd41-4429-aff3-d694f2183bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795426727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1795426727
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2073492488
Short name T622
Test name
Test status
Simulation time 5061526541 ps
CPU time 12.64 seconds
Started Jul 05 06:00:49 PM PDT 24
Finished Jul 05 06:01:02 PM PDT 24
Peak memory 201640 kb
Host smart-210049a7-e229-4641-8ff5-a1890e55ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073492488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2073492488
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.922771717
Short name T354
Test name
Test status
Simulation time 5828872381 ps
CPU time 10.87 seconds
Started Jul 05 06:00:58 PM PDT 24
Finished Jul 05 06:01:09 PM PDT 24
Peak memory 201732 kb
Host smart-e388bf10-6598-4c6a-bc00-9f7834b1891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922771717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.922771717
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.976678149
Short name T229
Test name
Test status
Simulation time 342677191116 ps
CPU time 153.77 seconds
Started Jul 05 06:00:59 PM PDT 24
Finished Jul 05 06:03:33 PM PDT 24
Peak memory 201864 kb
Host smart-ea0def59-8add-40b9-8aec-99498278491d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976678149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
976678149
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3928773609
Short name T28
Test name
Test status
Simulation time 81494430109 ps
CPU time 43.62 seconds
Started Jul 05 06:00:58 PM PDT 24
Finished Jul 05 06:01:42 PM PDT 24
Peak memory 210216 kb
Host smart-cf0a64dc-17d3-4c48-8022-5042ec1d2f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928773609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3928773609
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1188442625
Short name T506
Test name
Test status
Simulation time 412278145 ps
CPU time 1.56 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:53 PM PDT 24
Peak memory 201676 kb
Host smart-03c7b253-5657-4e85-aec9-ef2929071308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188442625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1188442625
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3155874621
Short name T175
Test name
Test status
Simulation time 363598834766 ps
CPU time 388.11 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 06:06:22 PM PDT 24
Peak memory 201908 kb
Host smart-2bfea4c6-64e4-4b71-bc23-590f7187453f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155874621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3155874621
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1639707186
Short name T771
Test name
Test status
Simulation time 185517303909 ps
CPU time 46.9 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:00:37 PM PDT 24
Peak memory 201832 kb
Host smart-a86a349e-4ee1-4fc1-b921-441411599e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639707186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1639707186
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3547591562
Short name T285
Test name
Test status
Simulation time 332607456512 ps
CPU time 130.27 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:02:03 PM PDT 24
Peak memory 201920 kb
Host smart-29bc1a52-82d6-4548-ad0c-3f384aaf3991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547591562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3547591562
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4162062550
Short name T748
Test name
Test status
Simulation time 323687521707 ps
CPU time 246.04 seconds
Started Jul 05 05:59:59 PM PDT 24
Finished Jul 05 06:04:06 PM PDT 24
Peak memory 201900 kb
Host smart-dad01139-cb0a-4c4e-a3f4-79bdfc448265
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162062550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4162062550
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3578465556
Short name T219
Test name
Test status
Simulation time 171158208541 ps
CPU time 86.09 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:01:18 PM PDT 24
Peak memory 201988 kb
Host smart-c1d1bb28-04cd-4add-bfab-7dad9f0e8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578465556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3578465556
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1567387085
Short name T606
Test name
Test status
Simulation time 488201723273 ps
CPU time 1128.53 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:18:39 PM PDT 24
Peak memory 201904 kb
Host smart-e5a75f6a-08da-4729-bfad-b29b58ab80d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567387085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1567387085
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.872534277
Short name T29
Test name
Test status
Simulation time 369250329203 ps
CPU time 708.28 seconds
Started Jul 05 05:59:42 PM PDT 24
Finished Jul 05 06:11:31 PM PDT 24
Peak memory 201928 kb
Host smart-1d7ba139-9845-4b25-8223-b97975ab743e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872534277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.872534277
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3498543442
Short name T679
Test name
Test status
Simulation time 200742080383 ps
CPU time 71.88 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:01:05 PM PDT 24
Peak memory 201904 kb
Host smart-a52a3472-0b9c-4e94-9783-ffc34915f90e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498543442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3498543442
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3024716979
Short name T10
Test name
Test status
Simulation time 26948941449 ps
CPU time 30.56 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:00:23 PM PDT 24
Peak memory 201600 kb
Host smart-2ccd6b0c-4535-4f77-9ce0-ea3e7715ac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024716979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3024716979
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2514950402
Short name T432
Test name
Test status
Simulation time 4675185156 ps
CPU time 4.2 seconds
Started Jul 05 05:59:55 PM PDT 24
Finished Jul 05 05:59:59 PM PDT 24
Peak memory 201716 kb
Host smart-2c8baba7-df88-4e0c-a99d-7fae051c1dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514950402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2514950402
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1981249489
Short name T63
Test name
Test status
Simulation time 3920888772 ps
CPU time 9.66 seconds
Started Jul 05 05:59:46 PM PDT 24
Finished Jul 05 05:59:57 PM PDT 24
Peak memory 217224 kb
Host smart-108c7960-75eb-4832-8f4a-8c1f155e7541
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981249489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1981249489
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.439373053
Short name T502
Test name
Test status
Simulation time 6100217217 ps
CPU time 4.58 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 05:59:55 PM PDT 24
Peak memory 201692 kb
Host smart-f80461a3-c50d-46d4-af62-758b201cbd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439373053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.439373053
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2182864801
Short name T466
Test name
Test status
Simulation time 28056150904 ps
CPU time 62.46 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 06:00:57 PM PDT 24
Peak memory 201716 kb
Host smart-0691d996-05e1-4a9c-870a-2d73b8d36ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182864801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2182864801
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1440313015
Short name T24
Test name
Test status
Simulation time 73257798489 ps
CPU time 171.72 seconds
Started Jul 05 06:00:02 PM PDT 24
Finished Jul 05 06:02:55 PM PDT 24
Peak memory 210532 kb
Host smart-d8e32ef7-7dd2-4c59-8bbe-2c9438a082f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440313015 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1440313015
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4156519035
Short name T558
Test name
Test status
Simulation time 376435808 ps
CPU time 1.06 seconds
Started Jul 05 06:01:03 PM PDT 24
Finished Jul 05 06:01:05 PM PDT 24
Peak memory 201660 kb
Host smart-e979cbca-fde7-4e55-84ce-546a943e99c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156519035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4156519035
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.145372885
Short name T177
Test name
Test status
Simulation time 502483369849 ps
CPU time 234.4 seconds
Started Jul 05 06:01:04 PM PDT 24
Finished Jul 05 06:04:59 PM PDT 24
Peak memory 201968 kb
Host smart-dac93a99-188a-4998-b3ad-47c903d86a38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145372885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.145372885
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1705253073
Short name T108
Test name
Test status
Simulation time 344528620324 ps
CPU time 408.58 seconds
Started Jul 05 06:01:06 PM PDT 24
Finished Jul 05 06:07:55 PM PDT 24
Peak memory 201860 kb
Host smart-5de2c22f-54a3-4a6d-a3e2-7cbeb046534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705253073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1705253073
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3371596581
Short name T247
Test name
Test status
Simulation time 162699019450 ps
CPU time 348.98 seconds
Started Jul 05 06:00:58 PM PDT 24
Finished Jul 05 06:06:48 PM PDT 24
Peak memory 201960 kb
Host smart-d4c25899-c2ef-49f4-923f-3b96d8abfaa3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371596581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3371596581
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2039032534
Short name T646
Test name
Test status
Simulation time 168847364134 ps
CPU time 394.22 seconds
Started Jul 05 06:00:56 PM PDT 24
Finished Jul 05 06:07:30 PM PDT 24
Peak memory 201952 kb
Host smart-1321d6cd-5d2d-47b1-b561-9d52b3a8e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039032534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2039032534
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.182781555
Short name T796
Test name
Test status
Simulation time 494119190065 ps
CPU time 1078.5 seconds
Started Jul 05 06:00:57 PM PDT 24
Finished Jul 05 06:18:56 PM PDT 24
Peak memory 201892 kb
Host smart-1a15967d-04db-49bd-8ecb-25a7c203db36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=182781555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.182781555
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.825708764
Short name T563
Test name
Test status
Simulation time 202733553907 ps
CPU time 414.58 seconds
Started Jul 05 06:01:02 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 201912 kb
Host smart-8e5c33a8-de01-461b-aeed-17d616341384
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825708764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.825708764
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.898882477
Short name T352
Test name
Test status
Simulation time 34140037223 ps
CPU time 79.48 seconds
Started Jul 05 06:01:06 PM PDT 24
Finished Jul 05 06:02:26 PM PDT 24
Peak memory 201732 kb
Host smart-fc545019-8717-4413-b06f-ab8b53a425c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898882477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.898882477
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1219543224
Short name T565
Test name
Test status
Simulation time 3343568272 ps
CPU time 2.81 seconds
Started Jul 05 06:01:04 PM PDT 24
Finished Jul 05 06:01:07 PM PDT 24
Peak memory 201732 kb
Host smart-284cd38c-2257-4908-93c6-b6d86284c66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219543224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1219543224
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2403825199
Short name T404
Test name
Test status
Simulation time 6179805307 ps
CPU time 3.92 seconds
Started Jul 05 06:00:56 PM PDT 24
Finished Jul 05 06:01:01 PM PDT 24
Peak memory 201720 kb
Host smart-6bdf243a-ee4f-4406-8703-0957d101864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403825199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2403825199
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2536932510
Short name T326
Test name
Test status
Simulation time 171961023486 ps
CPU time 177.38 seconds
Started Jul 05 06:01:05 PM PDT 24
Finished Jul 05 06:04:03 PM PDT 24
Peak memory 201976 kb
Host smart-7d53add0-2aa0-4eea-a017-fd216a3a52dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536932510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2536932510
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4025727144
Short name T521
Test name
Test status
Simulation time 16341834065 ps
CPU time 34.48 seconds
Started Jul 05 06:01:07 PM PDT 24
Finished Jul 05 06:01:42 PM PDT 24
Peak memory 202044 kb
Host smart-5aeecde2-29d1-4e16-874f-468cfeea808b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025727144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.4025727144
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2646740238
Short name T519
Test name
Test status
Simulation time 473086413 ps
CPU time 0.92 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:01:15 PM PDT 24
Peak memory 201672 kb
Host smart-b2f5adf7-e931-4cf4-ad1f-eea0ca9e1243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646740238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2646740238
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.167120514
Short name T418
Test name
Test status
Simulation time 169283334164 ps
CPU time 57.82 seconds
Started Jul 05 06:01:06 PM PDT 24
Finished Jul 05 06:02:04 PM PDT 24
Peak memory 201904 kb
Host smart-26b8b09c-6dad-4a8b-bea0-b471b46120f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167120514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.167120514
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3918224566
Short name T329
Test name
Test status
Simulation time 494765881874 ps
CPU time 410.8 seconds
Started Jul 05 06:01:06 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 201920 kb
Host smart-51adc88a-7390-4681-8da6-cdc57fbdee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918224566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3918224566
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.238706525
Short name T578
Test name
Test status
Simulation time 166523774369 ps
CPU time 94.62 seconds
Started Jul 05 06:03:23 PM PDT 24
Finished Jul 05 06:04:58 PM PDT 24
Peak memory 201840 kb
Host smart-a762bcb7-159c-4fc9-a6ca-15486752a176
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=238706525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.238706525
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.719975025
Short name T134
Test name
Test status
Simulation time 332864924193 ps
CPU time 662.66 seconds
Started Jul 05 06:01:08 PM PDT 24
Finished Jul 05 06:12:11 PM PDT 24
Peak memory 201936 kb
Host smart-b80b8b36-25ba-4434-924e-3552b15fcb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719975025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.719975025
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2092344705
Short name T659
Test name
Test status
Simulation time 493169708788 ps
CPU time 508.97 seconds
Started Jul 05 06:01:05 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 201892 kb
Host smart-033aacd6-11f2-4c02-947e-20a1536bd93c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092344705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2092344705
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3292007837
Short name T719
Test name
Test status
Simulation time 356637069290 ps
CPU time 797.74 seconds
Started Jul 05 06:01:05 PM PDT 24
Finished Jul 05 06:14:23 PM PDT 24
Peak memory 201988 kb
Host smart-bae3c551-8f68-4fe3-bc7d-bacccb288bc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292007837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3292007837
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3942847626
Short name T631
Test name
Test status
Simulation time 602944401550 ps
CPU time 1457.68 seconds
Started Jul 05 06:01:08 PM PDT 24
Finished Jul 05 06:25:26 PM PDT 24
Peak memory 201916 kb
Host smart-40702548-87a5-47d5-8e99-181455ef5a61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942847626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3942847626
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4100743180
Short name T575
Test name
Test status
Simulation time 67684569275 ps
CPU time 279.13 seconds
Started Jul 05 06:01:04 PM PDT 24
Finished Jul 05 06:05:43 PM PDT 24
Peak memory 202088 kb
Host smart-5d89fba7-229b-4928-a9a5-39ee089c76ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100743180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4100743180
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3295555616
Short name T794
Test name
Test status
Simulation time 32180664002 ps
CPU time 11.81 seconds
Started Jul 05 06:01:06 PM PDT 24
Finished Jul 05 06:01:18 PM PDT 24
Peak memory 201688 kb
Host smart-042dd384-cde4-4d78-8c68-a1f84a65423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295555616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3295555616
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.287097947
Short name T717
Test name
Test status
Simulation time 4329514840 ps
CPU time 4.47 seconds
Started Jul 05 06:01:07 PM PDT 24
Finished Jul 05 06:01:11 PM PDT 24
Peak memory 201628 kb
Host smart-cba0d8e1-2a12-49c3-a3e4-910ce48d6e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287097947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.287097947
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3519047984
Short name T750
Test name
Test status
Simulation time 6003959815 ps
CPU time 7.61 seconds
Started Jul 05 06:01:03 PM PDT 24
Finished Jul 05 06:01:11 PM PDT 24
Peak memory 201640 kb
Host smart-76ba8302-f71e-4f2f-91d7-b41992bfd97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519047984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3519047984
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2253051188
Short name T33
Test name
Test status
Simulation time 348390224809 ps
CPU time 1151.99 seconds
Started Jul 05 06:01:11 PM PDT 24
Finished Jul 05 06:20:24 PM PDT 24
Peak memory 202208 kb
Host smart-fce2dfe5-c890-4d9d-8ee2-7bd2b66ded1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253051188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2253051188
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.956930938
Short name T267
Test name
Test status
Simulation time 215886208677 ps
CPU time 180.98 seconds
Started Jul 05 06:01:10 PM PDT 24
Finished Jul 05 06:04:12 PM PDT 24
Peak memory 210576 kb
Host smart-9071a409-130c-4929-bb7f-3ff084c54a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956930938 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.956930938
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1555465831
Short name T407
Test name
Test status
Simulation time 338059600 ps
CPU time 1.02 seconds
Started Jul 05 06:01:15 PM PDT 24
Finished Jul 05 06:01:16 PM PDT 24
Peak memory 201660 kb
Host smart-985e9430-cc33-4000-9a1a-da1389d27f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555465831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1555465831
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.497215270
Short name T676
Test name
Test status
Simulation time 176530626434 ps
CPU time 205.11 seconds
Started Jul 05 06:01:12 PM PDT 24
Finished Jul 05 06:04:38 PM PDT 24
Peak memory 201928 kb
Host smart-45a75734-760a-4c54-86d0-742bde130e33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497215270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.497215270
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3698636416
Short name T135
Test name
Test status
Simulation time 350879390618 ps
CPU time 840.02 seconds
Started Jul 05 06:01:11 PM PDT 24
Finished Jul 05 06:15:11 PM PDT 24
Peak memory 201828 kb
Host smart-45c385e2-885e-4876-bf49-8a062d16d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698636416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3698636416
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2626882258
Short name T294
Test name
Test status
Simulation time 494615928763 ps
CPU time 1045.72 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:18:40 PM PDT 24
Peak memory 201936 kb
Host smart-90dd73af-8fe7-4f8c-9393-1f4ae7ab182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626882258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2626882258
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2093983869
Short name T509
Test name
Test status
Simulation time 331495814927 ps
CPU time 172.99 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:04:06 PM PDT 24
Peak memory 201904 kb
Host smart-e2adcfd8-b3d0-4404-9a0c-1f1497cc6554
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093983869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2093983869
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.107426163
Short name T172
Test name
Test status
Simulation time 494690047793 ps
CPU time 159.98 seconds
Started Jul 05 06:01:12 PM PDT 24
Finished Jul 05 06:03:53 PM PDT 24
Peak memory 201924 kb
Host smart-23d6fd05-d325-44fb-915a-6b7427df081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107426163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.107426163
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1635165569
Short name T443
Test name
Test status
Simulation time 499795601822 ps
CPU time 253.12 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:05:27 PM PDT 24
Peak memory 201832 kb
Host smart-8a588f6a-bf7c-4ec4-8afe-aadb01d3a807
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635165569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1635165569
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3292334641
Short name T292
Test name
Test status
Simulation time 173174032077 ps
CPU time 398.35 seconds
Started Jul 05 06:01:15 PM PDT 24
Finished Jul 05 06:07:53 PM PDT 24
Peak memory 201924 kb
Host smart-2b7359b1-80f8-4fdb-aaec-051852162990
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292334641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3292334641
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.292139700
Short name T472
Test name
Test status
Simulation time 402850031078 ps
CPU time 97.58 seconds
Started Jul 05 06:01:11 PM PDT 24
Finished Jul 05 06:02:49 PM PDT 24
Peak memory 201892 kb
Host smart-014532b8-4922-4f11-b167-6224c0ebda7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292139700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.292139700
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1622561326
Short name T493
Test name
Test status
Simulation time 90828484382 ps
CPU time 473.42 seconds
Started Jul 05 06:01:11 PM PDT 24
Finished Jul 05 06:09:05 PM PDT 24
Peak memory 202280 kb
Host smart-2918d76a-503f-479f-a2ce-bd4e85ae9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622561326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1622561326
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3561461364
Short name T358
Test name
Test status
Simulation time 28304658922 ps
CPU time 8.58 seconds
Started Jul 05 06:01:11 PM PDT 24
Finished Jul 05 06:01:21 PM PDT 24
Peak memory 201712 kb
Host smart-24fac435-62fc-4738-aee8-54156fdf23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561461364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3561461364
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3431915507
Short name T373
Test name
Test status
Simulation time 4772767993 ps
CPU time 10.54 seconds
Started Jul 05 06:01:11 PM PDT 24
Finished Jul 05 06:01:22 PM PDT 24
Peak memory 201636 kb
Host smart-018fbfa4-ee6f-4825-b5f0-9c4067bc825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431915507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3431915507
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.706763355
Short name T527
Test name
Test status
Simulation time 5539067493 ps
CPU time 4.02 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:01:18 PM PDT 24
Peak memory 201720 kb
Host smart-96dc0f43-051f-4371-b78c-68f1f1f90d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706763355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.706763355
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.532641290
Short name T313
Test name
Test status
Simulation time 333267280544 ps
CPU time 558.52 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 210376 kb
Host smart-0ad88df9-5f9c-4911-af68-39570480a704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532641290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
532641290
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1640866337
Short name T475
Test name
Test status
Simulation time 160158006616 ps
CPU time 166.6 seconds
Started Jul 05 06:01:10 PM PDT 24
Finished Jul 05 06:03:57 PM PDT 24
Peak memory 210576 kb
Host smart-6044a9fb-8383-49b8-9756-81c907465769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640866337 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1640866337
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3076830283
Short name T585
Test name
Test status
Simulation time 497902881 ps
CPU time 1.72 seconds
Started Jul 05 06:01:18 PM PDT 24
Finished Jul 05 06:01:20 PM PDT 24
Peak memory 201664 kb
Host smart-1f98c6c9-fc45-45ee-b024-49b9581599b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076830283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3076830283
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.885777842
Short name T228
Test name
Test status
Simulation time 512397037534 ps
CPU time 100.89 seconds
Started Jul 05 06:01:21 PM PDT 24
Finished Jul 05 06:03:02 PM PDT 24
Peak memory 201896 kb
Host smart-c33a20be-1c18-4ae6-bbef-4f5809721a11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885777842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.885777842
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2811759237
Short name T308
Test name
Test status
Simulation time 161374770612 ps
CPU time 166.38 seconds
Started Jul 05 06:01:22 PM PDT 24
Finished Jul 05 06:04:09 PM PDT 24
Peak memory 201876 kb
Host smart-251a2179-a129-4345-b777-2bbbc00127cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811759237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2811759237
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2368336985
Short name T232
Test name
Test status
Simulation time 337157926198 ps
CPU time 784.28 seconds
Started Jul 05 06:01:18 PM PDT 24
Finished Jul 05 06:14:23 PM PDT 24
Peak memory 201952 kb
Host smart-c6e886a4-159a-4e9e-a716-8703916c3d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368336985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2368336985
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3025440633
Short name T505
Test name
Test status
Simulation time 501792657999 ps
CPU time 990.77 seconds
Started Jul 05 06:01:22 PM PDT 24
Finished Jul 05 06:17:53 PM PDT 24
Peak memory 201872 kb
Host smart-c9211c05-d154-4f22-9dc3-1b600ecff88d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025440633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3025440633
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3251996079
Short name T743
Test name
Test status
Simulation time 490572471824 ps
CPU time 1129.05 seconds
Started Jul 05 06:01:12 PM PDT 24
Finished Jul 05 06:20:02 PM PDT 24
Peak memory 201912 kb
Host smart-c463ff76-ff73-46a9-8811-8e777844e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251996079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3251996079
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1629657527
Short name T592
Test name
Test status
Simulation time 327064940808 ps
CPU time 197.83 seconds
Started Jul 05 06:01:13 PM PDT 24
Finished Jul 05 06:04:32 PM PDT 24
Peak memory 201908 kb
Host smart-6f7cc566-57dd-4685-ac71-af65c74ac246
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629657527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1629657527
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1403887316
Short name T145
Test name
Test status
Simulation time 531091235978 ps
CPU time 1142.87 seconds
Started Jul 05 06:01:21 PM PDT 24
Finished Jul 05 06:20:24 PM PDT 24
Peak memory 201928 kb
Host smart-e3459ea3-7ed3-4369-bc44-8a11ae6f5af0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403887316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1403887316
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1025011414
Short name T638
Test name
Test status
Simulation time 621324206200 ps
CPU time 275.83 seconds
Started Jul 05 06:01:24 PM PDT 24
Finished Jul 05 06:06:00 PM PDT 24
Peak memory 201956 kb
Host smart-ef773e85-9049-4510-9dd7-7f0528c32d86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025011414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1025011414
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.99125934
Short name T211
Test name
Test status
Simulation time 96700801519 ps
CPU time 504.23 seconds
Started Jul 05 06:01:22 PM PDT 24
Finished Jul 05 06:09:47 PM PDT 24
Peak memory 202216 kb
Host smart-b41745bf-1ec4-473c-a8d9-b1bf5baa83bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99125934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.99125934
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1660840936
Short name T724
Test name
Test status
Simulation time 27614691202 ps
CPU time 65.76 seconds
Started Jul 05 06:01:23 PM PDT 24
Finished Jul 05 06:02:29 PM PDT 24
Peak memory 201680 kb
Host smart-3e0dca97-bb62-417c-b9de-86a50b509be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660840936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1660840936
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1242959635
Short name T409
Test name
Test status
Simulation time 3562417858 ps
CPU time 4.94 seconds
Started Jul 05 06:01:17 PM PDT 24
Finished Jul 05 06:01:22 PM PDT 24
Peak memory 201648 kb
Host smart-2d38ee8c-3e6e-4c22-8e11-f7127aa373a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242959635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1242959635
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4285154930
Short name T662
Test name
Test status
Simulation time 5857385105 ps
CPU time 14.59 seconds
Started Jul 05 06:01:12 PM PDT 24
Finished Jul 05 06:01:27 PM PDT 24
Peak memory 201696 kb
Host smart-472190f4-3ac5-46d2-b511-f1288d4af77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285154930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4285154930
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3411870135
Short name T689
Test name
Test status
Simulation time 28506051492 ps
CPU time 16.98 seconds
Started Jul 05 06:01:24 PM PDT 24
Finished Jul 05 06:01:42 PM PDT 24
Peak memory 201704 kb
Host smart-2bfe7f8e-078e-44fd-a71c-4a97e1f93ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411870135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3411870135
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4196380002
Short name T299
Test name
Test status
Simulation time 109179369834 ps
CPU time 210.01 seconds
Started Jul 05 06:01:22 PM PDT 24
Finished Jul 05 06:04:52 PM PDT 24
Peak memory 210324 kb
Host smart-e918b42d-eef6-4ec5-af3a-1806a4bdbded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196380002 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4196380002
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.516957144
Short name T446
Test name
Test status
Simulation time 317959639 ps
CPU time 1.25 seconds
Started Jul 05 06:01:26 PM PDT 24
Finished Jul 05 06:01:27 PM PDT 24
Peak memory 201676 kb
Host smart-9eaedc9f-8b38-4b71-872f-04237fcd0f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516957144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.516957144
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3073971092
Short name T241
Test name
Test status
Simulation time 328777238925 ps
CPU time 774.12 seconds
Started Jul 05 06:01:21 PM PDT 24
Finished Jul 05 06:14:16 PM PDT 24
Peak memory 201920 kb
Host smart-e13c6eaa-01c6-45e5-b736-da1c75a2ae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073971092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3073971092
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3289636191
Short name T193
Test name
Test status
Simulation time 488825457064 ps
CPU time 264.37 seconds
Started Jul 05 06:01:20 PM PDT 24
Finished Jul 05 06:05:44 PM PDT 24
Peak memory 201908 kb
Host smart-0a394fe3-d34c-4d76-b39e-f5b3f66d2be2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289636191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3289636191
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.426507958
Short name T661
Test name
Test status
Simulation time 324203558849 ps
CPU time 92.7 seconds
Started Jul 05 06:01:20 PM PDT 24
Finished Jul 05 06:02:53 PM PDT 24
Peak memory 201980 kb
Host smart-e45a74f7-6540-4e98-aff2-2dadaa41a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426507958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.426507958
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3228914138
Short name T161
Test name
Test status
Simulation time 497069077330 ps
CPU time 1150.59 seconds
Started Jul 05 06:01:22 PM PDT 24
Finished Jul 05 06:20:33 PM PDT 24
Peak memory 201868 kb
Host smart-0218d480-147f-48aa-b8eb-d853e85849af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228914138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3228914138
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.819082049
Short name T31
Test name
Test status
Simulation time 359854078180 ps
CPU time 192.99 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:04:45 PM PDT 24
Peak memory 201912 kb
Host smart-207f1015-4a08-4d9c-b711-1c2ec60fc322
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819082049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.819082049
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3827537045
Short name T445
Test name
Test status
Simulation time 593098467758 ps
CPU time 1376.76 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:24:30 PM PDT 24
Peak memory 201912 kb
Host smart-eae9843a-2957-4c8f-8b85-4faa6905965f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827537045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3827537045
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2359880208
Short name T4
Test name
Test status
Simulation time 110619914293 ps
CPU time 436.67 seconds
Started Jul 05 06:01:27 PM PDT 24
Finished Jul 05 06:08:44 PM PDT 24
Peak memory 202212 kb
Host smart-f4e996c7-8beb-4984-994a-04b6c119b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359880208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2359880208
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1919212256
Short name T618
Test name
Test status
Simulation time 44764643786 ps
CPU time 103.93 seconds
Started Jul 05 06:01:30 PM PDT 24
Finished Jul 05 06:03:14 PM PDT 24
Peak memory 201624 kb
Host smart-c3f27733-de7b-41f2-8d82-e658edbfdcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919212256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1919212256
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.22887817
Short name T684
Test name
Test status
Simulation time 4953149000 ps
CPU time 4.16 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:01:37 PM PDT 24
Peak memory 201716 kb
Host smart-6aab8dfc-cfbf-408f-a89c-a29ed131bcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22887817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.22887817
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.951476367
Short name T413
Test name
Test status
Simulation time 5742447495 ps
CPU time 13.21 seconds
Started Jul 05 06:01:24 PM PDT 24
Finished Jul 05 06:01:37 PM PDT 24
Peak memory 201716 kb
Host smart-a3134ff4-d73a-4950-9b93-c49f703601d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951476367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.951476367
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.920473657
Short name T657
Test name
Test status
Simulation time 786925873468 ps
CPU time 828.99 seconds
Started Jul 05 06:01:30 PM PDT 24
Finished Jul 05 06:15:19 PM PDT 24
Peak memory 201916 kb
Host smart-24578fc2-2c41-401c-a876-5e521e427d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920473657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
920473657
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.598295588
Short name T305
Test name
Test status
Simulation time 99154201749 ps
CPU time 263.61 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:05:56 PM PDT 24
Peak memory 210600 kb
Host smart-7b7738fa-176b-42e6-8217-e9410be53c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598295588 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.598295588
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2759764166
Short name T518
Test name
Test status
Simulation time 389067447 ps
CPU time 0.82 seconds
Started Jul 05 06:01:36 PM PDT 24
Finished Jul 05 06:01:38 PM PDT 24
Peak memory 201668 kb
Host smart-e5a959a6-71be-41a7-bde6-f5dd8857b8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759764166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2759764166
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1228230871
Short name T427
Test name
Test status
Simulation time 173570427308 ps
CPU time 122.12 seconds
Started Jul 05 06:01:29 PM PDT 24
Finished Jul 05 06:03:32 PM PDT 24
Peak memory 201828 kb
Host smart-e1d9dfca-6209-472a-a05c-af384dc6164e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228230871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1228230871
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1916380878
Short name T512
Test name
Test status
Simulation time 333739354602 ps
CPU time 415.49 seconds
Started Jul 05 06:01:38 PM PDT 24
Finished Jul 05 06:08:34 PM PDT 24
Peak memory 201908 kb
Host smart-3794e6f2-24ce-4b4b-88fd-6f433e344361
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916380878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1916380878
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3508434211
Short name T188
Test name
Test status
Simulation time 483697902996 ps
CPU time 238.89 seconds
Started Jul 05 06:01:28 PM PDT 24
Finished Jul 05 06:05:27 PM PDT 24
Peak memory 201872 kb
Host smart-48ab9612-ed16-4fe7-8f95-4369775a54d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508434211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3508434211
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1845486499
Short name T433
Test name
Test status
Simulation time 169372610106 ps
CPU time 390.02 seconds
Started Jul 05 06:01:31 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 201900 kb
Host smart-f7f010df-4bd2-430f-af34-6dbf73e6b802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845486499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1845486499
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3630057375
Short name T770
Test name
Test status
Simulation time 353364102254 ps
CPU time 169.64 seconds
Started Jul 05 06:01:30 PM PDT 24
Finished Jul 05 06:04:20 PM PDT 24
Peak memory 201980 kb
Host smart-d4bf5d0d-86ac-4c1b-9c97-895744ffc7cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630057375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3630057375
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1042221938
Short name T380
Test name
Test status
Simulation time 615809863489 ps
CPU time 1338.84 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:23:52 PM PDT 24
Peak memory 201908 kb
Host smart-8ae45ccb-9658-412e-a062-1b71fbc1bdef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042221938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1042221938
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1073525163
Short name T340
Test name
Test status
Simulation time 67152895777 ps
CPU time 330.76 seconds
Started Jul 05 06:01:28 PM PDT 24
Finished Jul 05 06:06:59 PM PDT 24
Peak memory 202216 kb
Host smart-92c31d43-67f1-41d5-bd0f-a34ce65aaa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073525163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1073525163
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1182664694
Short name T795
Test name
Test status
Simulation time 38446786375 ps
CPU time 88.15 seconds
Started Jul 05 06:01:31 PM PDT 24
Finished Jul 05 06:02:59 PM PDT 24
Peak memory 201716 kb
Host smart-92115275-47e5-4fb2-9747-b4e92ed0e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182664694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1182664694
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3659904890
Short name T428
Test name
Test status
Simulation time 3481171635 ps
CPU time 9.22 seconds
Started Jul 05 06:01:30 PM PDT 24
Finished Jul 05 06:01:39 PM PDT 24
Peak memory 201720 kb
Host smart-a6ff19a7-3507-45f7-b48a-6ef9fd7629c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659904890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3659904890
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.385508413
Short name T524
Test name
Test status
Simulation time 5708370084 ps
CPU time 14.15 seconds
Started Jul 05 06:01:28 PM PDT 24
Finished Jul 05 06:01:43 PM PDT 24
Peak memory 201700 kb
Host smart-3cb76297-78cc-4465-8e48-81712d7889ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385508413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.385508413
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2067213298
Short name T98
Test name
Test status
Simulation time 9257626207 ps
CPU time 21.85 seconds
Started Jul 05 06:01:35 PM PDT 24
Finished Jul 05 06:01:57 PM PDT 24
Peak memory 201720 kb
Host smart-67233450-8f0e-41f0-97fe-b3e96491c6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067213298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2067213298
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2251399656
Short name T253
Test name
Test status
Simulation time 67438027718 ps
CPU time 76.06 seconds
Started Jul 05 06:01:31 PM PDT 24
Finished Jul 05 06:02:47 PM PDT 24
Peak memory 210228 kb
Host smart-b004aa4a-adaf-4e2f-8b64-6be53b8a252c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251399656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2251399656
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1629342400
Short name T503
Test name
Test status
Simulation time 379158860 ps
CPU time 0.82 seconds
Started Jul 05 06:01:45 PM PDT 24
Finished Jul 05 06:01:46 PM PDT 24
Peak memory 201668 kb
Host smart-872fa410-bc13-428e-8444-a8d2bd2ef5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629342400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1629342400
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3058355653
Short name T653
Test name
Test status
Simulation time 168467591084 ps
CPU time 40.64 seconds
Started Jul 05 06:01:37 PM PDT 24
Finished Jul 05 06:02:18 PM PDT 24
Peak memory 201916 kb
Host smart-bac4c01f-5ab7-474a-b380-50aac038462f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058355653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3058355653
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.948183427
Short name T42
Test name
Test status
Simulation time 342383425463 ps
CPU time 799.24 seconds
Started Jul 05 06:01:37 PM PDT 24
Finished Jul 05 06:14:56 PM PDT 24
Peak memory 201920 kb
Host smart-29429585-982f-4f09-a696-706e9f85a9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948183427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.948183427
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2208965520
Short name T625
Test name
Test status
Simulation time 163649125092 ps
CPU time 179.73 seconds
Started Jul 05 06:01:32 PM PDT 24
Finished Jul 05 06:04:33 PM PDT 24
Peak memory 201920 kb
Host smart-8e0fa63f-f22d-49e5-b11d-9a450a94b5dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208965520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2208965520
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3008173780
Short name T396
Test name
Test status
Simulation time 163135991260 ps
CPU time 333.63 seconds
Started Jul 05 06:01:36 PM PDT 24
Finished Jul 05 06:07:11 PM PDT 24
Peak memory 201984 kb
Host smart-0f1f3368-8796-4907-bdc0-4ba35c0b943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008173780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3008173780
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1070835803
Short name T30
Test name
Test status
Simulation time 327416519314 ps
CPU time 181.95 seconds
Started Jul 05 06:01:35 PM PDT 24
Finished Jul 05 06:04:37 PM PDT 24
Peak memory 201976 kb
Host smart-bba42aa3-783c-45f2-879e-490ce63440dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070835803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1070835803
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.348957806
Short name T499
Test name
Test status
Simulation time 383753188549 ps
CPU time 819.88 seconds
Started Jul 05 06:01:36 PM PDT 24
Finished Jul 05 06:15:17 PM PDT 24
Peak memory 201840 kb
Host smart-eca9f136-3a8f-4663-b725-4ee0662943d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348957806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.348957806
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2580137444
Short name T377
Test name
Test status
Simulation time 203170643452 ps
CPU time 106.42 seconds
Started Jul 05 06:01:34 PM PDT 24
Finished Jul 05 06:03:21 PM PDT 24
Peak memory 201864 kb
Host smart-9f570f93-f0eb-476b-bd23-60ee357dae15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580137444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2580137444
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2746432071
Short name T346
Test name
Test status
Simulation time 109310084015 ps
CPU time 589.84 seconds
Started Jul 05 06:01:41 PM PDT 24
Finished Jul 05 06:11:32 PM PDT 24
Peak memory 202224 kb
Host smart-7a6f2738-9016-4ee3-b0ce-4244e8e9a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746432071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2746432071
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2999476981
Short name T734
Test name
Test status
Simulation time 24594308311 ps
CPU time 5.04 seconds
Started Jul 05 06:01:43 PM PDT 24
Finished Jul 05 06:01:48 PM PDT 24
Peak memory 201728 kb
Host smart-f619a31a-ee13-4dc0-86e2-5d8ebf9aaacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999476981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2999476981
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.78978918
Short name T416
Test name
Test status
Simulation time 3434473020 ps
CPU time 1.35 seconds
Started Jul 05 06:01:40 PM PDT 24
Finished Jul 05 06:01:42 PM PDT 24
Peak memory 201636 kb
Host smart-77666b8f-0199-4101-9f87-bdc7080f00ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78978918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.78978918
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1011457903
Short name T382
Test name
Test status
Simulation time 5972561055 ps
CPU time 5.2 seconds
Started Jul 05 06:01:36 PM PDT 24
Finished Jul 05 06:01:41 PM PDT 24
Peak memory 201740 kb
Host smart-bd9fcbb8-7b69-41da-8d57-4ea9015f636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011457903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1011457903
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2146683160
Short name T548
Test name
Test status
Simulation time 90701989583 ps
CPU time 208.27 seconds
Started Jul 05 06:01:44 PM PDT 24
Finished Jul 05 06:05:13 PM PDT 24
Peak memory 201904 kb
Host smart-fa74489d-c655-4073-8dad-6fdbed000e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146683160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2146683160
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.619810607
Short name T21
Test name
Test status
Simulation time 99862356558 ps
CPU time 95.38 seconds
Started Jul 05 06:01:41 PM PDT 24
Finished Jul 05 06:03:17 PM PDT 24
Peak memory 218728 kb
Host smart-3c63dd1c-3d6a-43ae-9e2c-1c09c5888f0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619810607 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.619810607
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2044218651
Short name T68
Test name
Test status
Simulation time 320043389 ps
CPU time 1.34 seconds
Started Jul 05 06:01:51 PM PDT 24
Finished Jul 05 06:01:53 PM PDT 24
Peak memory 201668 kb
Host smart-62a53e6c-2d79-4373-85ca-41d7ff83be8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044218651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2044218651
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.398131650
Short name T238
Test name
Test status
Simulation time 432207893371 ps
CPU time 473.24 seconds
Started Jul 05 06:01:51 PM PDT 24
Finished Jul 05 06:09:45 PM PDT 24
Peak memory 201920 kb
Host smart-032e283f-b5ae-4954-a21a-35e31ac2c432
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398131650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.398131650
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2086390525
Short name T95
Test name
Test status
Simulation time 164753148837 ps
CPU time 66.84 seconds
Started Jul 05 06:01:50 PM PDT 24
Finished Jul 05 06:02:57 PM PDT 24
Peak memory 201928 kb
Host smart-cfe3b6d9-be44-4250-8d08-03d4d60aaa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086390525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2086390525
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2818387893
Short name T196
Test name
Test status
Simulation time 494958139482 ps
CPU time 274.68 seconds
Started Jul 05 06:01:43 PM PDT 24
Finished Jul 05 06:06:18 PM PDT 24
Peak memory 201864 kb
Host smart-81cfcb2f-e24a-4ec0-a2a3-6de0d3889d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818387893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2818387893
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2876068021
Short name T494
Test name
Test status
Simulation time 480740474687 ps
CPU time 157.78 seconds
Started Jul 05 06:01:42 PM PDT 24
Finished Jul 05 06:04:20 PM PDT 24
Peak memory 201880 kb
Host smart-d167baa4-1056-4189-86ca-51431b4df269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876068021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2876068021
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2651505412
Short name T312
Test name
Test status
Simulation time 326210901587 ps
CPU time 204.29 seconds
Started Jul 05 06:01:39 PM PDT 24
Finished Jul 05 06:05:04 PM PDT 24
Peak memory 201896 kb
Host smart-884e758c-1b04-4cbd-a884-e03c3af749f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651505412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2651505412
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2392969374
Short name T468
Test name
Test status
Simulation time 488908103167 ps
CPU time 551.31 seconds
Started Jul 05 06:01:43 PM PDT 24
Finished Jul 05 06:10:55 PM PDT 24
Peak memory 201908 kb
Host smart-8566ed70-37bd-49fd-9ca0-d3f90642e7b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392969374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2392969374
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2943134429
Short name T682
Test name
Test status
Simulation time 204291527443 ps
CPU time 457.76 seconds
Started Jul 05 06:01:42 PM PDT 24
Finished Jul 05 06:09:20 PM PDT 24
Peak memory 201928 kb
Host smart-a808fd30-8e9e-413d-b41e-e4f5b339f786
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943134429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2943134429
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2893886777
Short name T365
Test name
Test status
Simulation time 411875013615 ps
CPU time 894.96 seconds
Started Jul 05 06:01:50 PM PDT 24
Finished Jul 05 06:16:45 PM PDT 24
Peak memory 201816 kb
Host smart-32d260e0-2142-4694-b3a5-2c71c49e13e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893886777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2893886777
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2106710715
Short name T451
Test name
Test status
Simulation time 113715568682 ps
CPU time 577.31 seconds
Started Jul 05 06:01:47 PM PDT 24
Finished Jul 05 06:11:25 PM PDT 24
Peak memory 202128 kb
Host smart-3e487857-0d39-481b-b468-68794e4130dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106710715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2106710715
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2384043625
Short name T551
Test name
Test status
Simulation time 43809279781 ps
CPU time 24.42 seconds
Started Jul 05 06:01:50 PM PDT 24
Finished Jul 05 06:02:14 PM PDT 24
Peak memory 201696 kb
Host smart-abb427ba-8b01-4c6f-9351-608177d912b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384043625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2384043625
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.197194027
Short name T476
Test name
Test status
Simulation time 5104644707 ps
CPU time 11.49 seconds
Started Jul 05 06:01:51 PM PDT 24
Finished Jul 05 06:02:02 PM PDT 24
Peak memory 201728 kb
Host smart-2b220cd4-ed71-493f-8715-747765eba4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197194027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.197194027
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2046085486
Short name T765
Test name
Test status
Simulation time 5657515383 ps
CPU time 4.1 seconds
Started Jul 05 06:01:42 PM PDT 24
Finished Jul 05 06:01:47 PM PDT 24
Peak memory 201684 kb
Host smart-58cbc46f-f7cc-4d72-a584-35a6e3a8ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046085486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2046085486
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3469885425
Short name T463
Test name
Test status
Simulation time 128740319773 ps
CPU time 658.56 seconds
Started Jul 05 06:01:50 PM PDT 24
Finished Jul 05 06:12:49 PM PDT 24
Peak memory 202272 kb
Host smart-de39d1c0-3e0c-4473-9b74-f4a0fc99b2b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469885425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3469885425
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1954769537
Short name T398
Test name
Test status
Simulation time 488105912 ps
CPU time 0.87 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:01:58 PM PDT 24
Peak memory 201664 kb
Host smart-d2deed1b-3393-4b4e-b9be-5cfb309f0b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954769537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1954769537
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3150865040
Short name T712
Test name
Test status
Simulation time 163111468406 ps
CPU time 388.03 seconds
Started Jul 05 06:01:54 PM PDT 24
Finished Jul 05 06:08:23 PM PDT 24
Peak memory 201896 kb
Host smart-e6bf60b3-92cc-4cb3-b20e-e5e3479e0f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150865040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3150865040
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1154962576
Short name T224
Test name
Test status
Simulation time 167546929734 ps
CPU time 99.38 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:03:36 PM PDT 24
Peak memory 201924 kb
Host smart-1a052f4f-0a18-4438-bcd6-e6759d6fd335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154962576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1154962576
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2541213757
Short name T104
Test name
Test status
Simulation time 331746347128 ps
CPU time 746.81 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:14:23 PM PDT 24
Peak memory 201904 kb
Host smart-f2049f80-6d73-401a-8c24-89a3806ecab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541213757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2541213757
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1268981316
Short name T143
Test name
Test status
Simulation time 319739308596 ps
CPU time 283.26 seconds
Started Jul 05 06:01:49 PM PDT 24
Finished Jul 05 06:06:32 PM PDT 24
Peak memory 201908 kb
Host smart-f793783d-f0d8-446f-93a5-f7c090c2c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268981316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1268981316
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2065381729
Short name T25
Test name
Test status
Simulation time 489058787290 ps
CPU time 269.44 seconds
Started Jul 05 06:01:51 PM PDT 24
Finished Jul 05 06:06:21 PM PDT 24
Peak memory 201908 kb
Host smart-117bbbcb-b341-4008-8082-6ff7f14ac1ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065381729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2065381729
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.4063318524
Short name T262
Test name
Test status
Simulation time 387866816584 ps
CPU time 830.62 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:15:47 PM PDT 24
Peak memory 201928 kb
Host smart-1ad1d17d-a1e5-4bdf-b600-b02dfeb036fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063318524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.4063318524
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1100407152
Short name T497
Test name
Test status
Simulation time 599676606192 ps
CPU time 341.97 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:07:38 PM PDT 24
Peak memory 201904 kb
Host smart-779ad0ac-c592-4d13-adf7-c338910a1dea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100407152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1100407152
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3356051503
Short name T465
Test name
Test status
Simulation time 72358281028 ps
CPU time 236.59 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:05:53 PM PDT 24
Peak memory 202200 kb
Host smart-90c20c82-d888-42e5-848d-95401d357a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356051503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3356051503
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3996470789
Short name T480
Test name
Test status
Simulation time 40585864547 ps
CPU time 22.47 seconds
Started Jul 05 06:01:57 PM PDT 24
Finished Jul 05 06:02:20 PM PDT 24
Peak memory 201728 kb
Host smart-b7026e1b-a140-4888-9db2-8d24ebf699b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996470789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3996470789
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.610188979
Short name T537
Test name
Test status
Simulation time 5405942289 ps
CPU time 2.25 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:01:59 PM PDT 24
Peak memory 201712 kb
Host smart-111a217c-3d9e-416b-9c09-d5c46d7055f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610188979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.610188979
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3383219025
Short name T580
Test name
Test status
Simulation time 6126285573 ps
CPU time 13.5 seconds
Started Jul 05 06:01:51 PM PDT 24
Finished Jul 05 06:02:05 PM PDT 24
Peak memory 201740 kb
Host smart-a80bf97b-14be-41b5-80c9-9f6022e94092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383219025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3383219025
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4218590229
Short name T106
Test name
Test status
Simulation time 330088721800 ps
CPU time 743.35 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:14:20 PM PDT 24
Peak memory 201872 kb
Host smart-fa89ec1e-9c2e-4239-8d7a-efcf300ca085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218590229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4218590229
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1375606736
Short name T93
Test name
Test status
Simulation time 49467580630 ps
CPU time 102.28 seconds
Started Jul 05 06:01:57 PM PDT 24
Finished Jul 05 06:03:40 PM PDT 24
Peak memory 210480 kb
Host smart-f8f11f3e-30b0-469f-92ee-37f5a444f748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375606736 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1375606736
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.31553644
Short name T479
Test name
Test status
Simulation time 400255209 ps
CPU time 1.32 seconds
Started Jul 05 06:02:12 PM PDT 24
Finished Jul 05 06:02:14 PM PDT 24
Peak memory 201660 kb
Host smart-501504cf-c167-4173-8424-ccc8b0222540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31553644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.31553644
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3967085552
Short name T142
Test name
Test status
Simulation time 325427656369 ps
CPU time 624 seconds
Started Jul 05 06:02:05 PM PDT 24
Finished Jul 05 06:12:29 PM PDT 24
Peak memory 201924 kb
Host smart-d0ad5c8d-b786-44df-85cf-40ec2b6e4945
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967085552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3967085552
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.441375632
Short name T613
Test name
Test status
Simulation time 500816723789 ps
CPU time 569.95 seconds
Started Jul 05 06:02:04 PM PDT 24
Finished Jul 05 06:11:35 PM PDT 24
Peak memory 201896 kb
Host smart-2f0d86b0-7264-4f34-88fd-46e9d2190753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441375632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.441375632
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.443839007
Short name T113
Test name
Test status
Simulation time 487130750492 ps
CPU time 602.62 seconds
Started Jul 05 06:02:04 PM PDT 24
Finished Jul 05 06:12:07 PM PDT 24
Peak memory 201888 kb
Host smart-ba0eb083-2309-491a-b41a-8d4bb880ade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443839007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.443839007
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2478119618
Short name T157
Test name
Test status
Simulation time 496417300829 ps
CPU time 308.91 seconds
Started Jul 05 06:02:02 PM PDT 24
Finished Jul 05 06:07:12 PM PDT 24
Peak memory 201796 kb
Host smart-2b177c73-6a80-4772-ae36-c0240e78733e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478119618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2478119618
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.516107109
Short name T252
Test name
Test status
Simulation time 487942333045 ps
CPU time 117.3 seconds
Started Jul 05 06:02:06 PM PDT 24
Finished Jul 05 06:04:04 PM PDT 24
Peak memory 201920 kb
Host smart-301137ce-8193-471e-9021-a033d8796847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516107109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.516107109
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1213638789
Short name T584
Test name
Test status
Simulation time 163820216998 ps
CPU time 38.06 seconds
Started Jul 05 06:02:04 PM PDT 24
Finished Jul 05 06:02:42 PM PDT 24
Peak memory 201908 kb
Host smart-22dfeeef-f666-4b9f-8612-55d45265af9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213638789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1213638789
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3391535087
Short name T707
Test name
Test status
Simulation time 416428494377 ps
CPU time 231.18 seconds
Started Jul 05 06:02:05 PM PDT 24
Finished Jul 05 06:05:57 PM PDT 24
Peak memory 201928 kb
Host smart-b8502f7a-3806-4b28-ad86-e155fd7375c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391535087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3391535087
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3856801525
Short name T555
Test name
Test status
Simulation time 605784102493 ps
CPU time 91.86 seconds
Started Jul 05 06:02:04 PM PDT 24
Finished Jul 05 06:03:36 PM PDT 24
Peak memory 201904 kb
Host smart-47cbf890-1306-4803-9e7f-b84ecc996966
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856801525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3856801525
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1327892145
Short name T703
Test name
Test status
Simulation time 70845437488 ps
CPU time 286.9 seconds
Started Jul 05 06:02:00 PM PDT 24
Finished Jul 05 06:06:47 PM PDT 24
Peak memory 202280 kb
Host smart-d3c85437-78c8-407a-8a53-e8779e1b072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327892145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1327892145
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3592066320
Short name T648
Test name
Test status
Simulation time 45290056795 ps
CPU time 26.03 seconds
Started Jul 05 06:02:01 PM PDT 24
Finished Jul 05 06:02:28 PM PDT 24
Peak memory 201640 kb
Host smart-8d242d04-1baa-4d9a-a326-de5a9c6a3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592066320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3592066320
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.924314639
Short name T417
Test name
Test status
Simulation time 4119588267 ps
CPU time 9.09 seconds
Started Jul 05 06:02:03 PM PDT 24
Finished Jul 05 06:02:12 PM PDT 24
Peak memory 201720 kb
Host smart-188c08d6-54ad-4fbc-82ea-fc0020e38501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924314639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.924314639
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1488968367
Short name T6
Test name
Test status
Simulation time 5810131299 ps
CPU time 7.38 seconds
Started Jul 05 06:01:56 PM PDT 24
Finished Jul 05 06:02:04 PM PDT 24
Peak memory 201704 kb
Host smart-21c34a84-8789-4250-b10f-0bcb3d8ae678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488968367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1488968367
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1156913873
Short name T645
Test name
Test status
Simulation time 366590519 ps
CPU time 0.8 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:00:06 PM PDT 24
Peak memory 201628 kb
Host smart-ca009218-cb48-45f2-8429-a54d77cf34dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156913873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1156913873
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3970183041
Short name T633
Test name
Test status
Simulation time 199177810323 ps
CPU time 373.79 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:06:06 PM PDT 24
Peak memory 201900 kb
Host smart-5ab54044-6085-4a9d-928f-8f7e8a6f1fcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970183041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3970183041
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3402025330
Short name T9
Test name
Test status
Simulation time 169758699321 ps
CPU time 193.55 seconds
Started Jul 05 05:59:55 PM PDT 24
Finished Jul 05 06:03:09 PM PDT 24
Peak memory 201968 kb
Host smart-52476bf4-fd55-4767-aa3b-ac25932e6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402025330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3402025330
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2704409328
Short name T458
Test name
Test status
Simulation time 330189094770 ps
CPU time 726.48 seconds
Started Jul 05 05:59:58 PM PDT 24
Finished Jul 05 06:12:05 PM PDT 24
Peak memory 201848 kb
Host smart-998fc60e-2f4d-4faa-8aa0-954c138404ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704409328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2704409328
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2755680718
Short name T198
Test name
Test status
Simulation time 491629638391 ps
CPU time 1132.52 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:18:43 PM PDT 24
Peak memory 201996 kb
Host smart-704ac5a9-c6d2-4e66-b479-ff4d2beb3d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755680718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2755680718
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2649115609
Short name T394
Test name
Test status
Simulation time 493763475491 ps
CPU time 1100.35 seconds
Started Jul 05 06:00:02 PM PDT 24
Finished Jul 05 06:18:22 PM PDT 24
Peak memory 201868 kb
Host smart-d04d01cd-8ff5-48ce-8a0d-26f5c61a75bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649115609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2649115609
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2107379588
Short name T647
Test name
Test status
Simulation time 186780977129 ps
CPU time 203.34 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:03:29 PM PDT 24
Peak memory 201936 kb
Host smart-94c70688-fe3e-4064-bd44-05b033693f78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107379588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2107379588
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3305394457
Short name T745
Test name
Test status
Simulation time 205001192834 ps
CPU time 426.6 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:07:17 PM PDT 24
Peak memory 201848 kb
Host smart-c37837c3-a3c3-41af-b29c-4c6d7046c0a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305394457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3305394457
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1175980124
Short name T49
Test name
Test status
Simulation time 125125913704 ps
CPU time 535.12 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:08:45 PM PDT 24
Peak memory 202272 kb
Host smart-e936fc27-0745-4bf8-95d2-651602e8d944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175980124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1175980124
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1822012595
Short name T567
Test name
Test status
Simulation time 40095783851 ps
CPU time 7.56 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:00:13 PM PDT 24
Peak memory 201724 kb
Host smart-58de1184-bfe7-482b-9f32-1bce7cb6c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822012595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1822012595
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.266525085
Short name T501
Test name
Test status
Simulation time 3218657682 ps
CPU time 7.93 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:00:00 PM PDT 24
Peak memory 201720 kb
Host smart-3a2143c1-d18b-452d-986c-0938985b7e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266525085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.266525085
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3007775669
Short name T83
Test name
Test status
Simulation time 3856512678 ps
CPU time 5.08 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:58 PM PDT 24
Peak memory 217072 kb
Host smart-70c624ef-0d63-46f1-8bd0-9f2d5fb0b125
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007775669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3007775669
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.890319451
Short name T752
Test name
Test status
Simulation time 5882798619 ps
CPU time 14.84 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 06:00:04 PM PDT 24
Peak memory 201732 kb
Host smart-6b5e8612-5656-48d9-acd4-b893acf85327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890319451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.890319451
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3631240963
Short name T111
Test name
Test status
Simulation time 176603716613 ps
CPU time 356.79 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:05:49 PM PDT 24
Peak memory 201820 kb
Host smart-9df878b0-8458-4709-9d8f-2d00e8ad980e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631240963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3631240963
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3111385288
Short name T342
Test name
Test status
Simulation time 20904999895 ps
CPU time 93 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 06:01:28 PM PDT 24
Peak memory 210600 kb
Host smart-7dd3480b-6007-4d29-8db1-83c85af40648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111385288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3111385288
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.858334635
Short name T459
Test name
Test status
Simulation time 368387174 ps
CPU time 1.01 seconds
Started Jul 05 06:02:17 PM PDT 24
Finished Jul 05 06:02:18 PM PDT 24
Peak memory 201656 kb
Host smart-5e99db01-ee44-42f5-8f22-7e52aec34edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858334635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.858334635
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2447741533
Short name T279
Test name
Test status
Simulation time 349053153377 ps
CPU time 36.63 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:02:56 PM PDT 24
Peak memory 201908 kb
Host smart-1570f564-b827-47c0-bdec-c3b1ed0fa657
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447741533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2447741533
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1332425456
Short name T223
Test name
Test status
Simulation time 194616226415 ps
CPU time 104.5 seconds
Started Jul 05 06:02:17 PM PDT 24
Finished Jul 05 06:04:02 PM PDT 24
Peak memory 201992 kb
Host smart-f251483a-3a30-4b0c-a978-d30c00281a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332425456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1332425456
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.438936054
Short name T191
Test name
Test status
Simulation time 338638466645 ps
CPU time 411.82 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:09:11 PM PDT 24
Peak memory 201908 kb
Host smart-827c1fe3-ff69-480e-b5fd-c884f09f452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438936054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.438936054
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.561843138
Short name T577
Test name
Test status
Simulation time 319351329480 ps
CPU time 192.04 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:05:31 PM PDT 24
Peak memory 201948 kb
Host smart-e3940dac-fbf5-4569-b485-00132f8bff9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=561843138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.561843138
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3597594565
Short name T471
Test name
Test status
Simulation time 334050730415 ps
CPU time 201.15 seconds
Started Jul 05 06:02:12 PM PDT 24
Finished Jul 05 06:05:33 PM PDT 24
Peak memory 201876 kb
Host smart-8fb2c69b-3e03-4c20-b434-60454402d707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597594565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3597594565
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2503893164
Short name T393
Test name
Test status
Simulation time 328109446459 ps
CPU time 50.25 seconds
Started Jul 05 06:02:09 PM PDT 24
Finished Jul 05 06:03:00 PM PDT 24
Peak memory 201960 kb
Host smart-b5539b82-b3d2-4ffd-af6e-51feecc79b7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503893164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2503893164
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3027283613
Short name T283
Test name
Test status
Simulation time 544241366177 ps
CPU time 1308.22 seconds
Started Jul 05 06:02:20 PM PDT 24
Finished Jul 05 06:24:09 PM PDT 24
Peak memory 201884 kb
Host smart-83b863fa-4ca1-4eba-ab04-3b89863aeadf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027283613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3027283613
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.785198694
Short name T716
Test name
Test status
Simulation time 588633650983 ps
CPU time 343.4 seconds
Started Jul 05 06:02:17 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 201900 kb
Host smart-66e628ff-2f91-4f77-b3e2-c6731b587185
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785198694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.785198694
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1864745437
Short name T395
Test name
Test status
Simulation time 114351292069 ps
CPU time 591.98 seconds
Started Jul 05 06:02:17 PM PDT 24
Finished Jul 05 06:12:10 PM PDT 24
Peak memory 202280 kb
Host smart-b84fa4ea-c96e-4a7c-8d02-b19eb34496fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864745437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1864745437
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2353674623
Short name T372
Test name
Test status
Simulation time 20554510759 ps
CPU time 8.78 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:02:28 PM PDT 24
Peak memory 201724 kb
Host smart-73f47124-17fc-49df-b163-91bc64c60034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353674623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2353674623
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2184749939
Short name T378
Test name
Test status
Simulation time 3475832994 ps
CPU time 2.71 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:02:22 PM PDT 24
Peak memory 201708 kb
Host smart-f1765958-4b67-4f2d-b309-5ed2dd0b1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184749939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2184749939
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.139311227
Short name T448
Test name
Test status
Simulation time 6164888839 ps
CPU time 1.82 seconds
Started Jul 05 06:02:11 PM PDT 24
Finished Jul 05 06:02:13 PM PDT 24
Peak memory 201720 kb
Host smart-90d09a98-2354-434b-babb-b05967fbb3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139311227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.139311227
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2380857843
Short name T485
Test name
Test status
Simulation time 111798990381 ps
CPU time 532.9 seconds
Started Jul 05 06:02:18 PM PDT 24
Finished Jul 05 06:11:11 PM PDT 24
Peak memory 202276 kb
Host smart-a57791da-ba85-49a4-9865-48dfe4190d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380857843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2380857843
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2894085864
Short name T490
Test name
Test status
Simulation time 317424403 ps
CPU time 1.29 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:02:34 PM PDT 24
Peak memory 201656 kb
Host smart-ee5e003e-ef00-4c4e-9692-11a3ad736b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894085864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2894085864
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.794670889
Short name T667
Test name
Test status
Simulation time 187666038508 ps
CPU time 231.23 seconds
Started Jul 05 06:02:25 PM PDT 24
Finished Jul 05 06:06:16 PM PDT 24
Peak memory 201920 kb
Host smart-98e950b9-757e-4a6c-800e-1ab8aeb5686f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794670889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.794670889
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.4039916606
Short name T334
Test name
Test status
Simulation time 515289599557 ps
CPU time 1218.2 seconds
Started Jul 05 06:02:27 PM PDT 24
Finished Jul 05 06:22:45 PM PDT 24
Peak memory 201984 kb
Host smart-fd7e3358-82a0-4b03-b719-6ab867a990f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039916606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.4039916606
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.46224160
Short name T392
Test name
Test status
Simulation time 157760534895 ps
CPU time 327.54 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:07:47 PM PDT 24
Peak memory 201856 kb
Host smart-7259f9c7-234e-44f9-990e-692c4363c67e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=46224160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt
_fixed.46224160
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1775205578
Short name T132
Test name
Test status
Simulation time 483173402174 ps
CPU time 282.31 seconds
Started Jul 05 06:02:18 PM PDT 24
Finished Jul 05 06:07:00 PM PDT 24
Peak memory 201980 kb
Host smart-93fda67e-5284-4ced-9ae4-d604c3d92640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775205578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1775205578
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1293645455
Short name T749
Test name
Test status
Simulation time 160793649309 ps
CPU time 183.56 seconds
Started Jul 05 06:02:19 PM PDT 24
Finished Jul 05 06:05:23 PM PDT 24
Peak memory 201888 kb
Host smart-8bda1d2b-3b50-432c-b70d-7e54e02cdabc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293645455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1293645455
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3348718557
Short name T306
Test name
Test status
Simulation time 350132326192 ps
CPU time 369.62 seconds
Started Jul 05 06:02:26 PM PDT 24
Finished Jul 05 06:08:36 PM PDT 24
Peak memory 201932 kb
Host smart-ebe6b16e-cc74-4504-910e-91335043fb14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348718557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3348718557
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2318339640
Short name T384
Test name
Test status
Simulation time 606188192013 ps
CPU time 342.77 seconds
Started Jul 05 06:02:27 PM PDT 24
Finished Jul 05 06:08:10 PM PDT 24
Peak memory 201976 kb
Host smart-dc577543-d179-427a-9a65-ea8d04b87311
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318339640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2318339640
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1697043748
Short name T781
Test name
Test status
Simulation time 80394497483 ps
CPU time 279.26 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:07:13 PM PDT 24
Peak memory 202156 kb
Host smart-8aeb36d2-a059-4d1b-a257-20cfa1a4eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697043748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1697043748
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.149042842
Short name T628
Test name
Test status
Simulation time 30340623626 ps
CPU time 16.81 seconds
Started Jul 05 06:02:27 PM PDT 24
Finished Jul 05 06:02:44 PM PDT 24
Peak memory 201684 kb
Host smart-092e94d0-cc3b-43ae-b6b6-beb8ba270477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149042842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.149042842
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1782567205
Short name T693
Test name
Test status
Simulation time 3118573427 ps
CPU time 4.53 seconds
Started Jul 05 06:02:26 PM PDT 24
Finished Jul 05 06:02:31 PM PDT 24
Peak memory 201720 kb
Host smart-06e00cdc-7a20-4ad7-b326-383b2c4bc73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782567205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1782567205
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.640023170
Short name T469
Test name
Test status
Simulation time 6149811265 ps
CPU time 3.39 seconds
Started Jul 05 06:02:15 PM PDT 24
Finished Jul 05 06:02:19 PM PDT 24
Peak memory 201652 kb
Host smart-69fec9ac-ffac-417a-97a0-70d6b309906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640023170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.640023170
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1907640316
Short name T549
Test name
Test status
Simulation time 84788404144 ps
CPU time 272.09 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:07:06 PM PDT 24
Peak memory 218548 kb
Host smart-d71cd3bc-e0d8-4a62-997a-80b0834bd1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907640316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1907640316
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2374464597
Short name T199
Test name
Test status
Simulation time 244751001668 ps
CPU time 270.26 seconds
Started Jul 05 06:02:34 PM PDT 24
Finished Jul 05 06:07:05 PM PDT 24
Peak memory 210792 kb
Host smart-1b610300-2c40-482a-8667-7c47ab86ab72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374464597 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2374464597
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1658313395
Short name T442
Test name
Test status
Simulation time 371265049 ps
CPU time 1.4 seconds
Started Jul 05 06:02:46 PM PDT 24
Finished Jul 05 06:02:47 PM PDT 24
Peak memory 201636 kb
Host smart-37077c5e-69ad-4644-8e5b-30b20502b156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658313395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1658313395
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1710481983
Short name T133
Test name
Test status
Simulation time 328818459437 ps
CPU time 168.53 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 201920 kb
Host smart-241d9742-90ba-41ef-9dca-9454793c1c57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710481983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1710481983
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.659596186
Short name T171
Test name
Test status
Simulation time 333364047401 ps
CPU time 182.1 seconds
Started Jul 05 06:02:34 PM PDT 24
Finished Jul 05 06:05:36 PM PDT 24
Peak memory 201908 kb
Host smart-f665592c-a9a5-4bc8-b131-5607cc563b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659596186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.659596186
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3226646100
Short name T723
Test name
Test status
Simulation time 485430537784 ps
CPU time 599.59 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:12:33 PM PDT 24
Peak memory 201920 kb
Host smart-33b5f422-cd56-4444-ab8c-20c02018a702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226646100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3226646100
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2623626524
Short name T510
Test name
Test status
Simulation time 332902925080 ps
CPU time 754.94 seconds
Started Jul 05 06:02:34 PM PDT 24
Finished Jul 05 06:15:09 PM PDT 24
Peak memory 201832 kb
Host smart-494c3d0a-e58a-4292-8b3d-a9d3e9ad2ff2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623626524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2623626524
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1460371280
Short name T423
Test name
Test status
Simulation time 166180077789 ps
CPU time 98.33 seconds
Started Jul 05 06:02:35 PM PDT 24
Finished Jul 05 06:04:13 PM PDT 24
Peak memory 201912 kb
Host smart-8b578344-5b43-4268-b067-8775f65aff1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460371280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1460371280
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1758875775
Short name T260
Test name
Test status
Simulation time 188927656573 ps
CPU time 443.96 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:09:57 PM PDT 24
Peak memory 201928 kb
Host smart-f7d0702b-b785-4303-aa2a-68cc02813754
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758875775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1758875775
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3339926320
Short name T489
Test name
Test status
Simulation time 599263358671 ps
CPU time 1348.87 seconds
Started Jul 05 06:02:33 PM PDT 24
Finished Jul 05 06:25:03 PM PDT 24
Peak memory 201896 kb
Host smart-e6966f90-6ea0-4c13-b19d-58055807b65f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339926320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3339926320
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3874496130
Short name T204
Test name
Test status
Simulation time 117796989923 ps
CPU time 586.69 seconds
Started Jul 05 06:02:40 PM PDT 24
Finished Jul 05 06:12:27 PM PDT 24
Peak memory 202212 kb
Host smart-b8a7e139-9a63-433e-aea0-e94905a30de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874496130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3874496130
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2681207436
Short name T525
Test name
Test status
Simulation time 40257144375 ps
CPU time 8.62 seconds
Started Jul 05 06:02:41 PM PDT 24
Finished Jul 05 06:02:50 PM PDT 24
Peak memory 201708 kb
Host smart-a3e9ddc8-7e35-4bae-9c7d-c7793eae70ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681207436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2681207436
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1451155989
Short name T782
Test name
Test status
Simulation time 3962246045 ps
CPU time 9.5 seconds
Started Jul 05 06:02:35 PM PDT 24
Finished Jul 05 06:02:44 PM PDT 24
Peak memory 201724 kb
Host smart-aa8ef2e0-cff5-4f1f-b738-9c06bc0584cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451155989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1451155989
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1743484699
Short name T713
Test name
Test status
Simulation time 5689127887 ps
CPU time 9.11 seconds
Started Jul 05 06:02:34 PM PDT 24
Finished Jul 05 06:02:43 PM PDT 24
Peak memory 201740 kb
Host smart-f60cd11c-54c3-4543-a95c-d01bfb8cfa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743484699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1743484699
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3930495237
Short name T82
Test name
Test status
Simulation time 513632101 ps
CPU time 1.68 seconds
Started Jul 05 06:02:56 PM PDT 24
Finished Jul 05 06:02:58 PM PDT 24
Peak memory 201668 kb
Host smart-a0beccde-a2d2-4e8d-8880-9d197bff1e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930495237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3930495237
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1953371851
Short name T621
Test name
Test status
Simulation time 175133789053 ps
CPU time 210.99 seconds
Started Jul 05 06:02:47 PM PDT 24
Finished Jul 05 06:06:18 PM PDT 24
Peak memory 201984 kb
Host smart-9e030c0c-1e79-45f9-8f44-62f01db78898
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953371851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1953371851
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2789831324
Short name T192
Test name
Test status
Simulation time 365087611377 ps
CPU time 202.48 seconds
Started Jul 05 06:02:47 PM PDT 24
Finished Jul 05 06:06:09 PM PDT 24
Peak memory 201888 kb
Host smart-efc7bda1-662c-4163-abab-a344f01bf11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789831324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2789831324
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1844592486
Short name T218
Test name
Test status
Simulation time 161986339515 ps
CPU time 201.12 seconds
Started Jul 05 06:02:40 PM PDT 24
Finished Jul 05 06:06:02 PM PDT 24
Peak memory 201920 kb
Host smart-13a78836-dced-4a6f-b8b4-4b8ca8412c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844592486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1844592486
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2705351459
Short name T776
Test name
Test status
Simulation time 328444040036 ps
CPU time 704.04 seconds
Started Jul 05 06:02:40 PM PDT 24
Finished Jul 05 06:14:25 PM PDT 24
Peak memory 201876 kb
Host smart-d39e789e-fcfb-46d4-9e6a-ca6e29e0fc04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705351459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2705351459
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4237397303
Short name T220
Test name
Test status
Simulation time 489140326545 ps
CPU time 1111.74 seconds
Started Jul 05 06:02:40 PM PDT 24
Finished Jul 05 06:21:12 PM PDT 24
Peak memory 201860 kb
Host smart-9171cfa4-c473-4d7c-add9-4a9cda7e9181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237397303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4237397303
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2385396568
Short name T444
Test name
Test status
Simulation time 163851313730 ps
CPU time 92.46 seconds
Started Jul 05 06:02:46 PM PDT 24
Finished Jul 05 06:04:19 PM PDT 24
Peak memory 201880 kb
Host smart-d52af04c-b117-4554-bf12-d3a969e964f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385396568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2385396568
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1747263590
Short name T754
Test name
Test status
Simulation time 367887894444 ps
CPU time 806.55 seconds
Started Jul 05 06:02:46 PM PDT 24
Finished Jul 05 06:16:13 PM PDT 24
Peak memory 201956 kb
Host smart-2f337942-e500-462d-92a5-c0a64ec5d2ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747263590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1747263590
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1337876162
Short name T155
Test name
Test status
Simulation time 210670155494 ps
CPU time 242.87 seconds
Started Jul 05 06:02:48 PM PDT 24
Finished Jul 05 06:06:51 PM PDT 24
Peak memory 201912 kb
Host smart-457dcd7a-943a-4528-af24-863471eddff9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337876162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1337876162
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3525778271
Short name T214
Test name
Test status
Simulation time 128009280012 ps
CPU time 627.49 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:19:14 PM PDT 24
Peak memory 202192 kb
Host smart-a7bc4794-4099-4255-ba7b-1f328d2de78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525778271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3525778271
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1672000218
Short name T773
Test name
Test status
Simulation time 37428957841 ps
CPU time 21.84 seconds
Started Jul 05 06:02:51 PM PDT 24
Finished Jul 05 06:03:13 PM PDT 24
Peak memory 201688 kb
Host smart-794b14d0-9f57-4b8c-b303-af1a0c26cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672000218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1672000218
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1143220240
Short name T785
Test name
Test status
Simulation time 4403660543 ps
CPU time 1.63 seconds
Started Jul 05 06:02:47 PM PDT 24
Finished Jul 05 06:02:49 PM PDT 24
Peak memory 201724 kb
Host smart-e837fa17-cfe7-493b-a134-59a8f6c09be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143220240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1143220240
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2905702626
Short name T129
Test name
Test status
Simulation time 5486119087 ps
CPU time 5.87 seconds
Started Jul 05 06:02:45 PM PDT 24
Finished Jul 05 06:02:51 PM PDT 24
Peak memory 201700 kb
Host smart-77bc8936-bea1-4748-8c4c-efcbbc548ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905702626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2905702626
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1760319384
Short name T18
Test name
Test status
Simulation time 20887054372 ps
CPU time 49.76 seconds
Started Jul 05 06:02:46 PM PDT 24
Finished Jul 05 06:03:36 PM PDT 24
Peak memory 210628 kb
Host smart-dbbc7061-c0b9-414e-8fe0-37234702a0aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760319384 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1760319384
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2344655542
Short name T368
Test name
Test status
Simulation time 405166401 ps
CPU time 0.95 seconds
Started Jul 05 06:03:01 PM PDT 24
Finished Jul 05 06:03:02 PM PDT 24
Peak memory 201656 kb
Host smart-898511ae-5f92-4fe9-8dc1-cca48d4e26b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344655542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2344655542
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1708117373
Short name T185
Test name
Test status
Simulation time 325776112842 ps
CPU time 72.19 seconds
Started Jul 05 06:03:03 PM PDT 24
Finished Jul 05 06:04:15 PM PDT 24
Peak memory 201920 kb
Host smart-3402baec-94ff-4212-a47f-ab2c778ae970
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708117373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1708117373
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1840759394
Short name T523
Test name
Test status
Simulation time 169138991664 ps
CPU time 247.26 seconds
Started Jul 05 06:02:59 PM PDT 24
Finished Jul 05 06:07:07 PM PDT 24
Peak memory 202008 kb
Host smart-5577ce1f-1f97-413f-ae94-0bc777e7d19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840759394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1840759394
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2920225637
Short name T760
Test name
Test status
Simulation time 168201670027 ps
CPU time 394.48 seconds
Started Jul 05 06:02:54 PM PDT 24
Finished Jul 05 06:09:29 PM PDT 24
Peak memory 201904 kb
Host smart-fc58c5de-09e5-4310-9a63-fd6ee7deae6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920225637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2920225637
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3637677346
Short name T217
Test name
Test status
Simulation time 332187244478 ps
CPU time 157.64 seconds
Started Jul 05 06:02:54 PM PDT 24
Finished Jul 05 06:05:32 PM PDT 24
Peak memory 201916 kb
Host smart-8354ce76-4dbb-4f42-ab01-98afcab956c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637677346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3637677346
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2687968390
Short name T737
Test name
Test status
Simulation time 165132977310 ps
CPU time 250.31 seconds
Started Jul 05 06:02:54 PM PDT 24
Finished Jul 05 06:07:05 PM PDT 24
Peak memory 201864 kb
Host smart-02099b01-3aa9-407f-a36a-b65a22d14b2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687968390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2687968390
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2441824196
Short name T146
Test name
Test status
Simulation time 174149612041 ps
CPU time 91.84 seconds
Started Jul 05 06:02:51 PM PDT 24
Finished Jul 05 06:04:24 PM PDT 24
Peak memory 201844 kb
Host smart-9587be97-5749-41ee-963a-2a94566391f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441824196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2441824196
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4035613524
Short name T486
Test name
Test status
Simulation time 590491462446 ps
CPU time 1063.16 seconds
Started Jul 05 06:02:56 PM PDT 24
Finished Jul 05 06:20:39 PM PDT 24
Peak memory 201912 kb
Host smart-6d2ba534-b20c-4fac-bfc7-f24b5fb24daf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035613524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4035613524
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3238801925
Short name T738
Test name
Test status
Simulation time 74309048525 ps
CPU time 280.5 seconds
Started Jul 05 06:03:00 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 202216 kb
Host smart-b4b2c7c0-7b6b-4f00-be95-16e3a3e42880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238801925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3238801925
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3545680668
Short name T350
Test name
Test status
Simulation time 45263454403 ps
CPU time 49.73 seconds
Started Jul 05 06:03:03 PM PDT 24
Finished Jul 05 06:03:53 PM PDT 24
Peak memory 201728 kb
Host smart-38ba59f9-b74a-440f-85c7-22d7e4c482df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545680668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3545680668
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2007993479
Short name T711
Test name
Test status
Simulation time 3009627469 ps
CPU time 2.12 seconds
Started Jul 05 06:03:02 PM PDT 24
Finished Jul 05 06:03:04 PM PDT 24
Peak memory 201712 kb
Host smart-ed4584f2-bbb5-453c-abe0-f1e08e7773db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007993479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2007993479
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.614873273
Short name T450
Test name
Test status
Simulation time 5882440513 ps
CPU time 7.85 seconds
Started Jul 05 06:02:52 PM PDT 24
Finished Jul 05 06:03:01 PM PDT 24
Peak memory 201720 kb
Host smart-6f4b685f-f8b8-4ebd-84bf-9e101d779870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614873273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.614873273
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2843494222
Short name T290
Test name
Test status
Simulation time 647314971025 ps
CPU time 1402.1 seconds
Started Jul 05 06:03:02 PM PDT 24
Finished Jul 05 06:26:25 PM PDT 24
Peak memory 201904 kb
Host smart-93e3903b-f504-4506-ab80-5166919a491d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843494222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2843494222
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.875053635
Short name T590
Test name
Test status
Simulation time 329814980 ps
CPU time 0.81 seconds
Started Jul 05 06:03:18 PM PDT 24
Finished Jul 05 06:03:19 PM PDT 24
Peak memory 201668 kb
Host smart-086ec97e-1696-46d0-bf4a-77de897e5312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875053635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.875053635
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2494857549
Short name T233
Test name
Test status
Simulation time 336253793511 ps
CPU time 405.17 seconds
Started Jul 05 06:03:08 PM PDT 24
Finished Jul 05 06:09:53 PM PDT 24
Peak memory 201988 kb
Host smart-6b148dd3-a134-4ff7-9ccb-e2f8ac8614ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494857549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2494857549
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2460547490
Short name T324
Test name
Test status
Simulation time 513056986885 ps
CPU time 1133.38 seconds
Started Jul 05 06:03:08 PM PDT 24
Finished Jul 05 06:22:01 PM PDT 24
Peak memory 201880 kb
Host smart-1a36f97e-abd4-4af6-8511-3a7ddf38f5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460547490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2460547490
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2840056748
Short name T328
Test name
Test status
Simulation time 325031318599 ps
CPU time 83.89 seconds
Started Jul 05 06:03:07 PM PDT 24
Finished Jul 05 06:04:32 PM PDT 24
Peak memory 201964 kb
Host smart-a7d2e4e9-2464-420f-8512-c1a99747f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840056748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2840056748
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4150079303
Short name T666
Test name
Test status
Simulation time 481355277064 ps
CPU time 975.62 seconds
Started Jul 05 06:03:08 PM PDT 24
Finished Jul 05 06:19:24 PM PDT 24
Peak memory 201864 kb
Host smart-491b1c8c-57d0-4aba-8c44-7f78dd3fd4c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150079303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4150079303
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3928398666
Short name T181
Test name
Test status
Simulation time 337410614123 ps
CPU time 161.15 seconds
Started Jul 05 06:03:00 PM PDT 24
Finished Jul 05 06:05:42 PM PDT 24
Peak memory 201920 kb
Host smart-72e1c21b-2092-49b6-a6d8-ac344692ea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928398666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3928398666
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.928415448
Short name T698
Test name
Test status
Simulation time 322706732019 ps
CPU time 371.04 seconds
Started Jul 05 06:03:07 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 201904 kb
Host smart-fbf6ef01-2def-4114-b65e-9aa571537ec7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=928415448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.928415448
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2067261012
Short name T775
Test name
Test status
Simulation time 371657239366 ps
CPU time 211.39 seconds
Started Jul 05 06:03:05 PM PDT 24
Finished Jul 05 06:06:37 PM PDT 24
Peak memory 201844 kb
Host smart-9d09294d-af0b-418c-8081-fc96f8d1b7de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067261012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2067261012
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4138028879
Short name T456
Test name
Test status
Simulation time 609074002900 ps
CPU time 1378.69 seconds
Started Jul 05 06:03:09 PM PDT 24
Finished Jul 05 06:26:08 PM PDT 24
Peak memory 201792 kb
Host smart-2257fec2-f344-4c2f-b95f-201e3a110ffa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138028879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4138028879
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1291150711
Short name T755
Test name
Test status
Simulation time 121264556554 ps
CPU time 395.88 seconds
Started Jul 05 06:03:16 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 202204 kb
Host smart-b5df976f-3684-40ab-9032-08461935505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291150711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1291150711
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1342285434
Short name T715
Test name
Test status
Simulation time 25767946513 ps
CPU time 28.96 seconds
Started Jul 05 06:03:18 PM PDT 24
Finished Jul 05 06:03:47 PM PDT 24
Peak memory 201724 kb
Host smart-68337c42-a29c-4ce8-9b6d-79883da45b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342285434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1342285434
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.161576819
Short name T671
Test name
Test status
Simulation time 4587351890 ps
CPU time 11.67 seconds
Started Jul 05 06:03:07 PM PDT 24
Finished Jul 05 06:03:19 PM PDT 24
Peak memory 201716 kb
Host smart-9a799668-3b8e-4a9c-b656-b8c6e484aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161576819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.161576819
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2276595335
Short name T686
Test name
Test status
Simulation time 5636787104 ps
CPU time 7.32 seconds
Started Jul 05 06:03:04 PM PDT 24
Finished Jul 05 06:03:11 PM PDT 24
Peak memory 201744 kb
Host smart-178dc371-642c-4409-aad9-e529b8fb82c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276595335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2276595335
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.766211434
Short name T744
Test name
Test status
Simulation time 201610495937 ps
CPU time 448.83 seconds
Started Jul 05 06:03:17 PM PDT 24
Finished Jul 05 06:10:46 PM PDT 24
Peak memory 201972 kb
Host smart-df0b35df-fa33-471a-9e2b-93f720ed8a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766211434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
766211434
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.254338871
Short name T318
Test name
Test status
Simulation time 47713867996 ps
CPU time 100.94 seconds
Started Jul 05 06:03:16 PM PDT 24
Finished Jul 05 06:04:57 PM PDT 24
Peak memory 202036 kb
Host smart-e0a17770-97e1-4872-b15a-1e00d38ac419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254338871 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.254338871
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2629754177
Short name T714
Test name
Test status
Simulation time 529663641 ps
CPU time 1.49 seconds
Started Jul 05 06:03:33 PM PDT 24
Finished Jul 05 06:03:35 PM PDT 24
Peak memory 201636 kb
Host smart-039d1f3a-c27e-434d-b961-581b7af6f5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629754177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2629754177
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2296604031
Short name T336
Test name
Test status
Simulation time 165051332774 ps
CPU time 96.19 seconds
Started Jul 05 06:03:24 PM PDT 24
Finished Jul 05 06:05:00 PM PDT 24
Peak memory 201872 kb
Host smart-de3b3181-9bfc-4a54-821d-df9cfffa8453
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296604031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2296604031
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4189906561
Short name T297
Test name
Test status
Simulation time 164950266442 ps
CPU time 188.24 seconds
Started Jul 05 06:03:23 PM PDT 24
Finished Jul 05 06:06:32 PM PDT 24
Peak memory 201976 kb
Host smart-98e1ff05-4837-4628-acbe-3d3c9cee7563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189906561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4189906561
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1283721682
Short name T257
Test name
Test status
Simulation time 491264145202 ps
CPU time 569.27 seconds
Started Jul 05 06:03:24 PM PDT 24
Finished Jul 05 06:12:54 PM PDT 24
Peak memory 201848 kb
Host smart-a8189ae7-ea02-4799-835a-0d1d1d179ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283721682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1283721682
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.743368924
Short name T349
Test name
Test status
Simulation time 324814834023 ps
CPU time 373.31 seconds
Started Jul 05 06:03:23 PM PDT 24
Finished Jul 05 06:09:36 PM PDT 24
Peak memory 201904 kb
Host smart-15ee87f8-b07b-4c61-a258-638abe23ef70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=743368924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.743368924
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1820130677
Short name T612
Test name
Test status
Simulation time 327739056868 ps
CPU time 392.04 seconds
Started Jul 05 06:03:23 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 201944 kb
Host smart-085821c6-8bdd-4fca-b45b-107401958981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820130677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1820130677
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1757270790
Short name T356
Test name
Test status
Simulation time 160002991692 ps
CPU time 174.82 seconds
Started Jul 05 06:03:21 PM PDT 24
Finished Jul 05 06:06:17 PM PDT 24
Peak memory 201824 kb
Host smart-3f18d583-b4e8-4983-b7c5-cee90aaa7e1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757270790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1757270790
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1977454520
Short name T186
Test name
Test status
Simulation time 365186954791 ps
CPU time 228.91 seconds
Started Jul 05 06:03:19 PM PDT 24
Finished Jul 05 06:07:09 PM PDT 24
Peak memory 201956 kb
Host smart-f1ad21b7-a263-4650-ac25-9f914bfb06cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977454520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1977454520
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1935899126
Short name T570
Test name
Test status
Simulation time 597290887666 ps
CPU time 383.87 seconds
Started Jul 05 06:03:22 PM PDT 24
Finished Jul 05 06:09:47 PM PDT 24
Peak memory 201856 kb
Host smart-d972e440-144e-48c0-bf2a-9e16bbc46a64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935899126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1935899126
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3396038540
Short name T343
Test name
Test status
Simulation time 86490758808 ps
CPU time 447.67 seconds
Started Jul 05 06:03:31 PM PDT 24
Finished Jul 05 06:10:59 PM PDT 24
Peak memory 202192 kb
Host smart-be8cd9a6-1fbf-4710-bfa5-7711613acf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396038540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3396038540
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3133747614
Short name T792
Test name
Test status
Simulation time 32294394385 ps
CPU time 40.63 seconds
Started Jul 05 06:03:21 PM PDT 24
Finished Jul 05 06:04:02 PM PDT 24
Peak memory 201716 kb
Host smart-ed998f3f-356b-4a99-9a4d-abac3d5a46b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133747614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3133747614
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1004719159
Short name T495
Test name
Test status
Simulation time 5668150315 ps
CPU time 3.97 seconds
Started Jul 05 06:03:22 PM PDT 24
Finished Jul 05 06:03:27 PM PDT 24
Peak memory 201628 kb
Host smart-a0fd5842-1845-4ef6-93fc-02d53216d28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004719159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1004719159
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3359055729
Short name T581
Test name
Test status
Simulation time 6037521379 ps
CPU time 3.96 seconds
Started Jul 05 06:03:23 PM PDT 24
Finished Jul 05 06:03:27 PM PDT 24
Peak memory 201744 kb
Host smart-195112e9-f8cf-4455-b0b5-db49f6ed1611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359055729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3359055729
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1925870211
Short name T265
Test name
Test status
Simulation time 505329470632 ps
CPU time 291.71 seconds
Started Jul 05 06:03:31 PM PDT 24
Finished Jul 05 06:08:23 PM PDT 24
Peak memory 201908 kb
Host smart-957c6da0-8457-4472-979c-922bf587bcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925870211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1925870211
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.776623860
Short name T288
Test name
Test status
Simulation time 64025740848 ps
CPU time 149.87 seconds
Started Jul 05 06:03:33 PM PDT 24
Finished Jul 05 06:06:03 PM PDT 24
Peak memory 210580 kb
Host smart-a7435915-3f87-476f-8b19-f65628ace0b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776623860 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.776623860
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3390648154
Short name T636
Test name
Test status
Simulation time 294804530 ps
CPU time 1.25 seconds
Started Jul 05 06:03:43 PM PDT 24
Finished Jul 05 06:03:44 PM PDT 24
Peak memory 201644 kb
Host smart-334430af-29d1-454f-a99d-0fedf792fa7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390648154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3390648154
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3344485148
Short name T319
Test name
Test status
Simulation time 347443496532 ps
CPU time 206.85 seconds
Started Jul 05 06:03:39 PM PDT 24
Finished Jul 05 06:07:07 PM PDT 24
Peak memory 201900 kb
Host smart-2de8e86a-e83b-4746-a085-e2e39c7e0c6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344485148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3344485148
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.767191747
Short name T793
Test name
Test status
Simulation time 332138937352 ps
CPU time 130.44 seconds
Started Jul 05 06:03:31 PM PDT 24
Finished Jul 05 06:05:42 PM PDT 24
Peak memory 201960 kb
Host smart-282a47c4-3624-4cfa-8ce5-025ea18781ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767191747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.767191747
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3573690991
Short name T360
Test name
Test status
Simulation time 497311193540 ps
CPU time 267.58 seconds
Started Jul 05 06:03:32 PM PDT 24
Finished Jul 05 06:08:00 PM PDT 24
Peak memory 201872 kb
Host smart-1884f8c7-43d3-4265-bad2-3f70bc5d4e5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573690991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3573690991
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2544449426
Short name T321
Test name
Test status
Simulation time 161060025117 ps
CPU time 304.72 seconds
Started Jul 05 06:03:32 PM PDT 24
Finished Jul 05 06:08:37 PM PDT 24
Peak memory 201876 kb
Host smart-5622fc9a-ce35-451c-91bd-24b18ebf4966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544449426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2544449426
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2280155888
Short name T369
Test name
Test status
Simulation time 327503027656 ps
CPU time 795.95 seconds
Started Jul 05 06:03:33 PM PDT 24
Finished Jul 05 06:16:49 PM PDT 24
Peak memory 201832 kb
Host smart-7b064dff-3510-4b7d-8fb6-a53de92d541a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280155888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2280155888
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2407583610
Short name T520
Test name
Test status
Simulation time 181234251280 ps
CPU time 106.39 seconds
Started Jul 05 06:03:33 PM PDT 24
Finished Jul 05 06:05:20 PM PDT 24
Peak memory 201904 kb
Host smart-80f706f6-e95c-4708-a395-2dad08c6dc51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407583610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2407583610
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.432574646
Short name T680
Test name
Test status
Simulation time 407154587564 ps
CPU time 440.84 seconds
Started Jul 05 06:03:39 PM PDT 24
Finished Jul 05 06:11:00 PM PDT 24
Peak memory 201908 kb
Host smart-14b51b3b-534f-40ca-8c21-dc6b9a7c6f9a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432574646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.432574646
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3137920058
Short name T772
Test name
Test status
Simulation time 100942747042 ps
CPU time 484.04 seconds
Started Jul 05 06:03:40 PM PDT 24
Finished Jul 05 06:11:45 PM PDT 24
Peak memory 202228 kb
Host smart-8706c6c4-4b63-481e-bafa-f5b057f2f894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137920058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3137920058
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.93472137
Short name T405
Test name
Test status
Simulation time 42562134133 ps
CPU time 26.06 seconds
Started Jul 05 06:03:44 PM PDT 24
Finished Jul 05 06:04:10 PM PDT 24
Peak memory 201696 kb
Host smart-d1015929-bf3c-4c0c-9044-515e91cdd1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93472137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.93472137
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.840060232
Short name T587
Test name
Test status
Simulation time 3037865687 ps
CPU time 4.12 seconds
Started Jul 05 06:03:40 PM PDT 24
Finished Jul 05 06:03:45 PM PDT 24
Peak memory 201724 kb
Host smart-d0e424f7-08eb-486b-ac5c-653ce7370887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840060232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.840060232
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.805059090
Short name T562
Test name
Test status
Simulation time 5950426552 ps
CPU time 1.49 seconds
Started Jul 05 06:03:31 PM PDT 24
Finished Jul 05 06:03:33 PM PDT 24
Peak memory 201736 kb
Host smart-0d2acbd1-d32b-4c92-bea1-d2c9fd88aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805059090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.805059090
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.487330853
Short name T34
Test name
Test status
Simulation time 360872489171 ps
CPU time 216.32 seconds
Started Jul 05 06:03:43 PM PDT 24
Finished Jul 05 06:07:20 PM PDT 24
Peak memory 201956 kb
Host smart-cd0336ae-41b9-4697-baf1-b3ca5a288122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487330853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
487330853
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4275056126
Short name T23
Test name
Test status
Simulation time 38326382656 ps
CPU time 46.28 seconds
Started Jul 05 06:03:39 PM PDT 24
Finished Jul 05 06:04:26 PM PDT 24
Peak memory 202112 kb
Host smart-fe1f3e4e-60fd-447b-9324-986930030bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275056126 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4275056126
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1367711559
Short name T780
Test name
Test status
Simulation time 350149110 ps
CPU time 0.82 seconds
Started Jul 05 06:03:53 PM PDT 24
Finished Jul 05 06:03:54 PM PDT 24
Peak memory 201628 kb
Host smart-0f62fa16-2358-4017-ac5e-d03f902b5220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367711559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1367711559
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1770522163
Short name T144
Test name
Test status
Simulation time 541769634953 ps
CPU time 1282.62 seconds
Started Jul 05 06:03:47 PM PDT 24
Finished Jul 05 06:25:10 PM PDT 24
Peak memory 201924 kb
Host smart-0578bf99-c5f1-4ca3-ad8c-75eaf871a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770522163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1770522163
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4223421214
Short name T271
Test name
Test status
Simulation time 167835510377 ps
CPU time 103.43 seconds
Started Jul 05 06:03:40 PM PDT 24
Finished Jul 05 06:05:24 PM PDT 24
Peak memory 201864 kb
Host smart-752d34c1-dbcf-44aa-b358-7f3ddee70705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223421214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4223421214
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2057689864
Short name T747
Test name
Test status
Simulation time 484372739618 ps
CPU time 141.03 seconds
Started Jul 05 06:03:39 PM PDT 24
Finished Jul 05 06:06:00 PM PDT 24
Peak memory 201916 kb
Host smart-de50e1d0-2b52-4013-a1ef-a7e6ce81abf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057689864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2057689864
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3775952541
Short name T194
Test name
Test status
Simulation time 490137021169 ps
CPU time 1184.62 seconds
Started Jul 05 06:03:41 PM PDT 24
Finished Jul 05 06:23:26 PM PDT 24
Peak memory 201916 kb
Host smart-e6ffaab9-ff67-4018-9422-6a62538e20fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775952541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3775952541
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3649377052
Short name T568
Test name
Test status
Simulation time 167938534121 ps
CPU time 89.79 seconds
Started Jul 05 06:03:37 PM PDT 24
Finished Jul 05 06:05:07 PM PDT 24
Peak memory 201924 kb
Host smart-5c62491b-aae5-4a2d-8667-50b8296528d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649377052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3649377052
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1089801173
Short name T166
Test name
Test status
Simulation time 344823104923 ps
CPU time 190.92 seconds
Started Jul 05 06:03:49 PM PDT 24
Finished Jul 05 06:07:00 PM PDT 24
Peak memory 201996 kb
Host smart-67e16c92-cff2-4e46-b939-5f6860b71ebd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089801173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1089801173
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2319112675
Short name T491
Test name
Test status
Simulation time 600846927168 ps
CPU time 259.21 seconds
Started Jul 05 06:03:46 PM PDT 24
Finished Jul 05 06:08:06 PM PDT 24
Peak memory 201860 kb
Host smart-4ca7013e-2c87-4471-817e-9272e4970cc7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319112675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2319112675
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4021890609
Short name T627
Test name
Test status
Simulation time 115393143629 ps
CPU time 640.23 seconds
Started Jul 05 06:03:46 PM PDT 24
Finished Jul 05 06:14:26 PM PDT 24
Peak memory 202216 kb
Host smart-dae0dc88-6f6f-4d41-91a3-41f7c36ff252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021890609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4021890609
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.312353256
Short name T651
Test name
Test status
Simulation time 28278320393 ps
CPU time 15.58 seconds
Started Jul 05 06:03:46 PM PDT 24
Finished Jul 05 06:04:02 PM PDT 24
Peak memory 201724 kb
Host smart-c8a5e0c5-6799-4f49-89d0-6aa91e2d92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312353256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.312353256
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3513557085
Short name T419
Test name
Test status
Simulation time 5220530015 ps
CPU time 3.31 seconds
Started Jul 05 06:03:46 PM PDT 24
Finished Jul 05 06:03:50 PM PDT 24
Peak memory 201724 kb
Host smart-8717cd3b-e04c-4167-8260-41a94879689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513557085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3513557085
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2610394935
Short name T154
Test name
Test status
Simulation time 5593587576 ps
CPU time 13.44 seconds
Started Jul 05 06:03:39 PM PDT 24
Finished Jul 05 06:03:53 PM PDT 24
Peak memory 201740 kb
Host smart-dd2732f8-3e45-49e8-ad55-b05058e1ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610394935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2610394935
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.483132723
Short name T559
Test name
Test status
Simulation time 169435390171 ps
CPU time 41.22 seconds
Started Jul 05 06:03:48 PM PDT 24
Finished Jul 05 06:04:29 PM PDT 24
Peak memory 201908 kb
Host smart-6e39315e-c314-47c7-ba86-acb80683e6b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483132723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
483132723
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.62419750
Short name T237
Test name
Test status
Simulation time 49615884256 ps
CPU time 74.85 seconds
Started Jul 05 06:03:44 PM PDT 24
Finished Jul 05 06:04:59 PM PDT 24
Peak memory 202032 kb
Host smart-a31534ba-156f-4e15-a665-437073308035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62419750 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.62419750
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.614718671
Short name T603
Test name
Test status
Simulation time 404144340 ps
CPU time 0.72 seconds
Started Jul 05 06:04:01 PM PDT 24
Finished Jul 05 06:04:02 PM PDT 24
Peak memory 201676 kb
Host smart-3c6a874e-a738-4b2d-ab2b-1908516f4413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614718671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.614718671
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2527165005
Short name T593
Test name
Test status
Simulation time 330230366378 ps
CPU time 175.98 seconds
Started Jul 05 06:03:55 PM PDT 24
Finished Jul 05 06:06:51 PM PDT 24
Peak memory 201908 kb
Host smart-66e5f867-c14c-4d4c-945b-4718e069c8f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527165005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2527165005
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2677391203
Short name T274
Test name
Test status
Simulation time 161941154490 ps
CPU time 391.77 seconds
Started Jul 05 06:03:55 PM PDT 24
Finished Jul 05 06:10:27 PM PDT 24
Peak memory 201924 kb
Host smart-9a373b44-77a0-408c-b65f-acc4b7081b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677391203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2677391203
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3965043816
Short name T389
Test name
Test status
Simulation time 163942400576 ps
CPU time 370.74 seconds
Started Jul 05 06:03:58 PM PDT 24
Finished Jul 05 06:10:09 PM PDT 24
Peak memory 201904 kb
Host smart-530980e2-7e39-4f1a-a7a5-e6edbc08af7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965043816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3965043816
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2345448774
Short name T190
Test name
Test status
Simulation time 493505873764 ps
CPU time 335.8 seconds
Started Jul 05 06:03:54 PM PDT 24
Finished Jul 05 06:09:30 PM PDT 24
Peak memory 201972 kb
Host smart-21b55265-69a3-47be-b2bd-2b1245fd92d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345448774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2345448774
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.824971250
Short name T741
Test name
Test status
Simulation time 484386770675 ps
CPU time 549.91 seconds
Started Jul 05 06:03:54 PM PDT 24
Finished Jul 05 06:13:04 PM PDT 24
Peak memory 201916 kb
Host smart-449f3512-c422-406e-8a31-e47ea5d45336
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=824971250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.824971250
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2642455353
Short name T777
Test name
Test status
Simulation time 193169794647 ps
CPU time 62.11 seconds
Started Jul 05 06:03:53 PM PDT 24
Finished Jul 05 06:04:55 PM PDT 24
Peak memory 201860 kb
Host smart-24290d57-306b-429e-bdbe-3644188261fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642455353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2642455353
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.594197409
Short name T484
Test name
Test status
Simulation time 84862697642 ps
CPU time 324.95 seconds
Started Jul 05 06:03:55 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 202280 kb
Host smart-42e3eb88-0aa0-450b-bc66-99f018b1bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594197409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.594197409
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1849033194
Short name T649
Test name
Test status
Simulation time 39356314156 ps
CPU time 48.71 seconds
Started Jul 05 06:03:58 PM PDT 24
Finished Jul 05 06:04:47 PM PDT 24
Peak memory 201724 kb
Host smart-371ce3e8-ae49-4c9d-a351-18b0e5a6dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849033194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1849033194
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.890309418
Short name T791
Test name
Test status
Simulation time 5383847482 ps
CPU time 13.61 seconds
Started Jul 05 06:03:54 PM PDT 24
Finished Jul 05 06:04:08 PM PDT 24
Peak memory 201724 kb
Host smart-66297717-8af0-4073-970d-7473af678f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890309418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.890309418
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1280374342
Short name T461
Test name
Test status
Simulation time 5868141752 ps
CPU time 3.8 seconds
Started Jul 05 06:03:53 PM PDT 24
Finished Jul 05 06:03:58 PM PDT 24
Peak memory 201732 kb
Host smart-be959a23-7a31-497e-a8c8-6c5c458aaa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280374342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1280374342
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2319076986
Short name T641
Test name
Test status
Simulation time 238692587476 ps
CPU time 504.15 seconds
Started Jul 05 06:04:02 PM PDT 24
Finished Jul 05 06:12:26 PM PDT 24
Peak memory 201916 kb
Host smart-ff535a7d-70b2-4604-9ae5-7c61def3c66c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319076986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2319076986
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1009447692
Short name T272
Test name
Test status
Simulation time 62932066262 ps
CPU time 133.98 seconds
Started Jul 05 06:04:01 PM PDT 24
Finished Jul 05 06:06:15 PM PDT 24
Peak memory 210256 kb
Host smart-fdf619e2-3159-4448-b5ef-0ffa9d17fa56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009447692 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1009447692
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1084859569
Short name T672
Test name
Test status
Simulation time 362370324 ps
CPU time 0.79 seconds
Started Jul 05 06:00:12 PM PDT 24
Finished Jul 05 06:00:13 PM PDT 24
Peak memory 201616 kb
Host smart-dc5ca73c-e9b2-4b07-aeac-78bc8ee4dd58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084859569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1084859569
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1221281827
Short name T180
Test name
Test status
Simulation time 568034011406 ps
CPU time 324.28 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:05:16 PM PDT 24
Peak memory 201916 kb
Host smart-9fd03f82-1461-4b9a-8fe3-908b27f893a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221281827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1221281827
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3015812397
Short name T138
Test name
Test status
Simulation time 326683160749 ps
CPU time 766.19 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:13:02 PM PDT 24
Peak memory 201904 kb
Host smart-6137bd56-492f-4bb0-bf3e-63951b539520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015812397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3015812397
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1465770777
Short name T361
Test name
Test status
Simulation time 492230941113 ps
CPU time 1036.8 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 06:17:09 PM PDT 24
Peak memory 201904 kb
Host smart-c3accd17-e60a-49df-8a96-f20573600f5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465770777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1465770777
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1267507769
Short name T298
Test name
Test status
Simulation time 161340304256 ps
CPU time 101.48 seconds
Started Jul 05 06:00:11 PM PDT 24
Finished Jul 05 06:01:53 PM PDT 24
Peak memory 201916 kb
Host smart-9629f379-d0ea-4ab4-b77a-0eeada2b2b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267507769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1267507769
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2598318052
Short name T481
Test name
Test status
Simulation time 167817152864 ps
CPU time 183.16 seconds
Started Jul 05 05:59:48 PM PDT 24
Finished Jul 05 06:02:52 PM PDT 24
Peak memory 201904 kb
Host smart-091cf832-4332-47c4-9c39-591560b1fac1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598318052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2598318052
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1396728301
Short name T540
Test name
Test status
Simulation time 208829852278 ps
CPU time 110.01 seconds
Started Jul 05 06:00:06 PM PDT 24
Finished Jul 05 06:01:56 PM PDT 24
Peak memory 201876 kb
Host smart-ae152904-a482-4c29-92c1-754cae848f1e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396728301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1396728301
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3265285937
Short name T359
Test name
Test status
Simulation time 71876866202 ps
CPU time 265.65 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:04:42 PM PDT 24
Peak memory 202216 kb
Host smart-d7934e25-ed2a-4119-83b8-4418970be81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265285937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3265285937
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1809612743
Short name T721
Test name
Test status
Simulation time 31937673553 ps
CPU time 8.24 seconds
Started Jul 05 06:00:04 PM PDT 24
Finished Jul 05 06:00:13 PM PDT 24
Peak memory 201712 kb
Host smart-aabdc365-41c7-4871-a534-a70b8b21c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809612743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1809612743
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3235293577
Short name T640
Test name
Test status
Simulation time 4875557050 ps
CPU time 6.08 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:00:23 PM PDT 24
Peak memory 201704 kb
Host smart-47e71f97-4da8-4ee8-a4b2-14705b9a1da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235293577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3235293577
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2943096301
Short name T561
Test name
Test status
Simulation time 6048600689 ps
CPU time 4.72 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 05:59:59 PM PDT 24
Peak memory 201668 kb
Host smart-3451ea00-1c23-4d1e-8cab-227ec9d9a844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943096301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2943096301
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.626528049
Short name T708
Test name
Test status
Simulation time 202296724325 ps
CPU time 193.42 seconds
Started Jul 05 06:00:12 PM PDT 24
Finished Jul 05 06:03:26 PM PDT 24
Peak memory 201920 kb
Host smart-1631099c-e02a-4b88-bcd3-28a15e4765bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626528049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.626528049
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3602832232
Short name T39
Test name
Test status
Simulation time 77475808528 ps
CPU time 169.07 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:03:02 PM PDT 24
Peak memory 218296 kb
Host smart-1c11a863-d548-4b0e-a015-6509fd9e0bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602832232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3602832232
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3106407378
Short name T758
Test name
Test status
Simulation time 378193187 ps
CPU time 0.83 seconds
Started Jul 05 06:00:09 PM PDT 24
Finished Jul 05 06:00:10 PM PDT 24
Peak memory 201628 kb
Host smart-ca7c1a47-1a61-459e-9459-550ee84871b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106407378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3106407378
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2968654587
Short name T786
Test name
Test status
Simulation time 194014392672 ps
CPU time 77.9 seconds
Started Jul 05 05:59:58 PM PDT 24
Finished Jul 05 06:01:16 PM PDT 24
Peak memory 201908 kb
Host smart-8108ce77-0917-4287-a168-1439c0cd4ce7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968654587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2968654587
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3992960592
Short name T153
Test name
Test status
Simulation time 334549578246 ps
CPU time 369.07 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:06:23 PM PDT 24
Peak memory 201872 kb
Host smart-0e6b7564-8ba6-481c-8aa7-ffee84b06bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992960592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3992960592
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3804964381
Short name T522
Test name
Test status
Simulation time 494016612774 ps
CPU time 298.49 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 06:04:52 PM PDT 24
Peak memory 201892 kb
Host smart-6079550e-0e61-4112-9b13-ef19a0a787dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804964381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3804964381
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3013118348
Short name T112
Test name
Test status
Simulation time 323439629083 ps
CPU time 742.42 seconds
Started Jul 05 05:59:52 PM PDT 24
Finished Jul 05 06:12:16 PM PDT 24
Peak memory 201936 kb
Host smart-fb9d87bb-9d14-49c7-8bb6-e6cf5cada0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013118348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3013118348
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2584463430
Short name T173
Test name
Test status
Simulation time 163296849578 ps
CPU time 98.29 seconds
Started Jul 05 05:59:59 PM PDT 24
Finished Jul 05 06:01:38 PM PDT 24
Peak memory 201916 kb
Host smart-9e0b34b2-7f81-4877-8549-fd4d742a139b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584463430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2584463430
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3882035737
Short name T301
Test name
Test status
Simulation time 393481600268 ps
CPU time 836.79 seconds
Started Jul 05 06:00:09 PM PDT 24
Finished Jul 05 06:14:06 PM PDT 24
Peak memory 201988 kb
Host smart-53185472-7124-4fbc-b68f-f1eaac1440e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882035737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3882035737
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3713790862
Short name T488
Test name
Test status
Simulation time 610176507429 ps
CPU time 1314.57 seconds
Started Jul 05 06:00:00 PM PDT 24
Finished Jul 05 06:21:55 PM PDT 24
Peak memory 201888 kb
Host smart-2759271f-999f-4ee8-a382-3f85f3b743c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713790862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3713790862
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.4096019607
Short name T347
Test name
Test status
Simulation time 124391228890 ps
CPU time 397.23 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:06:45 PM PDT 24
Peak memory 202208 kb
Host smart-35668051-b39f-4dda-91b6-6872331aa0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096019607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.4096019607
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1039412682
Short name T514
Test name
Test status
Simulation time 38087334542 ps
CPU time 22.46 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:00:31 PM PDT 24
Peak memory 201716 kb
Host smart-72f9d205-bc9d-4850-93b2-6118211f68ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039412682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1039412682
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3558848399
Short name T48
Test name
Test status
Simulation time 3709753859 ps
CPU time 9.34 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:00:26 PM PDT 24
Peak memory 201724 kb
Host smart-ddf28dea-353b-415f-8c3c-4b5c38b0e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558848399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3558848399
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3744194108
Short name T665
Test name
Test status
Simulation time 5869708376 ps
CPU time 4.01 seconds
Started Jul 05 05:59:53 PM PDT 24
Finished Jul 05 05:59:58 PM PDT 24
Peak memory 201720 kb
Host smart-7a816573-b247-4c0b-ab33-b63ab4b73274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744194108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3744194108
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1217552715
Short name T726
Test name
Test status
Simulation time 40573770091 ps
CPU time 12.43 seconds
Started Jul 05 05:59:53 PM PDT 24
Finished Jul 05 06:00:06 PM PDT 24
Peak memory 201716 kb
Host smart-6a79338a-eddc-46b2-9cbd-a455fcd0a569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217552715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1217552715
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3685306987
Short name T37
Test name
Test status
Simulation time 94634398807 ps
CPU time 330.71 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:05:22 PM PDT 24
Peak memory 218196 kb
Host smart-4269745d-2239-4013-ae36-c4fcb8fa82fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685306987 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3685306987
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2322346653
Short name T467
Test name
Test status
Simulation time 506824998 ps
CPU time 0.98 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:00:16 PM PDT 24
Peak memory 201644 kb
Host smart-4b50d81d-66b2-4fb5-8eec-08e7b4ef8c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322346653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2322346653
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1511377241
Short name T167
Test name
Test status
Simulation time 329622193172 ps
CPU time 399.31 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:06:55 PM PDT 24
Peak memory 201984 kb
Host smart-53ad68b3-0872-44fb-87e3-95eebbbdd12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511377241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1511377241
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2921751569
Short name T131
Test name
Test status
Simulation time 488489866841 ps
CPU time 389.75 seconds
Started Jul 05 06:00:07 PM PDT 24
Finished Jul 05 06:06:38 PM PDT 24
Peak memory 201972 kb
Host smart-a2d5af1c-b4ec-48b0-9257-ceef90a5e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921751569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2921751569
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.10867849
Short name T526
Test name
Test status
Simulation time 162801200560 ps
CPU time 282.44 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:04:33 PM PDT 24
Peak memory 201900 kb
Host smart-5948d5ea-202a-4a6e-a00d-d2c3024413bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10867849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt_
fixed.10867849
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1109651129
Short name T282
Test name
Test status
Simulation time 325525737681 ps
CPU time 172.95 seconds
Started Jul 05 06:00:02 PM PDT 24
Finished Jul 05 06:02:56 PM PDT 24
Peak memory 201888 kb
Host smart-26410b58-814b-4259-b8f8-fb837b403486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109651129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1109651129
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3530803071
Short name T608
Test name
Test status
Simulation time 484609298871 ps
CPU time 313.79 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:05:30 PM PDT 24
Peak memory 201924 kb
Host smart-bf046910-df15-42ce-80d2-fc87bd0ef6a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530803071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3530803071
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.692718119
Short name T236
Test name
Test status
Simulation time 551584220100 ps
CPU time 679.02 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:11:09 PM PDT 24
Peak memory 201980 kb
Host smart-b7020943-5619-43e9-8d76-4f89f20db6ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692718119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.692718119
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.14018363
Short name T371
Test name
Test status
Simulation time 187275603550 ps
CPU time 456.13 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:07:51 PM PDT 24
Peak memory 201896 kb
Host smart-58b7b894-7840-4e9e-936f-a759ac3ce8b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14018363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.ad
c_ctrl_filters_wakeup_fixed.14018363
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2428843599
Short name T624
Test name
Test status
Simulation time 81477395876 ps
CPU time 252.76 seconds
Started Jul 05 06:00:11 PM PDT 24
Finished Jul 05 06:04:24 PM PDT 24
Peak memory 202248 kb
Host smart-787b774c-00c1-41dd-b1e8-03f6850a49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428843599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2428843599
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1081521130
Short name T700
Test name
Test status
Simulation time 43640348247 ps
CPU time 27.12 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:00:20 PM PDT 24
Peak memory 201700 kb
Host smart-bf9d29ca-a08a-4609-82f6-f395053f92b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081521130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1081521130
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.352253453
Short name T388
Test name
Test status
Simulation time 3610583513 ps
CPU time 4.64 seconds
Started Jul 05 05:59:51 PM PDT 24
Finished Jul 05 05:59:57 PM PDT 24
Peak memory 201620 kb
Host smart-0410a782-c9c6-444b-8608-0cc16f73c5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352253453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.352253453
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2468485632
Short name T746
Test name
Test status
Simulation time 6011850774 ps
CPU time 4.08 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:00:12 PM PDT 24
Peak memory 201692 kb
Host smart-685cdc5a-7bc9-4345-a6b6-73b925a18ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468485632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2468485632
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.741461455
Short name T529
Test name
Test status
Simulation time 163502102515 ps
CPU time 100.34 seconds
Started Jul 05 06:00:15 PM PDT 24
Finished Jul 05 06:01:56 PM PDT 24
Peak memory 201912 kb
Host smart-bd26c262-5270-4c8e-9125-2bdd400ce1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741461455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.741461455
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2188405192
Short name T94
Test name
Test status
Simulation time 305244976 ps
CPU time 1.3 seconds
Started Jul 05 05:59:56 PM PDT 24
Finished Jul 05 05:59:58 PM PDT 24
Peak memory 201676 kb
Host smart-f683f815-6b4f-46a4-87a1-a4b8db06eb55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188405192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2188405192
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.72935749
Short name T576
Test name
Test status
Simulation time 162513899917 ps
CPU time 340.29 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:05:54 PM PDT 24
Peak memory 201912 kb
Host smart-1f3d9210-eaf2-4b48-ad22-e49a8e1ec64b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72935749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating
.72935749
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.132039803
Short name T107
Test name
Test status
Simulation time 166052280618 ps
CPU time 208.35 seconds
Started Jul 05 05:59:49 PM PDT 24
Finished Jul 05 06:03:19 PM PDT 24
Peak memory 201980 kb
Host smart-6223aa5e-a3cb-4bf0-9e10-fed07b957a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132039803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.132039803
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.54661004
Short name T474
Test name
Test status
Simulation time 326771385124 ps
CPU time 192.49 seconds
Started Jul 05 05:59:53 PM PDT 24
Finished Jul 05 06:03:06 PM PDT 24
Peak memory 201892 kb
Host smart-bd8221f2-baba-498b-b66c-c300e23b51d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=54661004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_
fixed.54661004
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3638680676
Short name T333
Test name
Test status
Simulation time 487311853034 ps
CPU time 1179.69 seconds
Started Jul 05 06:00:08 PM PDT 24
Finished Jul 05 06:19:48 PM PDT 24
Peak memory 201988 kb
Host smart-61d2434f-4061-499c-a3b5-0396002943e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638680676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3638680676
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4208454925
Short name T508
Test name
Test status
Simulation time 326723887402 ps
CPU time 181.22 seconds
Started Jul 05 06:00:16 PM PDT 24
Finished Jul 05 06:03:18 PM PDT 24
Peak memory 201964 kb
Host smart-35472fbe-9bc5-4506-b888-7471a564037f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208454925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.4208454925
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2658739047
Short name T677
Test name
Test status
Simulation time 172532839632 ps
CPU time 193.84 seconds
Started Jul 05 05:59:57 PM PDT 24
Finished Jul 05 06:03:11 PM PDT 24
Peak memory 201936 kb
Host smart-38bde86e-6292-4baa-a90e-0d59e3f08593
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658739047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2658739047
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1382905191
Short name T164
Test name
Test status
Simulation time 411046422662 ps
CPU time 236.8 seconds
Started Jul 05 05:59:54 PM PDT 24
Finished Jul 05 06:03:52 PM PDT 24
Peak memory 201900 kb
Host smart-01bf6bed-2fe9-425d-b2c0-3329ad2cc87d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382905191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1382905191
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2843613602
Short name T736
Test name
Test status
Simulation time 104380607971 ps
CPU time 543.35 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 202080 kb
Host smart-3589cb2f-0b9f-4184-bfa7-3f96c87f56cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843613602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2843613602
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2690088239
Short name T496
Test name
Test status
Simulation time 31365650266 ps
CPU time 71.74 seconds
Started Jul 05 06:00:00 PM PDT 24
Finished Jul 05 06:01:12 PM PDT 24
Peak memory 201700 kb
Host smart-209804b3-0be3-4580-bbda-b25880f611de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690088239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2690088239
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1466615394
Short name T452
Test name
Test status
Simulation time 4364163573 ps
CPU time 5.44 seconds
Started Jul 05 05:59:50 PM PDT 24
Finished Jul 05 05:59:57 PM PDT 24
Peak memory 201716 kb
Host smart-1ebd63c6-0f1d-4f62-b93d-720b12c007b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466615394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1466615394
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1630144605
Short name T664
Test name
Test status
Simulation time 5769921407 ps
CPU time 1.98 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:00:17 PM PDT 24
Peak memory 201736 kb
Host smart-32a87e48-ed63-4194-9274-486ec47c1b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630144605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1630144605
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1206622652
Short name T391
Test name
Test status
Simulation time 510820601 ps
CPU time 0.91 seconds
Started Jul 05 06:00:10 PM PDT 24
Finished Jul 05 06:00:12 PM PDT 24
Peak memory 201660 kb
Host smart-b2816716-0a63-4c59-8427-73ee471bc952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206622652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1206622652
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2450873635
Short name T314
Test name
Test status
Simulation time 159805765761 ps
CPU time 103.77 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:01:58 PM PDT 24
Peak memory 201968 kb
Host smart-f0c3a3ce-e6e5-499d-a76e-b73a038557cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450873635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2450873635
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1603572973
Short name T655
Test name
Test status
Simulation time 494093576590 ps
CPU time 603.89 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:10:18 PM PDT 24
Peak memory 201656 kb
Host smart-01242e37-3f54-42ea-a929-8bc9cac4af08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603572973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1603572973
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.454854632
Short name T150
Test name
Test status
Simulation time 484534483859 ps
CPU time 281.48 seconds
Started Jul 05 05:59:56 PM PDT 24
Finished Jul 05 06:04:37 PM PDT 24
Peak memory 201932 kb
Host smart-55090e63-243c-4697-9a9c-76a8343d5ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454854632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.454854632
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2261329102
Short name T439
Test name
Test status
Simulation time 487250544921 ps
CPU time 994.94 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:16:52 PM PDT 24
Peak memory 201912 kb
Host smart-ed21ae4d-e042-48ff-8b7a-8bdaee42d37c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261329102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2261329102
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1040031401
Short name T235
Test name
Test status
Simulation time 423703386675 ps
CPU time 921.92 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:15:36 PM PDT 24
Peak memory 201928 kb
Host smart-0865047f-7455-4458-bace-ee58bb9bddca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040031401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1040031401
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1180009369
Short name T41
Test name
Test status
Simulation time 198170065821 ps
CPU time 226.81 seconds
Started Jul 05 06:00:18 PM PDT 24
Finished Jul 05 06:04:06 PM PDT 24
Peak memory 201916 kb
Host smart-f9ac9d69-c026-48ef-89bf-ba699603a5b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180009369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1180009369
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1284543586
Short name T546
Test name
Test status
Simulation time 84660126470 ps
CPU time 258.77 seconds
Started Jul 05 06:00:12 PM PDT 24
Finished Jul 05 06:04:31 PM PDT 24
Peak memory 202212 kb
Host smart-38049196-c316-4a91-83cd-1e041c1b219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284543586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1284543586
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1716916824
Short name T383
Test name
Test status
Simulation time 38697035069 ps
CPU time 45.18 seconds
Started Jul 05 06:00:17 PM PDT 24
Finished Jul 05 06:01:03 PM PDT 24
Peak memory 201728 kb
Host smart-93c54426-bda4-4ec0-aa71-1a079bd41676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716916824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1716916824
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3839549190
Short name T374
Test name
Test status
Simulation time 3501306100 ps
CPU time 2.49 seconds
Started Jul 05 06:00:05 PM PDT 24
Finished Jul 05 06:00:08 PM PDT 24
Peak memory 201716 kb
Host smart-a139d2c6-ab37-4739-8eaa-9dbff7c36699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839549190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3839549190
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3710894419
Short name T728
Test name
Test status
Simulation time 6051944975 ps
CPU time 13.23 seconds
Started Jul 05 06:00:11 PM PDT 24
Finished Jul 05 06:00:25 PM PDT 24
Peak memory 201688 kb
Host smart-31ed1674-8dda-4840-a70c-13676b62afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710894419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3710894419
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2270075073
Short name T316
Test name
Test status
Simulation time 374999435341 ps
CPU time 903.44 seconds
Started Jul 05 06:00:13 PM PDT 24
Finished Jul 05 06:15:17 PM PDT 24
Peak memory 201708 kb
Host smart-386d68d6-261f-4488-ad5e-a96ff4985c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270075073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2270075073
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3061373664
Short name T307
Test name
Test status
Simulation time 250468103647 ps
CPU time 79.36 seconds
Started Jul 05 06:00:14 PM PDT 24
Finished Jul 05 06:01:35 PM PDT 24
Peak memory 210296 kb
Host smart-fadbdb85-d085-4bbd-a399-9f758a240caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061373664 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3061373664
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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