Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7958	1			T2	3		T6	6		T9	47
testmodes[AdcCtrlTestmodeNormal]	6319	1			T1	2		T2	12		T3	3
testmodes[AdcCtrlTestmodeLowpower]	6398	1			T4	1		T5	1		T6	25
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4277	1			T6	1		T9	32		T40	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	2010	1			T2	3		T6	2		T9	9
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1563	1			T6	3		T9	6		T45	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1942	1			T2	3		T9	8		T87	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2347	1			T1	1		T2	8		T3	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1682	1			T6	3		T9	7		T45	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1622	1			T6	5		T9	7		T45	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1615	1			T6	2		T9	5		T45	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2917	1			T6	18		T9	2		T34	2