Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25717

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3203

1

T3

2

T5

11

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22710

1

T2

15

T3

2

T4

13

auto[1]

6210

1

T1

20

T3

1

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T139	1		T219	3		-	-
values[0]	132	1			T142	12		T186	29		T178	1
values[1]	731	1			T10	15		T151	1		T37	8
values[2]	720	1			T3	1		T139	1		T12	4
values[3]	578	1			T3	1		T35	17		T12	18
values[4]	585	1			T3	1		T10	10		T26	1
values[5]	716	1			T6	7		T33	5		T110	2
values[6]	656	1			T4	13		T6	1		T8	17
values[7]	515	1			T9	2		T103	16		T38	1
values[8]	705	1			T7	7		T67	14		T133	17
values[9]	3814	1			T1	20		T5	11		T9	4
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1026	1			T12	4		T22	5		T151	1
values[1]	711	1			T3	2		T10	15		T35	17
values[2]	543	1			T12	18		T27	12		T140	17
values[3]	559	1			T3	1		T6	7		T10	10
values[4]	761	1			T4	13		T8	17		T110	1
values[5]	683	1			T6	1		T110	1		T36	18
values[6]	2630	1			T1	20		T9	2		T34	46
values[7]	857	1			T7	7		T11	30		T67	14
values[8]	1126	1			T5	11		T9	4		T35	17
values[9]	252	1			T139	1		T110	1		T103	8
minimum	19772	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T12	4		T22	1		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T37	2		T141	1		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T35	17		T139	1		T27	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	2		T10	1		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	9		T27	12		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	13		T16	4		T144	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	1		T33	5		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	6		T10	1		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	13		T110	1		T24	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	6		T101	1		T106	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T110	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T36	3		T38	1		T142	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T1	2		T9	1		T34	46
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T181	1		T172	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T11	16		T67	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T39	9		T141	1		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T9	4		T50	17		T180	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	6		T35	17		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T103	8		T220	7		T168	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T139	1		T110	1		T106	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19619	1			T2	15		T6	31		T9	81
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T22	4		T136	14		T164	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	4		T164	13		T221	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T180	12		T222	6		T149	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T10	14		T31	2		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	9		T140	10		T105	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T38	12		T16	3		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T149	2		T223	4		T224	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	1		T10	9		T173	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	13		T180	14		T172	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	11		T147	9		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T36	5		T226	13		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	2		T38	2		T227	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T1	18		T9	1		T107	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T181	10		T172	16		T145	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	6		T11	14		T67	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T39	3		T16	6		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T50	17		T180	10		T228	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	5		T38	1		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T220	2		T168	11		T230	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T172	15		T231	11		T232	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	2		T33	1		T67	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T219	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T139	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T186	17		T178	1		T202	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T142	12		T233	5		T234	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T151	1		T37	4		T106	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T15	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T139	1		T12	4		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T37	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	17		T12	9		T27	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	1		T13	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T140	7		T163	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T26	1		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	5		T110	2		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	6		T26	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	13		T6	1		T36	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	6		T36	3		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T103	16		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T181	1		T16	10		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	1		T67	1		T133	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	9		T141	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1863	1			T1	2		T9	4		T11	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	422	1			T5	6		T35	17		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T186	12		T202	15		T236	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T233	9		T234	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	4		T136	14		T164	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	14		T15	3		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T22	4		T222	6		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T15	2		T16	3		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	9		T105	14		T180	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T31	2		T144	2		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T140	10		T149	2		T155	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	9		T38	12		T173	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T24	13		T146	7		T157	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	1		T147	9		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T36	5		T180	14		T172	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	11		T36	2		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T150	6		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T181	10		T16	6		T235	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	6		T67	13		T133	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	3		T172	16		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T1	18		T11	14		T107	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T5	5		T38	1		T172	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T12	1		T22	5		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	2		T141	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T35	1		T139	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	2		T10	15		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	13		T27	1		T140	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	14		T16	5		T144	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T33	3		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	5		T10	10		T26	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T110	1		T24	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	12		T101	1		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T6	1		T110	1		T36	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T36	3		T38	3		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T1	20		T9	2		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T181	11		T172	17		T145	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	7		T11	15		T67	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T39	9		T141	1		T16	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T9	3		T50	18		T180	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	6		T35	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T103	1		T220	3		T168	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T139	1		T110	1		T106	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19771	1			T2	15		T6	31		T9	83
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T12	3		T106	16		T136	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T142	11		T15	2		T164	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	16		T27	7		T180	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T144	4		T154	14		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	5		T27	11		T140	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	11		T16	2		T144	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T33	2		T149	3		T223	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	2		T148	1		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	12		T24	13		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	5		T106	13		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	5		T163	6		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	2		T142	17		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T34	43		T43	15		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T165	8		T232	8		T240	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	15		T133	8		T14	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T39	3		T16	8		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T9	1		T50	16		T180	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	5		T35	16		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T103	7		T220	6		T168	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T106	13		T231	11		T232	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T37	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T139	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T186	13		T178	1		T202	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T142	1		T233	10		T234	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T151	1		T37	7		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	15		T15	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T139	1		T12	1		T22	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T37	2		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	1		T12	13		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	1		T13	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T140	11		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	10		T26	1		T38	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T33	3		T110	2		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	5		T26	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	1		T6	1		T36	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	12		T36	3		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	2		T103	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T181	11		T16	8		T235	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	7		T67	14		T133	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	9		T141	1		T172	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T1	20		T9	3		T11	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T5	6		T35	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T219	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T186	16		T202	17		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T142	11		T233	4		T234	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	1		T106	16		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T221	13		T241	8		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	3		T27	7		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	2		T16	2		T144	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	16		T12	5		T27	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T144	2		T148	1		T174	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T140	6		T163	12		T149	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	11		T165	6		T185	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	2		T24	13		T146	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	2		T106	13		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T4	12		T36	5		T180	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	5		T36	2		T142	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T103	15		T135	4		T163	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T16	8		T165	8		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	8		T14	7		T243	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T39	3		T32	12		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T9	1		T11	15		T34	43
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T5	5		T35	16		T106	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25242

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3678

1

T3

2

T8

17

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23163

1

T2

15

T3

2

T4

13

auto[1]

5757

1

T1

20

T3

1

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T244	1		-	-		-	-
values[0]	100	1			T137	1		T79	15		T245	5
values[1]	634	1			T67	14		T139	1		T26	1
values[2]	2884	1			T1	20		T10	10		T34	46
values[3]	747	1			T3	1		T4	13		T110	1
values[4]	676	1			T35	17		T110	1		T103	16
values[5]	666	1			T37	8		T38	1		T106	14
values[6]	663	1			T6	1		T33	5		T26	1
values[7]	842	1			T5	11		T8	17		T11	30
values[8]	787	1			T3	2		T6	7		T9	6
values[9]	1156	1			T7	7		T10	15		T35	17
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	989	1			T10	10		T67	14		T139	1
values[1]	2807	1			T1	20		T4	13		T34	46
values[2]	621	1			T3	1		T110	1		T246	1
values[3]	696	1			T35	17		T110	1		T103	16
values[4]	719	1			T6	1		T26	1		T36	13
values[5]	801	1			T5	11		T11	30		T33	5
values[6]	715	1			T8	17		T110	1		T26	1
values[7]	844	1			T3	1		T6	7		T9	6
values[8]	787	1			T3	1		T7	7		T10	15
values[9]	157	1			T22	5		T142	12		T153	1
minimum	19784	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T139	1		T12	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T67	1		T106	17		T135	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	2		T4	13		T34	46
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	1		T39	9		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T110	1		T154	13		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T246	1		T221	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T110	1		T106	28		T180	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T35	17		T103	16		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	1		T37	4		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	1		T36	8		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	6		T11	16		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	5		T101	1		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T26	1		T28	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	6		T110	1		T27	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T6	6		T9	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	1		T162	10		T32	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T24	14		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	1		T10	1		T35	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T248	1		T249	1		T250	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T22	1		T142	12		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19619	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T251	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	9		T12	9		T38	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T67	13		T173	1		T150	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T1	18		T107	21		T109	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T38	1		T39	3		T172	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T237	13		T252	11		T253	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T221	7		T223	1		T185	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T180	12		T145	13		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T181	10		T229	14		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	4		T15	1		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T36	5		T50	17		T164	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	5		T11	14		T180	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T136	14		T239	2		T165	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T32	13		T146	7		T222	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	11		T133	8		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T14	7		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	1		T32	18		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	6		T24	13		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T10	14		T105	14		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T248	5		T250	3		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T22	4		T218	8		T234	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T251	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T137	1		T245	4		T255	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T79	5		T244	1		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T139	1		T26	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T67	1		T39	9		T135	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T1	2		T10	1		T34	46
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T106	17		T143	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	13		T110	1		T180	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T38	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T110	1		T106	14		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T35	17		T103	16		T50	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	4		T106	14		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T38	1		T31	1		T256	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T16	10		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	5		T26	1		T27	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	6		T11	16		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	6		T133	9		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T6	6		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T9	1		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T7	1		T139	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T10	1		T35	17		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T245	1		T257	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T79	10		T244	12		T30	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T38	12		T226	13		T187	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T67	13		T39	3		T173	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T1	18		T10	9		T107	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T221	7		T148	2		T258	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T180	12		T165	3		T259	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T38	1		T172	16		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T145	13		T148	2		T187	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	17		T181	10		T229	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T37	4		T15	1		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T221	2		T219	15		T188	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	6		T138	3		T157	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T36	5		T164	3		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	5		T11	14		T180	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	11		T133	8		T136	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	1		T14	7		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T38	2		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	6		T24	13		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T10	14		T22	4		T105	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1