Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25574

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3346

1

T3

2

T4

13

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22951

1

T2

15

T3

1

T5

11

auto[1]

5969

1

T1

20

T3

2

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T5	11		T146	19		T149	11
values[0]	63	1			T4	13		T27	12		T273	12
values[1]	684	1			T139	1		T133	17		T37	2
values[2]	635	1			T9	2		T106	14		T136	29
values[3]	920	1			T110	1		T28	1		T103	8
values[4]	527	1			T139	1		T22	5		T101	1
values[5]	2586	1			T1	20		T6	1		T7	7
values[6]	704	1			T8	17		T11	30		T12	18
values[7]	762	1			T9	4		T35	34		T26	2
values[8]	726	1			T3	3		T10	10		T67	14
values[9]	1286	1			T6	7		T10	15		T33	5
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	575	1			T4	13		T133	17		T37	2
values[1]	730	1			T9	2		T103	8		T106	14
values[2]	721	1			T110	1		T22	5		T28	1
values[3]	2757	1			T1	20		T6	1		T34	46
values[4]	410	1			T7	7		T12	4		T281	1
values[5]	731	1			T8	17		T11	30		T35	17
values[6]	810	1			T3	1		T9	4		T35	17
values[7]	746	1			T3	2		T10	10		T110	1
values[8]	1163	1			T5	11		T6	7		T10	15
values[9]	148	1			T151	1		T38	3		T324	8
minimum	20129	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T133	9		T37	2		T181	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	13		T136	15		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T103	8		T106	14		T180	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T32	30		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T22	1		T141	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T110	1		T28	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T1	2		T6	1		T34	46
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T38	1		T243	9		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	4		T281	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	1		T274	9		T277	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	6		T11	16		T35	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	9		T13	1		T24	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T35	17		T67	1		T27	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	1		T9	4		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	1		T110	1		T37	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T10	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T6	6		T33	5		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T5	6		T10	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T151	1		T38	1		T231	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T324	5		T269	2		T30	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19717	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T139	1		T164	4		T221	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	8		T181	10		T218	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T136	14		T226	13		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T180	10		T32	5		T138	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T9	1		T32	26		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T22	4		T222	1		T174	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T105	14		T172	23		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T1	18		T107	21		T109	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	7		T144	3		T222	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T173	1		T148	2		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	6		T274	8		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	11		T11	14		T180	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	9		T24	13		T36	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T67	13		T221	13		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T50	17		T15	1		T223	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T37	4		T180	14		T172	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	9		T140	10		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T6	1		T146	10		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	5		T10	14		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T38	2		T231	11		T232	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T324	3		T30	8		T325	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T164	3		T221	7		T239	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T146	9		T149	3		T187	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T5	6		T149	4		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T27	12		T326	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T4	13		T273	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T133	9		T37	2		T181	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	1		T246	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T106	14		T142	12		T243	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T136	15		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T103	8		T180	14		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T110	1		T28	1		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T139	1		T22	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T38	1		T172	1		T243	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T1	2		T6	1		T34	46
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	1		T222	1		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	6		T11	16		T180	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	9		T13	1		T24	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T35	34		T26	1		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	4		T26	1		T106	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	1		T67	1		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	2		T10	1		T14	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T6	6		T33	5		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T10	1		T139	1		T140	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T146	10		T149	2		T187	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T5	5		T149	2		T155	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T326	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T133	8		T181	10		T173	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T226	13		T164	3		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T138	3		T320	12		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T9	1		T136	14		T150	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T180	10		T32	5		T221	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T105	14		T172	15		T32	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T22	4		T148	2		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T172	8		T146	7		T144	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T1	18		T107	21		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	6		T222	13		T274	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	11		T11	14		T180	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	9		T24	13		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T144	1		T221	13		T228	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T50	17		T223	1		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T67	13		T37	4		T180	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T10	9		T14	7		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T6	1		T38	2		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	14		T140	10		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	9		T37	2		T181	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	1		T136	15		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T103	1		T106	1		T180	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	2		T32	28		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T22	5		T141	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T110	1		T28	1		T105	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T1	20		T6	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	1		T243	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T281	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	7		T274	9		T277	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	12		T11	15		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	13		T13	1		T24	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T35	1		T67	14		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T9	3		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T110	1		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	1		T10	10		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T6	5		T33	3		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T5	6		T10	15		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T151	1		T38	3		T231	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T324	4		T269	2		T30	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19872	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T139	1		T164	4		T221	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T133	8		T142	11		T260	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	12		T136	14		T263	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T103	7		T106	13		T180	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	28		T261	10		T291	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T174	8		T227	7		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T228	12		T324	9		T185	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T34	43		T43	15		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T243	8		T146	7		T144	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	3		T173	1		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T274	8		T277	19		T185	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	5		T11	15		T35	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	5		T24	13		T36	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T35	16		T27	7		T106	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	1		T106	13		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	1		T135	4		T180	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	6		T14	7		T38	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	2		T33	2		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	5		T36	2		T103	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T231	11		T232	2		T299	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T324	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T27	11		T324	20		T327	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T164	3		T221	10		T239	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T146	11		T149	3		T187	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T5	6		T149	3		T155	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T27	1		T326	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T4	1		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T133	9		T37	2		T181	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	1		T246	1		T226	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T106	1		T142	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T9	2		T136	15		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T103	1		T180	11		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T110	1		T28	1		T105	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T139	1		T22	5		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	1		T172	9		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T1	20		T6	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	7		T222	14		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	12		T11	15		T180	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	13		T13	1		T24	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	2		T26	1		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	3		T26	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T67	14		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	2		T10	10		T14	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T6	5		T33	3		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T10	15		T139	1		T140	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T146	8		T149	2		T238	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T5	5		T149	3		T266	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T27	11		T326	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T4	12		T273	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	8		T260	18		T218	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T164	3		T263	9		T221	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T106	13		T142	11		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T136	14		T242	11		T261	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T103	7		T180	13		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	28		T228	12		T324	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T148	2		T149	3		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T243	8		T146	7		T144	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T34	43		T43	15		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T274	8		T277	19		T185	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	5		T11	15		T180	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	5		T24	13		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T35	32		T106	16		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	1		T106	13		T50	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	7		T37	1		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	7		T38	11		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T6	2		T33	2		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T140	6		T36	2		T103	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2