Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25263

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3657

1

T3

2

T8

17

T9

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23128

1

T2

15

T3

2

T4

13

auto[1]

5792

1

T1

20

T3

1

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	247	1			T35	17		T139	1		T103	8
values[0]	47	1			T150	7		T257	27		T244	13
values[1]	707	1			T67	14		T26	1		T101	1
values[2]	2852	1			T1	20		T10	10		T34	46
values[3]	772	1			T3	1		T4	13		T110	1
values[4]	655	1			T35	17		T110	1		T103	16
values[5]	675	1			T26	1		T37	8		T38	1
values[6]	691	1			T6	1		T33	5		T27	12
values[7]	819	1			T5	11		T8	17		T11	30
values[8]	716	1			T3	2		T6	7		T9	6
values[9]	975	1			T7	7		T10	15		T139	1
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T10	10		T67	14		T139	1
values[1]	2827	1			T1	20		T4	13		T34	46
values[2]	659	1			T3	1		T110	1		T246	1
values[3]	679	1			T35	17		T110	1		T103	16
values[4]	680	1			T6	1		T26	1		T36	13
values[5]	771	1			T5	11		T11	30		T33	5
values[6]	717	1			T8	17		T110	1		T26	1
values[7]	872	1			T3	2		T6	7		T9	6
values[8]	886	1			T7	7		T35	17		T139	1
values[9]	61	1			T144	7		T218	17		T249	1
minimum	20008	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	1		T139	1		T12	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T67	1		T106	17		T39	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T1	2		T4	13		T34	46
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	1		T172	1		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T110	1		T154	13		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T246	1		T221	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T110	1		T106	28		T180	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T35	17		T103	16		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T37	4		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	1		T36	8		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T5	6		T11	16		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T33	5		T27	12		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T26	1		T151	1		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	6		T110	1		T133	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	1		T6	6		T9	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T3	1		T9	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	1		T24	14		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T35	17		T139	1		T12	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T144	5		T249	1		T250	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T218	9		T234	12		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19661	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T135	9		T137	1		T154	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	9		T12	9		T38	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T67	13		T39	3		T173	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T1	18		T107	21		T109	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T38	1		T172	16		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T285	1		T289	11		T252	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T221	7		T223	1		T301	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T180	12		T145	13		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T181	10		T229	14		T150	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	4		T15	1		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	5		T50	17		T164	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	5		T11	14		T180	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T136	14		T239	2		T165	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	13		T222	6		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T8	11		T133	8		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T14	7		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	1		T10	14		T32	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	6		T24	13		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T22	4		T105	14		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T144	2		T250	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T218	8		T234	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T150	6		T79	10		T328	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T141	1		T248	1		T244	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T35	17		T139	1		T103	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T257	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T150	1		T244	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	1		T101	1		T38	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T67	1		T106	17		T39	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T1	2		T10	1		T34	46
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T143	1		T152	1		T260	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	13		T110	1		T183	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T38	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T110	1		T106	28		T180	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T35	17		T103	16		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	4		T141	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T26	1		T38	1		T50	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T180	14		T16	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T33	5		T27	12		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	6		T11	16		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	6		T133	9		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T6	6		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T9	1		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T139	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T10	1		T12	4		T22	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T248	5		T250	3		T254	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T105	14		T180	14		T149	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T257	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T150	6		T244	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	12		T226	13		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T67	13		T39	3		T173	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T1	18		T10	9		T107	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T148	2		T258	7		T287	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T165	3		T237	13		T259	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T38	1		T172	16		T16	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T180	12		T145	13		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T181	10		T229	14		T150	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T37	4		T15	1		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	17		T221	2		T219	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T180	10		T16	6		T138	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T36	5		T164	3		T235	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	5		T11	14		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	11		T133	8		T136	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T14	7		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T38	2		T32	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	6		T24	13		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	14		T22	4		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	10		T139	1		T12	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T67	14		T106	1		T39	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T1	20		T4	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	2		T172	17		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T110	1		T154	1		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T246	1		T221	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T110	1		T106	2		T180	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	1		T103	1		T181	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	1		T37	7		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T26	1		T36	8		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	6		T11	15		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T33	3		T27	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T26	1		T151	1		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	12		T110	1		T133	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T6	5		T9	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	1		T9	2		T10	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	7		T24	14		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T35	1		T139	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T144	5		T249	1		T250	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T218	9		T234	16		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19810	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T135	1		T137	1		T154	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	5		T38	11		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T106	16		T39	3		T173	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T4	12		T34	43		T43	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T16	2		T148	2		T163	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T154	12		T285	1		T289	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T221	10		T185	30		T262	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T106	26		T180	10		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T35	16		T103	15		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	1		T15	2		T16	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T36	5		T50	16		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	5		T11	15		T27	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T33	2		T27	11		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T32	12		T222	6		T149	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	5		T133	8		T135	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	2		T9	1		T14	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T162	9		T32	22		T163	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	13		T36	2		T153	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T35	16		T12	3		T103	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T144	2		T250	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T218	8		T234	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T168	8		T255	11		T257	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T135	8		T154	14		T79	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T141	1		T248	6		T244	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T35	1		T139	1		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T257	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T150	7		T244	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	1		T101	1		T38	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T67	14		T106	1		T39	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T1	20		T10	10		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T143	1		T152	1		T260	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	1		T110	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T3	1		T38	2		T172	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T110	1		T106	2		T180	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	1		T103	1		T181	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T37	7		T141	1		T15	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	1		T38	1		T50	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T6	1		T180	11		T16	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T33	3		T27	1		T36	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	6		T11	15		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	12		T133	9		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T6	5		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T9	2		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	7		T139	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T10	15		T12	1		T22	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T250	2		T254	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T35	16		T103	7		T180	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T257	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T38	11		T157	2		T224	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T106	16		T39	3		T135	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T34	43		T43	15		T108	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T260	12		T148	2		T163	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	12		T183	9		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	2		T221	10		T185	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T106	26		T180	10		T148	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T35	16		T103	15		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	1		T15	2		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	16		T260	18		T221	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T180	13		T16	8		T138	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T33	2		T27	11		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	5		T11	15		T27	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	5		T133	8		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	2		T9	1		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T162	9		T32	6		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	13		T36	2		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	3		T142	11		T32	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2